1
|
SUDT ACCESSPORT LOG FILE - Monitor mode
|
2
|
|
3
|
Monitor: COM1
|
4
|
Create Time: 2016-12-01, 21:41:01
|
5
|
Computer Name: ?????F
|
6
|
System version: (Build 9200)
|
7
|
|
8
|
# Time Duration (s) Process Request Port Result Data ( Hex )
|
9
|
|
10
|
1 21:40:22.500 0.11692884 UV4BAND_E_CPS. IRP_MJ_CREATE COM1 SUCCESS Port Opened
|
11
|
2 21:40:22.625 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
12
|
3 21:40:22.625 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE COM1 SUCCESS InSize: 1024, OutSize: 512
|
13
|
4 21:40:22.625 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR
|
14
|
5 21:40:22.625 0.00000079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_TIMEOUTS COM1 SUCCESS ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000
|
15
|
6 21:40:22.625 0.06179953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_BAUD_RATE COM1 SUCCESS Baud Rate: 9600
|
16
|
7 21:40:22.625 0.06173869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
17
|
8 21:40:22.688 0.00054123 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_RTS COM1 SUCCESS
|
18
|
9 21:40:22.688 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
19
|
10 21:40:22.688 0.00194884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
20
|
11 21:40:22.688 0.00044128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_DTR COM1 SUCCESS
|
21
|
12 21:40:22.688 0.00043536 UV4BAND_E_CPS. IOCTL_SERIAL_SET_LINE_CONTROL COM1 SUCCESS StopBits: 1, Parity: No, DataBits: 8
|
22
|
13 21:40:22.688 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_CHARS COM1 SUCCESS EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13
|
23
|
14 21:40:22.688 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_HANDFLOW COM1 SUCCESS ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256
|
24
|
15 21:40:22.688 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask:
|
25
|
16 21:40:22.688 0.00027733 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_DTR COM1 SUCCESS
|
26
|
17 21:40:22.688 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR
|
27
|
18 21:40:22.688 0.05216950 UV4BAND_E_CPS. IRP_MJ_CLOSE COM1 SUCCESS Port Closed
|
28
|
19 21:40:22.734 0.11786158 UV4BAND_E_CPS. IRP_MJ_CREATE COM1 SUCCESS Port Opened
|
29
|
20 21:40:22.860 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
30
|
21 21:40:22.860 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE COM1 SUCCESS InSize: 1024, OutSize: 512
|
31
|
22 21:40:22.860 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR
|
32
|
23 21:40:22.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_TIMEOUTS COM1 SUCCESS ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000
|
33
|
24 21:40:22.860 0.06105128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_BAUD_RATE COM1 SUCCESS Baud Rate: 9600
|
34
|
25 21:40:22.860 0.06138985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
35
|
26 21:40:22.922 0.00037926 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_RTS COM1 SUCCESS
|
36
|
27 21:40:22.922 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_DTR COM1 SUCCESS
|
37
|
28 21:40:22.922 0.00125116 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
38
|
29 21:40:22.922 0.00045630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_LINE_CONTROL COM1 SUCCESS StopBits: 1, Parity: No, DataBits: 8
|
39
|
30 21:40:22.922 0.00035951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_CHARS COM1 SUCCESS EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13
|
40
|
31 21:40:22.922 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_HANDFLOW COM1 SUCCESS ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256
|
41
|
32 21:40:22.922 0.33480151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
42
|
33 21:40:22.922 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR
|
43
|
34 21:40:23.250 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55
|
44
|
35 21:40:23.250 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
45
|
36 21:40:23.250 0.00648455 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
46
|
37 21:40:23.266 0.00036820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20
|
47
|
38 21:40:23.266 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
48
|
39 21:40:23.266 0.01538094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
49
|
40 21:40:23.281 0.00031921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16
|
50
|
41 21:40:23.281 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
51
|
42 21:40:23.281 0.01566657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
52
|
43 21:40:23.297 0.00034094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08
|
53
|
44 21:40:23.297 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
54
|
45 21:40:23.297 0.01556465 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
55
|
46 21:40:23.313 0.00037610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01
|
56
|
47 21:40:23.313 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
57
|
48 21:40:23.313 0.01539793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
58
|
49 21:40:23.328 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF
|
59
|
50 21:40:23.328 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
60
|
51 21:40:23.328 0.01573848 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
61
|
52 21:40:23.344 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: DC
|
62
|
53 21:40:23.344 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
63
|
54 21:40:23.344 0.01537897 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
64
|
55 21:40:23.360 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02
|
65
|
56 21:40:23.360 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
66
|
57 21:40:23.360 0.00216296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
67
|
58 21:40:23.360 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
68
|
59 21:40:23.360 0.00683339 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
69
|
60 21:40:23.360 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
70
|
61 21:40:23.360 0.00598124 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
71
|
62 21:40:23.375 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
72
|
63 21:40:23.375 0.00981136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
73
|
64 21:40:23.375 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
74
|
65 21:40:23.375 0.00947121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
75
|
66 21:40:23.391 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
76
|
67 21:40:23.391 0.01001482 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
77
|
68 21:40:23.391 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
78
|
69 21:40:23.391 0.01010331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
79
|
70 21:40:23.407 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
80
|
71 21:40:23.407 0.00961028 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
81
|
72 21:40:23.422 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
82
|
73 21:40:23.422 0.00980978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
83
|
74 21:40:23.422 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
84
|
75 21:40:23.422 0.00981215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
85
|
76 21:40:23.438 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
86
|
77 21:40:23.438 0.00947240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
87
|
78 21:40:23.453 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
88
|
79 21:40:23.453 0.00976316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
89
|
80 21:40:23.453 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
90
|
81 21:40:23.453 0.01013097 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
91
|
82 21:40:23.469 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
92
|
83 21:40:23.469 0.00926894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
93
|
84 21:40:23.485 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
94
|
85 21:40:23.485 0.00985166 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
95
|
86 21:40:23.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
96
|
87 21:40:23.485 0.00992988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
97
|
88 21:40:23.500 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
98
|
89 21:40:23.500 0.00969403 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
99
|
90 21:40:23.516 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
100
|
91 21:40:23.516 0.01004445 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
101
|
92 21:40:23.516 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
102
|
93 21:40:23.516 0.00950440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
103
|
94 21:40:23.532 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
104
|
95 21:40:23.532 0.00990104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
105
|
96 21:40:23.532 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
106
|
97 21:40:23.532 0.01017126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
107
|
98 21:40:23.547 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
108
|
99 21:40:23.547 0.00940405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
109
|
100 21:40:23.563 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
110
|
101 21:40:23.563 0.00970272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
111
|
102 21:40:23.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
112
|
103 21:40:23.563 0.00989907 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
113
|
104 21:40:23.579 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
114
|
105 21:40:23.579 0.00973353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
115
|
106 21:40:23.594 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
116
|
107 21:40:23.594 0.00978805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
117
|
108 21:40:23.594 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
118
|
109 21:40:23.594 0.00979161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
119
|
110 21:40:23.610 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
120
|
111 21:40:23.610 0.00977897 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
121
|
112 21:40:23.626 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
122
|
113 21:40:23.626 0.01016692 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
123
|
115 21:40:23.626 0.00929107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
124
|
116 21:40:23.641 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
125
|
117 21:40:23.641 0.00976119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
126
|
118 21:40:23.641 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
127
|
119 21:40:23.641 0.01012030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
128
|
120 21:40:23.657 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
129
|
121 21:40:23.657 0.00925709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
130
|
122 21:40:23.672 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
131
|
123 21:40:23.672 0.00996860 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
132
|
124 21:40:23.672 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
133
|
125 21:40:23.672 0.00947674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
134
|
126 21:40:23.688 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
135
|
127 21:40:23.688 0.00961462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
136
|
128 21:40:23.704 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
137
|
129 21:40:23.704 0.00992830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
138
|
130 21:40:23.704 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
139
|
131 21:40:23.704 0.00954628 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
140
|
132 21:40:23.719 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
141
|
133 21:40:23.719 0.00982479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
142
|
134 21:40:23.735 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
143
|
135 21:40:23.735 0.01016850 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
144
|
136 21:40:23.735 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
145
|
137 21:40:23.735 0.00929107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
146
|
138 21:40:23.751 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
147
|
139 21:40:23.751 0.00965176 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
148
|
140 21:40:23.766 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
149
|
141 21:40:23.766 0.00995991 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
150
|
142 21:40:23.766 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
151
|
143 21:40:23.766 0.00986153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
152
|
144 21:40:23.782 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
153
|
145 21:40:23.782 0.00971418 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
154
|
146 21:40:23.782 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
155
|
147 21:40:23.782 0.00974855 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
156
|
148 21:40:23.797 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
157
|
149 21:40:23.797 0.00978173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
158
|
150 21:40:23.813 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
159
|
151 21:40:23.813 0.00995595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
160
|
152 21:40:23.813 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
161
|
153 21:40:23.813 0.00971141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
162
|
154 21:40:23.828 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
163
|
155 21:40:23.828 0.00964623 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
164
|
156 21:40:23.844 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
165
|
157 21:40:23.844 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06
|
166
|
158 21:40:23.844 0.01007013 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
167
|
159 21:40:23.844 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01
|
168
|
160 21:40:23.844 0.00004622 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03
|
169
|
161 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06
|
170
|
162 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01
|
171
|
163 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07
|
172
|
164 21:40:23.844 0.00012879 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04
|
173
|
165 21:40:23.844 0.00002568 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
174
|
166 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01
|
175
|
167 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
176
|
168 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
177
|
169 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20
|
178
|
170 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20
|
179
|
171 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20
|
180
|
172 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20
|
181
|
173 21:40:23.844 0.00009481 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20
|
182
|
174 21:40:23.844 0.00004662 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20
|
183
|
175 21:40:23.844 0.00008849 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02
|
184
|
176 21:40:23.844 0.00001106 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
185
|
177 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
186
|
178 21:40:23.844 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02
|
187
|
179 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07
|
188
|
180 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
189
|
181 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
190
|
182 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01
|
191
|
183 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
192
|
184 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
193
|
185 21:40:23.844 0.00005649 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 56
|
194
|
186 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 43
|
195
|
187 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32
|
196
|
188 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30
|
197
|
189 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30
|
198
|
190 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32
|
199
|
191 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04
|
200
|
192 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
201
|
193 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
202
|
194 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04
|
203
|
195 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 08
|
204
|
196 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
205
|
197 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
206
|
198 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01
|
207
|
199 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03
|
208
|
200 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 05
|
209
|
201 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
210
|
202 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03
|
211
|
203 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 09
|
212
|
204 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
213
|
205 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00
|
214
|
206 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01
|
215
|
207 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 55
|
216
|
208 21:40:23.844 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR
|
217
|
209 21:40:23.844 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING
|
218
|
210 21:40:23.844 0.04479449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS
|
219
|
211 21:40:23.891 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask:
|
220
|
212 21:40:23.891 0.00041798 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_DTR COM1 SUCCESS
|
221
|
213 21:40:23.891 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR
|
222
|
214 21:40:23.891 0.02377719 UV4BAND_E_CPS. IRP_MJ_CLOSE COM1 SUCCESS Port Closed
|