option write.txt

Option write Log - marco rossi, 12/01/2016 01:37 pm

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SUDT ACCESSPORT LOG FILE - Monitor mode
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Monitor: COM1
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Create Time: 2016-12-01, 21:49:32
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Computer Name: ??B??F
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System version:  (Build 9200)
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#	Time		Duration (s)	Process		Request                             	Port	Result	Data ( Hex )	
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1	21:48:56.219	0.14176559	UV4BAND_E_CPS.	IRP_MJ_CREATE                       	COM1	SUCCESS	Port Opened	
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2	21:48:56.375	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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3	21:48:56.375	0.00000119	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_QUEUE_SIZE         	COM1	SUCCESS	InSize: 1024, OutSize: 512	
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4	21:48:56.375	0.00007546	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1	SUCCESS	Purge: TXABORT RXABORT TXCLEAR RXCLEAR	
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5	21:48:56.375	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_TIMEOUTS           	COM1	SUCCESS	ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000	
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6	21:48:56.375	0.06112674	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_BAUD_RATE          	COM1	SUCCESS	Baud Rate: 9600	
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7	21:48:56.375	0.06116506	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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8	21:48:56.438	0.00060800	UV4BAND_E_CPS.	IOCTL_SERIAL_CLR_RTS                	COM1	SUCCESS		
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9	21:48:56.438	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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10	21:48:56.438	0.01579694	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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11	21:48:56.438	0.00040138	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_DTR                	COM1	SUCCESS		
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12	21:48:56.438	0.00046617	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_LINE_CONTROL       	COM1	SUCCESS	StopBits: 1, Parity: No, DataBits: 8	
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13	21:48:56.438	0.00030973	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_CHARS              	COM1	SUCCESS	EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13	
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14	21:48:56.438	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_HANDFLOW           	COM1	SUCCESS	ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256	
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15	21:48:56.438	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1		Purge: RXABORT RXCLEAR	
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16	21:48:56.438	0.00012365	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1	SUCCESS	Purge: RXABORT RXCLEAR	
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17	21:48:56.454	0.00023506	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 55 	
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18	21:48:56.454	0.00010469	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
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19	21:48:56.454	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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20	21:48:56.454	0.00002133	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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21	21:48:56.454	0.00007980	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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22	21:48:56.454	0.00013788	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 16 	
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23	21:48:56.454	0.00007822	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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24	21:48:56.454	0.00018410	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 08 	
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25	21:48:56.454	0.00028761	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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26	21:48:56.454	0.00025916	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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27	21:48:56.454	0.00028326	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
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28	21:48:56.454	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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29	21:48:56.454	0.00018805	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
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30	21:48:56.454	0.00008178	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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31	21:48:56.454	0.00010746	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: DC 	
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32	21:48:56.454	0.00007546	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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33	21:48:56.454	0.00002449	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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34	21:48:56.454	0.00001185	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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35	21:48:56.454	0.00014736	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
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36	21:48:56.454	0.00017580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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37	21:48:56.454	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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38	21:48:56.454	0.00751921	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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39	21:48:56.454	0.00006953	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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40	21:48:56.454	0.00799645	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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41	21:48:56.469	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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42	21:48:56.469	0.00953482	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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43	21:48:56.469	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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44	21:48:56.469	0.00992593	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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45	21:48:56.484	0.00002489	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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46	21:48:56.484	0.01044702	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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47	21:48:56.500	0.00001027	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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48	21:48:56.500	0.00915832	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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49	21:48:56.500	0.00003358	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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50	21:48:56.500	0.00972642	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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51	21:48:56.516	0.00012642	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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52	21:48:56.516	0.00952613	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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53	21:48:56.532	0.00000790	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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54	21:48:56.532	0.00991645	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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55	21:48:56.532	0.00000514	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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56	21:48:56.532	0.01003497	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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57	21:48:56.547	0.00002094	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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58	21:48:56.547	0.00966716	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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59	21:48:56.547	0.00000632	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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60	21:48:56.547	0.00970707	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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61	21:48:56.563	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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62	21:48:56.563	0.01027398	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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63	21:48:56.578	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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65	21:48:56.578	0.00000514	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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66	21:48:56.578	0.01005591	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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67	21:48:56.594	0.00017896	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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68	21:48:56.594	0.00947398	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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69	21:48:56.610	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
78
70	21:48:56.610	0.00996386	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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71	21:48:56.610	0.00010943	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
80
72	21:48:56.610	0.00978805	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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73	21:48:56.625	0.00008336	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
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74	21:48:56.625	0.00952455	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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75	21:48:56.641	0.00002291	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
84
76	21:48:56.641	0.00978173	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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77	21:48:56.641	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
86
78	21:48:56.641	0.01010410	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
87
79	21:48:56.657	0.00020978	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
88
81	21:48:56.672	0.00000632	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
89
82	21:48:56.672	0.00968139	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
90
83	21:48:56.672	0.00007388	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
91
84	21:48:56.672	0.01036129	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
92
85	21:48:56.688	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
93
86	21:48:56.688	0.00934400	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
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87	21:48:56.688	0.00002805	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
95
88	21:48:56.688	0.00970549	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
96
89	21:48:56.704	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
97
90	21:48:56.704	0.00990104	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
98
91	21:48:56.720	0.00000869	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
99
92	21:48:56.720	0.00965176	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
100
93	21:48:56.720	0.00015012	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
101
94	21:48:56.720	0.00978805	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
102
95	21:48:56.734	0.00001975	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
103
96	21:48:56.734	0.00963595	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
104
97	21:48:56.750	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
105
98	21:48:56.750	0.00991566	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
106
99	21:48:56.750	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
107
100	21:48:56.750	0.01018391	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
108
101	21:48:56.766	0.00000790	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
109
102	21:48:56.766	0.00944395	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
110
103	21:48:56.781	0.00000790	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
111
104	21:48:56.781	0.00982242	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
112
105	21:48:56.781	0.00012128	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
113
106	21:48:56.781	0.00978134	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
114
107	21:48:56.797	0.00000751	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
115
108	21:48:56.797	0.00992593	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
116
109	21:48:56.813	0.00013314	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
117
110	21:48:56.813	0.00964386	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
118
111	21:48:56.813	0.00020543	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
119
112	21:48:56.813	0.00945383	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
120
113	21:48:56.828	0.00019556	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
121
114	21:48:56.828	0.00967586	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
122
115	21:48:56.828	0.00000632	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
123
116	21:48:56.828	0.01010055	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
124
117	21:48:56.844	0.00016593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
125
118	21:48:56.844	0.00950282	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
126
119	21:48:56.860	0.00002686	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
127
120	21:48:56.860	0.00977028	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
128
121	21:48:56.860	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
129
122	21:48:56.860	0.01041778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
130
123	21:48:56.875	0.00017146	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
131
124	21:48:56.875	0.00928119	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
132
125	21:48:56.891	0.00002173	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
133
126	21:48:56.891	0.00968968	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
134
127	21:48:56.891	0.00000869	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
135
128	21:48:56.891	0.01001956	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
136
129	21:48:56.906	0.00000751	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
137
130	21:48:56.906	0.00969837	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
138
131	21:48:56.922	0.00011220	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
139
132	21:48:56.922	0.00993028	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
140
133	21:48:56.922	0.00002805	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
141
134	21:48:56.922	0.00974065	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
142
135	21:48:56.938	0.00000830	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
143
136	21:48:56.938	0.00953442	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
144
137	21:48:56.938	0.00002607	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
145
138	21:48:56.938	0.00178370	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
146
139	21:48:56.938	0.00000316	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
147
140	21:48:56.938	0.00010153	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 01 	
148
141	21:48:56.938	0.00000158	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 03 	
149
142	21:48:56.938	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
150
143	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 01 	
151
144	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 07 	
152
145	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 04 	
153
146	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
154
147	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 01 	
155
148	21:48:56.953	0.00014459	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
156
149	21:48:56.953	0.00000119	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
157
150	21:48:56.953	0.00003990	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
158
151	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
159
152	21:48:56.953	0.00003002	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
160
153	21:48:56.953	0.00000751	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
161
154	21:48:56.953	0.00002686	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
162
155	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
163
156	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 02 	
164
157	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
165
158	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
166
159	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 02 	
167
160	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 07 	
168
161	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
169
162	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
170
163	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 01 	
171
164	21:48:56.953	0.00003477	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
172
165	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
173
166	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 56 	
174
167	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 43 	
175
168	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 32 	
176
169	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 30 	
177
170	21:48:56.953	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 30 	
178
171	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 32 	
179
172	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 04 	
180
173	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
181
174	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
182
175	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 04 	
183
176	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 08 	
184
177	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
185
178	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
186
179	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 01 	
187
180	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 03 	
188
181	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 05 	
189
182	21:48:56.953	0.00000198	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
190
183	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 03 	
191
184	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 09 	
192
185	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
193
186	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
194
187	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 01 	
195
188	21:48:56.953	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 55 	
196
189	21:48:56.953	0.00001422	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1	SUCCESS	Purge: RXABORT RXCLEAR	
197
190	21:48:56.953	0.00030262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
198
191	21:48:56.953	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
199
192	21:48:56.953	0.00818963	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
200
193	21:48:56.953	0.00004346	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1	SUCCESS	Purge: RXABORT RXCLEAR	
201
194	21:48:56.953	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
202
195	21:48:56.953	0.00652524	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
203
196	21:48:56.969	0.00022321	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 53 	
204
197	21:48:56.969	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
205
198	21:48:56.969	0.00062775	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
206
199	21:48:56.969	0.00059299	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 3D 	
207
200	21:48:56.969	0.00021965	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: F0 	
208
201	21:48:56.969	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
209
202	21:48:56.969	0.00008415	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
210
203	21:48:56.969	0.00011694	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
211
204	21:48:56.969	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
212
205	21:48:56.969	0.00006479	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
213
206	21:48:56.969	0.00009798	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
214
207	21:48:56.969	0.08901416	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
215
208	21:48:57.047	0.00007230	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
216
209	21:48:57.047	0.00068701	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
217
210	21:48:57.047	0.00013867	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
218
211	21:48:57.047	0.00078222	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
219
212	21:48:57.047	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
220
213	21:48:57.047	0.00103783	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
221
214	21:48:57.062	0.00004346	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
222
215	21:48:57.062	0.00135151	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
223
216	21:48:57.062	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
224
217	21:48:57.062	0.00120296	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
225
218	21:48:57.062	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
226
219	21:48:57.062	0.00118479	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
227
220	21:48:57.062	0.00014775	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
228
221	21:48:57.062	0.00130015	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
229
222	21:48:57.062	0.00000514	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
230
223	21:48:57.062	0.00136849	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
231
224	21:48:57.062	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
232
225	21:48:57.062	0.00122232	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
233
226	21:48:57.062	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
234
227	21:48:57.062	0.00143486	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
235
228	21:48:57.062	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
236
229	21:48:57.062	0.00132267	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
237
230	21:48:57.062	0.00003121	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
238
231	21:48:57.062	0.00127803	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
239
232	21:48:57.062	0.00002410	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
240
233	21:48:57.062	0.00128158	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
241
234	21:48:57.062	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
242
235	21:48:57.062	0.00136731	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
243
236	21:48:57.078	0.00016711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
244
237	21:48:57.078	0.00143407	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
245
238	21:48:57.078	0.00001580	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
246
239	21:48:57.078	0.00099674	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
247
240	21:48:57.078	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
248
241	21:48:57.078	0.00132109	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
249
242	21:48:57.078	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
250
243	21:48:57.078	0.00137956	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
251
244	21:48:57.078	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
252
245	21:48:57.078	0.00086163	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
253
246	21:48:57.078	0.00000158	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 05 	
254
247	21:48:57.078	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 58 	
255
248	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 3D 	
256
249	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: F0 	
257
250	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 10 	
258
251	21:48:57.078	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
259
252	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
260
253	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
261
254	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
262
255	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
263
256	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
264
257	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
265
258	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
266
259	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
267
260	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
268
261	21:48:57.078	0.00000040	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
269
262	21:48:57.078	0.00001106	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 20 	
270
263	21:48:57.078	0.00000079	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
271
264	21:48:57.078	0.00011062	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
272
265	21:48:57.078	0.00003911	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
273
266	21:48:57.078	0.00010509	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1	SUCCESS	Purge: RXABORT RXCLEAR	
274
267	21:48:57.078	0.00011575	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
275
268	21:48:57.078	0.00001896	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
276
269	21:48:57.078	0.00030775	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
277
270	21:48:57.078	0.00004978	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
278
271	21:48:57.078	0.00163003	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
279
272	21:48:57.078	0.00000158	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 00 	
280
273	21:48:57.078	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
281
274	21:48:57.078	0.00585245	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
282
275	21:48:57.078	0.00006242	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
283
276	21:48:57.094	0.00024652	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
284
277	21:48:57.094	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
285
278	21:48:57.094	0.00028958	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
286
279	21:48:57.094	0.00023348	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
287
280	21:48:57.094	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
288
281	21:48:57.094	0.00026509	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
289
282	21:48:57.094	0.00022835	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
290
283	21:48:57.094	0.00001738	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
291
284	21:48:57.094	0.00043615	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
292
285	21:48:57.094	0.00036464	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
293
289	21:48:57.094	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
294
290	21:48:57.094	0.00031328	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
295
291	21:48:57.094	0.00021333	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
296
292	21:48:57.094	0.00026232	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
297
293	21:48:57.094	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
298
294	21:48:57.094	0.00018528	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
299
295	21:48:57.094	0.00019437	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
300
296	21:48:57.094	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
301
297	21:48:57.094	0.00016079	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
302
298	21:48:57.094	0.00016474	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
303
299	21:48:57.094	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
304
300	21:48:57.094	0.00001778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
305
301	21:48:57.094	0.00013432	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
306
302	21:48:57.094	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
307
303	21:48:57.094	0.00007506	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
308
304	21:48:57.094	0.00012326	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
309
305	21:48:57.094	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
310
306	21:48:57.094	0.00005136	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
311
307	21:48:57.094	0.00013630	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
312
308	21:48:57.094	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
313
309	21:48:57.094	0.00008731	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
314
310	21:48:57.094	0.00008691	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
315
311	21:48:57.094	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
316
312	21:48:57.094	0.00005136	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
317
313	21:48:57.094	0.00010469	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
318
314	21:48:57.094	0.00004662	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
319
315	21:48:57.094	0.00006440	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
320
316	21:48:57.094	0.00010983	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
321
317	21:48:57.094	0.00004780	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
322
318	21:48:57.094	0.00008375	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
323
319	21:48:57.094	0.00008415	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
324
320	21:48:57.094	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
325
321	21:48:57.094	0.00004701	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
326
322	21:48:57.094	0.00012721	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
327
323	21:48:57.094	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
328
324	21:48:57.094	0.00008099	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
329
325	21:48:57.094	0.00031447	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
330
326	21:48:57.094	0.00022953	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
331
327	21:48:57.094	0.00011773	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
332
328	21:48:57.094	0.00005728	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
333
329	21:48:57.094	0.00018686	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
334
331	21:48:57.094	0.00001975	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
335
332	21:48:57.094	0.00010943	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
336
333	21:48:57.094	0.00013590	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
337
334	21:48:57.094	0.00017817	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
338
335	21:48:57.094	0.00011378	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
339
336	21:48:57.094	0.00002015	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
340
337	21:48:57.094	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
341
338	21:48:57.094	0.07290116	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
342
339	21:48:57.172	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
343
340	21:48:57.172	0.01555872	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
344
341	21:48:57.172	0.00000277	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
345
342	21:48:57.188	0.00034331	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
346
343	21:48:57.188	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
347
344	21:48:57.188	0.00021452	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
348
345	21:48:57.188	0.00015921	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
349
346	21:48:57.188	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
350
347	21:48:57.188	0.00024415	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
351
348	21:48:57.188	0.00018449	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
352
349	21:48:57.188	0.00029393	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
353
350	21:48:57.188	0.00024494	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
354
351	21:48:57.188	0.00003002	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
355
352	21:48:57.188	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
356
353	21:48:57.188	0.00025442	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
357
354	21:48:57.188	0.00021017	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
358
355	21:48:57.188	0.00017817	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
359
356	21:48:57.188	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
360
357	21:48:57.188	0.00011694	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
361
358	21:48:57.188	0.00012760	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
362
359	21:48:57.188	0.00005531	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
363
360	21:48:57.188	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
364
361	21:48:57.188	0.00023467	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
365
362	21:48:57.188	0.00000988	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
366
363	21:48:57.188	0.00021807	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
367
364	21:48:57.188	0.00001146	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
368
365	21:48:57.188	0.00016751	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
369
366	21:48:57.188	0.00015526	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
370
367	21:48:57.188	0.00004030	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
371
368	21:48:57.188	0.00021689	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
372
370	21:48:57.188	0.00003832	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
373
371	21:48:57.188	0.00016790	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
374
372	21:48:57.188	0.00018963	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
375
373	21:48:57.188	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
376
374	21:48:57.188	0.00017699	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
377
375	21:48:57.188	0.00014538	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
378
376	21:48:57.188	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
379
377	21:48:57.188	0.00043259	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
380
378	21:48:57.188	0.00029077	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
381
379	21:48:57.188	0.00012286	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
382
380	21:48:57.188	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
383
381	21:48:57.188	0.00006953	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
384
382	21:48:57.188	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
385
383	21:48:57.188	0.00023427	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
386
384	21:48:57.188	0.00020583	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
387
385	21:48:57.188	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
388
386	21:48:57.188	0.00021847	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
389
387	21:48:57.188	0.00023783	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
390
388	21:48:57.188	0.00002765	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
391
389	21:48:57.188	0.00017422	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
392
390	21:48:57.188	0.00010232	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
393
391	21:48:57.188	0.00016711	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
394
392	21:48:57.188	0.00008415	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
395
393	21:48:57.188	0.00004622	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
396
394	21:48:57.188	0.00010311	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
397
395	21:48:57.188	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
398
396	21:48:57.188	0.00009798	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
399
397	21:48:57.188	0.00011536	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
400
398	21:48:57.188	0.00002647	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
401
399	21:48:57.188	0.00011773	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
402
400	21:48:57.188	0.00009560	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
403
401	21:48:57.188	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
404
402	21:48:57.188	0.00006281	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
405
403	21:48:57.188	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
406
404	21:48:57.188	0.02619063	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
407
405	21:48:57.219	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
408
406	21:48:57.219	0.01458450	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
409
407	21:48:57.219	0.00000316	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
410
408	21:48:57.235	0.00024810	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
411
409	21:48:57.235	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
412
410	21:48:57.235	0.00029353	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
413
411	21:48:57.235	0.00020938	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
414
412	21:48:57.235	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
415
413	21:48:57.235	0.00030657	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
416
414	21:48:57.235	0.00024612	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
417
415	21:48:57.235	0.00034173	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
418
416	21:48:57.235	0.00023072	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
419
417	21:48:57.235	0.00013393	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
420
418	21:48:57.235	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
421
419	21:48:57.235	0.00022281	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
422
420	21:48:57.235	0.00025126	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
423
421	21:48:57.235	0.00016198	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
424
422	21:48:57.235	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
425
423	21:48:57.235	0.00012563	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
426
424	21:48:57.235	0.00013551	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
427
425	21:48:57.235	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
428
426	21:48:57.235	0.00007230	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
429
427	21:48:57.235	0.00014815	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
430
428	21:48:57.235	0.00007585	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
431
429	21:48:57.235	0.00006756	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
432
430	21:48:57.235	0.00012049	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
433
431	21:48:57.235	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
434
432	21:48:57.235	0.00005531	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
435
433	21:48:57.235	0.00027536	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
436
434	21:48:57.235	0.00015447	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
437
435	21:48:57.235	0.00012049	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
438
436	21:48:57.235	0.00000751	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
439
437	21:48:57.235	0.00019319	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
440
438	21:48:57.235	0.00015961	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
441
439	21:48:57.235	0.00017343	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
442
440	21:48:57.235	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
443
441	21:48:57.235	0.00008889	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
444
442	21:48:57.235	0.00017896	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 04 	
445
443	21:48:57.235	0.00008810	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
446
444	21:48:57.235	0.00009916	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
447
445	21:48:57.235	0.00011101	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
448
446	21:48:57.235	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
449
447	21:48:57.235	0.00001264	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
450
448	21:48:57.235	0.00008217	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 04 	
451
449	21:48:57.235	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
452
450	21:48:57.235	0.00005017	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
453
451	21:48:57.235	0.00011654	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
454
452	21:48:57.235	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
455
453	21:48:57.235	0.00008691	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
456
454	21:48:57.235	0.00015447	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
457
455	21:48:57.235	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
458
456	21:48:57.235	0.00007348	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
459
457	21:48:57.235	0.00007348	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
460
458	21:48:57.235	0.00025047	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
461
459	21:48:57.235	0.00016474	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
462
460	21:48:57.235	0.00028049	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
463
461	21:48:57.235	0.00029946	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
464
462	21:48:57.235	0.00003674	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
465
463	21:48:57.235	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
466
464	21:48:57.235	0.00019319	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
467
465	21:48:57.235	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
468
466	21:48:57.235	0.00004188	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
469
467	21:48:57.235	0.00014578	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
470
468	21:48:57.235	0.00014459	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
471
469	21:48:57.235	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
472
470	21:48:57.235	0.02712692	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
473
471	21:48:57.266	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
474
472	21:48:57.266	0.01437354	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
475
473	21:48:57.266	0.00000237	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
476
474	21:48:57.282	0.00052622	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
477
475	21:48:57.282	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
478
476	21:48:57.282	0.00034133	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
479
477	21:48:57.282	0.00017659	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
480
478	21:48:57.282	0.00000553	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
481
479	21:48:57.282	0.00026272	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
482
480	21:48:57.282	0.00021215	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
483
481	21:48:57.282	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
484
482	21:48:57.282	0.00013748	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 30 	
485
483	21:48:57.282	0.00019358	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
486
484	21:48:57.282	0.00002252	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
487
485	21:48:57.282	0.00017580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
488
486	21:48:57.282	0.00013274	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
489
487	21:48:57.282	0.00020069	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
490
488	21:48:57.282	0.00005886	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
491
489	21:48:57.282	0.00013867	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
492
490	21:48:57.282	0.00017343	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
493
491	21:48:57.282	0.00000909	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
494
492	21:48:57.282	0.00016356	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
495
493	21:48:57.282	0.00003002	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
496
494	21:48:57.282	0.00019240	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
497
495	21:48:57.282	0.00014617	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
498
496	21:48:57.282	0.00012484	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
499
497	21:48:57.282	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
500
498	21:48:57.282	0.00008968	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
501
499	21:48:57.282	0.00012286	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0A 	
502
500	21:48:57.282	0.00005333	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
503
501	21:48:57.282	0.00006519	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
504
502	21:48:57.282	0.00016909	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
505
503	21:48:57.282	0.00011654	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
506
504	21:48:57.282	0.00006519	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
507
505	21:48:57.282	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
508
506	21:48:57.282	0.00018252	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
509
507	21:48:57.282	0.00020504	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
510
508	21:48:57.282	0.00011931	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
511
509	21:48:57.282	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
512
510	21:48:57.282	0.00006321	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
513
511	21:48:57.282	0.00009837	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 14 	
514
512	21:48:57.282	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
515
513	21:48:57.282	0.00005768	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
516
514	21:48:57.282	0.00008691	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
517
515	21:48:57.282	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
518
516	21:48:57.282	0.00004780	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
519
517	21:48:57.282	0.00009600	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
520
518	21:48:57.282	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
521
519	21:48:57.282	0.00001778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
522
520	21:48:57.282	0.00009442	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
523
521	21:48:57.282	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
524
522	21:48:57.282	0.00008099	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
525
523	21:48:57.282	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
526
524	21:48:57.282	0.00021570	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
527
525	21:48:57.282	0.00021294	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
528
526	21:48:57.282	0.00012800	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
529
527	21:48:57.282	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
530
528	21:48:57.282	0.00012207	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
531
529	21:48:57.282	0.00010904	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
532
530	21:48:57.282	0.00001896	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
533
531	21:48:57.282	0.00001462	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
534
532	21:48:57.282	0.00010509	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
535
533	21:48:57.282	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
536
534	21:48:57.282	0.00009323	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
537
535	21:48:57.282	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
538
536	21:48:57.282	0.02834134	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
539
537	21:48:57.313	0.00003240	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
540
538	21:48:57.313	0.01279921	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
541
539	21:48:57.313	0.00004385	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
542
540	21:48:57.328	0.00026114	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
543
541	21:48:57.328	0.00006123	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
544
542	21:48:57.328	0.00071822	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
545
543	21:48:57.328	0.00025916	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
546
544	21:48:57.328	0.00023783	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
547
545	21:48:57.328	0.00013314	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
548
546	21:48:57.328	0.00014578	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
549
547	21:48:57.328	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
550
548	21:48:57.328	0.00034291	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 40 	
551
549	21:48:57.328	0.00022242	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
552
550	21:48:57.328	0.00016711	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
553
551	21:48:57.328	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
554
552	21:48:57.328	0.00012800	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
555
553	21:48:57.328	0.00016751	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
556
554	21:48:57.328	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
557
555	21:48:57.328	0.00011773	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
558
556	21:48:57.328	0.00013827	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
559
557	21:48:57.328	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
560
558	21:48:57.328	0.00011773	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
561
559	21:48:57.328	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
562
560	21:48:57.328	0.00026588	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
563
561	21:48:57.328	0.00025007	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
564
562	21:48:57.328	0.00018923	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
565
563	21:48:57.328	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
566
564	21:48:57.328	0.00003911	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
567
565	21:48:57.328	0.00010864	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
568
566	21:48:57.328	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
569
567	21:48:57.328	0.00005373	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
570
568	21:48:57.328	0.00007467	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
571
569	21:48:57.328	0.00012840	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
572
570	21:48:57.328	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
573
571	21:48:57.328	0.00026272	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
574
572	21:48:57.328	0.00013946	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
575
573	21:48:57.328	0.00014499	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
576
574	21:48:57.328	0.00008810	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
577
575	21:48:57.328	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
578
576	21:48:57.328	0.00005057	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
579
577	21:48:57.328	0.00015289	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
580
578	21:48:57.328	0.00013709	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
581
579	21:48:57.328	0.00006163	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
582
580	21:48:57.328	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
583
581	21:48:57.328	0.00013827	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
584
582	21:48:57.328	0.00011575	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
585
583	21:48:57.328	0.00004820	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
586
584	21:48:57.328	0.00028681	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
587
585	21:48:57.328	0.00015921	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
588
586	21:48:57.328	0.00010390	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
589
587	21:48:57.328	0.00002607	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
590
588	21:48:57.328	0.00007506	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
591
589	21:48:57.328	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
592
590	21:48:57.328	0.00016948	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
593
591	21:48:57.328	0.00009600	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
594
592	21:48:57.328	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
595
593	21:48:57.328	0.00001975	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
596
594	21:48:57.328	0.00006914	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
597
595	21:48:57.328	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
598
596	21:48:57.328	0.00018291	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
599
597	21:48:57.328	0.00021452	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
600
598	21:48:57.328	0.00024178	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
601
599	21:48:57.328	0.00007269	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
602
600	21:48:57.328	0.00013748	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
603
601	21:48:57.328	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
604
602	21:48:57.328	0.02590737	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
605
603	21:48:57.359	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
606
604	21:48:57.359	0.01455210	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
607
605	21:48:57.359	0.00001225	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
608
606	21:48:57.375	0.00018410	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
609
607	21:48:57.375	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
610
608	21:48:57.375	0.00018489	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
611
609	21:48:57.375	0.00014025	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
612
610	21:48:57.375	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
613
611	21:48:57.375	0.00013353	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
614
612	21:48:57.375	0.00011812	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
615
613	21:48:57.375	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
616
614	21:48:57.375	0.00019635	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
617
615	21:48:57.375	0.00015210	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 50 	
618
616	21:48:57.375	0.00000869	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
619
617	21:48:57.375	0.00021491	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
620
618	21:48:57.375	0.00019081	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
621
619	21:48:57.375	0.00009995	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
622
620	21:48:57.375	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
623
621	21:48:57.375	0.00013235	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
624
622	21:48:57.375	0.00018015	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
625
623	21:48:57.375	0.00004227	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
626
624	21:48:57.375	0.00009205	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
627
625	21:48:57.375	0.00014341	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
628
626	21:48:57.375	0.00004780	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
629
627	21:48:57.375	0.00014025	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
630
628	21:48:57.375	0.00015131	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
631
629	21:48:57.375	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
632
630	21:48:57.375	0.00002686	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
633
631	21:48:57.375	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
634
632	21:48:57.375	0.00016079	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
635
633	21:48:57.375	0.00012879	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
636
634	21:48:57.375	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
637
635	21:48:57.375	0.00016672	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
638
636	21:48:57.375	0.00010904	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
639
637	21:48:57.375	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
640
638	21:48:57.375	0.00022519	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
641
639	21:48:57.375	0.00013630	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
642
640	21:48:57.375	0.00007743	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
643
641	21:48:57.375	0.00029906	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
644
642	21:48:57.375	0.00017067	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
645
643	21:48:57.375	0.00012365	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
646
644	21:48:57.375	0.00020701	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
647
645	21:48:57.375	0.00038005	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
648
646	21:48:57.375	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
649
647	21:48:57.375	0.00019753	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
650
648	21:48:57.375	0.00019358	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
651
649	21:48:57.375	0.00011101	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
652
650	21:48:57.375	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
653
651	21:48:57.375	0.00009007	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
654
652	21:48:57.375	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
655
653	21:48:57.375	0.00023704	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
656
654	21:48:57.375	0.00027220	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
657
655	21:48:57.375	0.00018844	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
658
656	21:48:57.375	0.00006558	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
659
657	21:48:57.375	0.00009126	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
660
658	21:48:57.375	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
661
659	21:48:57.375	0.00020069	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
662
660	21:48:57.375	0.00016119	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
663
661	21:48:57.375	0.00004425	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
664
662	21:48:57.375	0.00013590	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
665
663	21:48:57.375	0.00015802	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
666
664	21:48:57.375	0.00026114	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
667
665	21:48:57.375	0.00015091	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
668
666	21:48:57.375	0.00012089	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
669
667	21:48:57.375	0.00003319	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
670
668	21:48:57.375	0.02700446	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
671
669	21:48:57.406	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
672
670	21:48:57.406	0.01344593	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
673
671	21:48:57.406	0.00001264	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
674
672	21:48:57.422	0.00029511	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
675
673	21:48:57.422	0.00003002	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
676
674	21:48:57.422	0.00022479	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
677
675	21:48:57.422	0.00019121	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
678
676	21:48:57.422	0.00017580	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
679
677	21:48:57.422	0.00013393	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
680
678	21:48:57.422	0.00002489	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
681
679	21:48:57.422	0.00028405	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 60 	
682
680	21:48:57.422	0.00001896	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
683
681	21:48:57.422	0.00025561	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
684
682	21:48:57.422	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
685
683	21:48:57.422	0.00014736	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
686
684	21:48:57.422	0.00022914	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
687
685	21:48:57.422	0.00015723	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
688
686	21:48:57.422	0.00013037	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
689
687	21:48:57.422	0.00005965	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
690
688	21:48:57.422	0.00015802	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
691
689	21:48:57.422	0.00004741	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
692
690	21:48:57.422	0.00016158	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
693
691	21:48:57.422	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
694
692	21:48:57.422	0.00028010	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
695
693	21:48:57.422	0.00018726	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
696
694	21:48:57.422	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
697
695	21:48:57.422	0.00016751	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
698
696	21:48:57.422	0.00021017	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
699
697	21:48:57.422	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
700
698	21:48:57.422	0.00022361	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
701
699	21:48:57.422	0.00013432	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
702
700	21:48:57.422	0.00002331	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
703
701	21:48:57.422	0.00019635	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
704
702	21:48:57.422	0.00013116	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
705
703	21:48:57.422	0.00017146	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
706
704	21:48:57.422	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
707
705	21:48:57.422	0.00016435	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
708
706	21:48:57.422	0.00017501	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
709
707	21:48:57.422	0.00015921	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
710
708	21:48:57.422	0.00002884	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
711
712	21:48:57.422	0.00022202	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
712
713	21:48:57.422	0.00009798	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
713
714	21:48:57.422	0.00002607	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
714
715	21:48:57.422	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
715
716	21:48:57.422	0.00024178	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
716
717	21:48:57.422	0.00019081	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
717
718	21:48:57.422	0.00022321	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
718
719	21:48:57.422	0.00009481	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
719
720	21:48:57.422	0.00016198	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
720
721	21:48:57.422	0.00020938	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
721
722	21:48:57.422	0.00002054	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
722
723	21:48:57.422	0.00015289	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
723
724	21:48:57.422	0.00023941	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
724
725	21:48:57.422	0.00011852	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
725
726	21:48:57.422	0.00007388	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
726
727	21:48:57.422	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
727
728	21:48:57.422	0.00019319	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
728
729	21:48:57.422	0.00013077	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
729
730	21:48:57.422	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
730
731	21:48:57.422	0.00017778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
731
732	21:48:57.422	0.00015921	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
732
733	21:48:57.422	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
733
734	21:48:57.422	0.02683300	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
734
735	21:48:57.453	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
735
736	21:48:57.453	0.01351388	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
736
737	21:48:57.453	0.00000237	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
737
738	21:48:57.469	0.00026785	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
738
739	21:48:57.469	0.00011022	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
739
740	21:48:57.469	0.00021175	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
740
741	21:48:57.469	0.00016909	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
741
742	21:48:57.469	0.00016119	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
742
743	21:48:57.469	0.00011694	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
743
744	21:48:57.469	0.00003160	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
744
745	21:48:57.469	0.00004030	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
745
746	21:48:57.469	0.00024178	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
746
747	21:48:57.469	0.00018015	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 70 	
747
748	21:48:57.469	0.00020188	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
748
749	21:48:57.469	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
749
750	21:48:57.469	0.00013946	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
750
751	21:48:57.469	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
751
752	21:48:57.469	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
752
753	21:48:57.469	0.00005610	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
753
754	21:48:57.469	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
754
755	21:48:57.469	0.00015052	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
755
756	21:48:57.469	0.00010430	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
756
757	21:48:57.469	0.00012405	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
757
758	21:48:57.469	0.00003160	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
758
759	21:48:57.469	0.00011615	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
759
760	21:48:57.469	0.00011338	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
760
761	21:48:57.469	0.00005610	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
761
762	21:48:57.469	0.00007862	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
762
763	21:48:57.469	0.00011496	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
763
764	21:48:57.469	0.00013511	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
764
765	21:48:57.469	0.00005254	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
765
766	21:48:57.469	0.00022044	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
766
767	21:48:57.469	0.00001541	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
767
768	21:48:57.469	0.00013353	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
768
769	21:48:57.469	0.00011575	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
769
770	21:48:57.469	0.00006281	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
770
771	21:48:57.469	0.00003832	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
771
773	21:48:57.469	0.00018015	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
772
774	21:48:57.469	0.00015091	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
773
775	21:48:57.469	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
774
776	21:48:57.469	0.00013314	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
775
777	21:48:57.469	0.00015842	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
776
778	21:48:57.469	0.00009323	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
777
779	21:48:57.469	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
778
780	21:48:57.469	0.00005017	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
779
781	21:48:57.469	0.00009244	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
780
782	21:48:57.469	0.00003160	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
781
783	21:48:57.469	0.00007546	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
782
784	21:48:57.469	0.00008928	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
783
785	21:48:57.469	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
784
786	21:48:57.469	0.00005175	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
785
787	21:48:57.469	0.00008612	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
786
788	21:48:57.469	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
787
789	21:48:57.469	0.00005175	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
788
790	21:48:57.469	0.00013590	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
789
791	21:48:57.469	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
790
792	21:48:57.469	0.00009442	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
791
793	21:48:57.469	0.00009007	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
792
794	21:48:57.469	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
793
795	21:48:57.469	0.00005175	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
794
796	21:48:57.469	0.00007862	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
795
797	21:48:57.469	0.00009798	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
796
798	21:48:57.469	0.00006242	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
797
799	21:48:57.469	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
798
800	21:48:57.469	0.02717670	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
799
801	21:48:57.500	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
800
802	21:48:57.500	0.01474924	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
801
803	21:48:57.500	0.00001422	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
802
804	21:48:57.516	0.00026074	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
803
805	21:48:57.516	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
804
806	21:48:57.516	0.00026390	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
805
807	21:48:57.516	0.00022479	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
806
808	21:48:57.516	0.00023111	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
807
809	21:48:57.516	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
808
810	21:48:57.516	0.00010035	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
809
811	21:48:57.516	0.00026904	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 80 	
810
812	21:48:57.516	0.00003200	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
811
813	21:48:57.516	0.00021333	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
812
814	21:48:57.516	0.00002370	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
813
815	21:48:57.516	0.00025758	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
814
816	21:48:57.516	0.00020227	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
815
817	21:48:57.516	0.00016000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
816
818	21:48:57.516	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
817
819	21:48:57.516	0.00009007	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
818
820	21:48:57.516	0.00016000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
819
821	21:48:57.516	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
820
822	21:48:57.516	0.00010035	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
821
823	21:48:57.516	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
822
824	21:48:57.516	0.00014222	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
823
825	21:48:57.516	0.00017501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
824
826	21:48:57.516	0.00021649	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: C8 	
825
827	21:48:57.516	0.00006479	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
826
828	21:48:57.516	0.00016474	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
827
829	21:48:57.516	0.00025561	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 1F 	
828
830	21:48:57.516	0.00016316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
829
831	21:48:57.516	0.00009956	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
830
832	21:48:57.516	0.00018607	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
831
833	21:48:57.516	0.00006202	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
832
834	21:48:57.516	0.00015565	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
833
835	21:48:57.516	0.00013590	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
834
836	21:48:57.516	0.00015012	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
835
837	21:48:57.516	0.00014025	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
836
838	21:48:57.516	0.00011773	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
837
839	21:48:57.516	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
838
840	21:48:57.516	0.00004030	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
839
841	21:48:57.516	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
840
842	21:48:57.516	0.00015605	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
841
843	21:48:57.516	0.00010311	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
842
844	21:48:57.516	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
843
845	21:48:57.516	0.00027852	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
844
846	21:48:57.516	0.00028602	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
845
847	21:48:57.516	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
846
848	21:48:57.516	0.00029077	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
847
849	21:48:57.516	0.00022914	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
848
850	21:48:57.516	0.00024296	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
849
851	21:48:57.516	0.00005531	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
850
852	21:48:57.516	0.00013472	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
851
853	21:48:57.516	0.00022479	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
852
854	21:48:57.516	0.00007941	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
853
855	21:48:57.516	0.00014657	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
854
856	21:48:57.516	0.00022874	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
855
857	21:48:57.516	0.00008612	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
856
858	21:48:57.516	0.00014815	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
857
859	21:48:57.516	0.00022123	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
858
860	21:48:57.516	0.00010351	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
859
861	21:48:57.516	0.00012286	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
860
862	21:48:57.516	0.00011417	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
861
863	21:48:57.516	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
862
864	21:48:57.516	0.00001422	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
863
865	21:48:57.516	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
864
866	21:48:57.516	0.02683063	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
865
867	21:48:57.547	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
866
868	21:48:57.547	0.01406381	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
867
869	21:48:57.547	0.00001541	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
868
870	21:48:57.563	0.00028089	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
869
871	21:48:57.563	0.00000514	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
870
872	21:48:57.563	0.00022005	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
871
873	21:48:57.563	0.00018094	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
872
874	21:48:57.563	0.00027891	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
873
875	21:48:57.563	0.00005096	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
874
876	21:48:57.563	0.00024849	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
875
877	21:48:57.563	0.00025837	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 90 	
876
878	21:48:57.563	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
877
879	21:48:57.563	0.00015842	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
878
880	21:48:57.563	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
879
881	21:48:57.563	0.00033580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
880
882	21:48:57.563	0.00024770	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
881
883	21:48:57.563	0.00019595	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
882
884	21:48:57.563	0.00024415	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
883
885	21:48:57.563	0.00009402	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
884
886	21:48:57.563	0.00006084	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
885
887	21:48:57.563	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
886
888	21:48:57.563	0.00005136	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
887
889	21:48:57.563	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
888
890	21:48:57.563	0.00023388	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
889
891	21:48:57.563	0.00015012	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
890
892	21:48:57.563	0.00017106	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
891
893	21:48:57.563	0.00020543	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
892
894	21:48:57.563	0.00021254	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
893
895	21:48:57.563	0.00017501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
894
896	21:48:57.563	0.00014578	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
895
897	21:48:57.563	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
896
898	21:48:57.563	0.00001264	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
897
899	21:48:57.563	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
898
900	21:48:57.563	0.00004030	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
899
901	21:48:57.563	0.00000119	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
900
902	21:48:57.563	0.00022993	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
901
903	21:48:57.563	0.00016988	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
902
904	21:48:57.563	0.00010746	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
903
905	21:48:57.563	0.00033541	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
904
906	21:48:57.563	0.00013472	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
905
907	21:48:57.563	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
906
908	21:48:57.563	0.00020543	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
907
909	21:48:57.563	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
908
910	21:48:57.563	0.00012642	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
909
911	21:48:57.563	0.00002054	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
910
912	21:48:57.563	0.00009047	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
911
913	21:48:57.563	0.00013116	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
912
914	21:48:57.563	0.00008415	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
913
915	21:48:57.563	0.00009047	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
914
916	21:48:57.563	0.00001225	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
915
917	21:48:57.563	0.00016474	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
916
918	21:48:57.563	0.00012523	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
917
919	21:48:57.563	0.00019595	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
918
920	21:48:57.563	0.00012168	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
919
921	21:48:57.563	0.00008573	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
920
922	21:48:57.563	0.00016988	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
921
923	21:48:57.563	0.00020227	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
922
924	21:48:57.563	0.00003200	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
923
925	21:48:57.563	0.00013314	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
924
926	21:48:57.563	0.00002805	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
925
927	21:48:57.563	0.00008849	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
926
928	21:48:57.563	0.00012326	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
927
929	21:48:57.563	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
928
930	21:48:57.563	0.00001462	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
929
931	21:48:57.563	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
930
932	21:48:57.563	0.02692268	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
931
933	21:48:57.594	0.00000790	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
932
934	21:48:57.594	0.01334993	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
933
935	21:48:57.594	0.00001343	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
934
936	21:48:57.610	0.00017146	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
935
937	21:48:57.610	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
936
938	21:48:57.610	0.00021215	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
937
939	21:48:57.610	0.00019081	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
938
940	21:48:57.610	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
939
941	21:48:57.610	0.00021728	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
940
942	21:48:57.610	0.00016277	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
941
943	21:48:57.610	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
942
944	21:48:57.610	0.00036425	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: A0 	
943
945	21:48:57.610	0.00024533	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
944
946	21:48:57.610	0.00020622	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
945
947	21:48:57.610	0.00024731	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
946
948	21:48:57.610	0.00016909	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
947
949	21:48:57.610	0.00011338	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
948
950	21:48:57.610	0.00001264	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
949
951	21:48:57.610	0.00002410	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
950
952	21:48:57.610	0.00004780	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
951
953	21:48:57.610	0.00016790	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
952
954	21:48:57.610	0.00011180	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
953
955	21:48:57.610	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
954
956	21:48:57.610	0.00012326	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: C7 	
955
957	21:48:57.610	0.00013985	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
956
958	21:48:57.610	0.00012128	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
957
959	21:48:57.610	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
958
960	21:48:57.610	0.00005136	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
959
961	21:48:57.610	0.00011536	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
960
962	21:48:57.610	0.00010232	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
961
963	21:48:57.610	0.00005017	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
962
964	21:48:57.610	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
963
965	21:48:57.610	0.00013709	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
964
966	21:48:57.610	0.00009679	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
965
967	21:48:57.610	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
966
968	21:48:57.610	0.00013669	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
967
969	21:48:57.610	0.00013709	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
968
970	21:48:57.610	0.00011970	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
969
971	21:48:57.610	0.00003042	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
970
972	21:48:57.610	0.00006795	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
971
973	21:48:57.610	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
972
974	21:48:57.610	0.00016711	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
973
976	21:48:57.610	0.00014143	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
974
977	21:48:57.610	0.00021254	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
975
978	21:48:57.610	0.00028484	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
976
979	21:48:57.610	0.00016316	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
977
980	21:48:57.610	0.00026904	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
978
981	21:48:57.610	0.00006321	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
979
982	21:48:57.610	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
980
983	21:48:57.610	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
981
984	21:48:57.610	0.00019635	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
982
985	21:48:57.610	0.00010311	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
983
986	21:48:57.610	0.00011299	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
984
987	21:48:57.610	0.00012010	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
985
988	21:48:57.610	0.00002844	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
986
989	21:48:57.610	0.00011378	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
987
990	21:48:57.610	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
988
991	21:48:57.610	0.00008691	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
989
992	21:48:57.610	0.00010114	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
990
993	21:48:57.610	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
991
994	21:48:57.610	0.00006914	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
992
995	21:48:57.610	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
993
996	21:48:57.610	0.02933967	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
994
997	21:48:57.641	0.00000632	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
995
998	21:48:57.641	0.00004938	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
996
999	21:48:57.641	0.01191270	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
997
1000	21:48:57.657	0.00030617	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
998
1001	21:48:57.657	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
999
1002	21:48:57.657	0.00020701	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1000
1003	21:48:57.657	0.00015921	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1001
1004	21:48:57.657	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1002
1005	21:48:57.657	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1003
1006	21:48:57.657	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 0E 	
1004
1009	21:48:57.657	0.00027733	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1005
1010	21:48:57.657	0.00019319	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1006
1011	21:48:57.657	0.00020662	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1007
1012	21:48:57.657	0.00002528	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1008
1013	21:48:57.657	0.00021491	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1009
1014	21:48:57.657	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1010
1015	21:48:57.657	0.00012523	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1011
1016	21:48:57.657	0.00015961	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1012
1017	21:48:57.657	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1013
1018	21:48:57.657	0.00020346	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1014
1019	21:48:57.657	0.00019911	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1015
1020	21:48:57.657	0.00007862	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1016
1021	21:48:57.657	0.00013432	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1017
1022	21:48:57.657	0.00018805	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1018
1023	21:48:57.657	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1019
1024	21:48:57.657	0.00001304	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1020
1025	21:48:57.657	0.00018884	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1021
1026	21:48:57.657	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1022
1027	21:48:57.657	0.00008336	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1023
1028	21:48:57.657	0.00013235	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1024
1029	21:48:57.657	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1025
1030	21:48:57.657	0.00022716	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1026
1031	21:48:57.657	0.00002094	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1027
1032	21:48:57.657	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1028
1033	21:48:57.657	0.00014143	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1029
1034	21:48:57.657	0.00016672	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1030
1035	21:48:57.657	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1031
1036	21:48:57.657	0.00001778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1032
1037	21:48:57.657	0.00015565	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1033
1038	21:48:57.657	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1034
1039	21:48:57.657	0.00012089	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1035
1040	21:48:57.657	0.00020267	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1036
1041	21:48:57.657	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1037
1042	21:48:57.657	0.00015249	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1038
1043	21:48:57.657	0.00014025	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1039
1044	21:48:57.657	0.00009323	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1040
1045	21:48:57.657	0.00001422	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1041
1046	21:48:57.657	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1042
1047	21:48:57.657	0.00015763	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1043
1048	21:48:57.657	0.00011931	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1044
1049	21:48:57.657	0.00014301	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1045
1050	21:48:57.657	0.00009284	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1046
1051	21:48:57.657	0.00007980	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1047
1052	21:48:57.657	0.00001185	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1048
1053	21:48:57.657	0.00017580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1049
1054	21:48:57.657	0.00011654	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1050
1055	21:48:57.657	0.00021373	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1051
1056	21:48:57.657	0.00006440	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1052
1057	21:48:57.657	0.00012326	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1053
1058	21:48:57.657	0.00017185	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1054
1059	21:48:57.657	0.00006005	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1055
1060	21:48:57.657	0.00010667	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1056
1061	21:48:57.657	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1057
1062	21:48:57.657	0.02651418	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1058
1063	21:48:57.688	0.00000632	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1059
1064	21:48:57.688	0.01367151	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1060
1065	21:48:57.688	0.00000277	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1061
1066	21:48:57.703	0.00030380	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1062
1067	21:48:57.703	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1063
1068	21:48:57.703	0.00033422	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1064
1069	21:48:57.703	0.00028089	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1065
1070	21:48:57.703	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1066
1071	21:48:57.703	0.00042667	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1067
1072	21:48:57.703	0.00033778	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
1068
1073	21:48:57.703	0.00017383	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: C0 	
1069
1074	21:48:57.703	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1070
1075	21:48:57.703	0.00018647	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1071
1076	21:48:57.703	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1072
1077	21:48:57.703	0.00031131	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1073
1078	21:48:57.703	0.00033422	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1074
1079	21:48:57.703	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1075
1080	21:48:57.703	0.00046025	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1076
1081	21:48:57.703	0.00033146	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1077
1082	21:48:57.703	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1078
1083	21:48:57.703	0.00018212	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1079
1084	21:48:57.703	0.00025481	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1080
1085	21:48:57.703	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1081
1086	21:48:57.703	0.00017501	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1082
1087	21:48:57.703	0.00020741	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1083
1088	21:48:57.703	0.00022440	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1084
1089	21:48:57.703	0.00015526	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1085
1090	21:48:57.703	0.00011259	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1086
1091	21:48:57.703	0.00021610	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1087
1092	21:48:57.703	0.00006440	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1088
1093	21:48:57.703	0.00011496	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1089
1094	21:48:57.703	0.00015052	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1090
1095	21:48:57.703	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1091
1096	21:48:57.703	0.00008138	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1092
1097	21:48:57.703	0.00020622	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1093
1098	21:48:57.703	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1094
1099	21:48:57.703	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1095
1100	21:48:57.703	0.00018015	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1096
1101	21:48:57.703	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1097
1102	21:48:57.703	0.00017778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1098
1103	21:48:57.703	0.00022598	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1099
1104	21:48:57.703	0.00007032	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1100
1105	21:48:57.703	0.00010469	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1101
1106	21:48:57.703	0.00013353	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1102
1107	21:48:57.703	0.00006637	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1103
1108	21:48:57.703	0.00004227	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1104
1109	21:48:57.703	0.00015131	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1105
1110	21:48:57.703	0.00008375	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1106
1111	21:48:57.703	0.00009323	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1107
1112	21:48:57.703	0.00016988	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1108
1113	21:48:57.703	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1109
1114	21:48:57.703	0.00016119	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1110
1115	21:48:57.703	0.00031249	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1111
1116	21:48:57.703	0.00015131	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1112
1117	21:48:57.703	0.00020938	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1113
1118	21:48:57.703	0.00016119	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1114
1119	21:48:57.703	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1115
1120	21:48:57.703	0.00001580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1116
1121	21:48:57.703	0.00022202	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1117
1122	21:48:57.703	0.00013432	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1118
1123	21:48:57.703	0.00007467	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1119
1124	21:48:57.703	0.00016040	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1120
1125	21:48:57.703	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1121
1126	21:48:57.703	0.00012642	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1122
1127	21:48:57.703	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1123
1128	21:48:57.703	0.02652525	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1124
1129	21:48:57.734	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1125
1130	21:48:57.734	0.01337640	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1126
1131	21:48:57.734	0.00001304	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1127
1132	21:48:57.750	0.00035002	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1128
1133	21:48:57.750	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1129
1134	21:48:57.750	0.00032237	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1130
1135	21:48:57.750	0.00025165	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1131
1136	21:48:57.750	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1132
1137	21:48:57.750	0.00026864	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1133
1138	21:48:57.750	0.00021017	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
1134
1139	21:48:57.750	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1135
1140	21:48:57.750	0.00029630	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: D0 	
1136
1141	21:48:57.750	0.00032632	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1137
1142	21:48:57.750	0.00002923	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1138
1143	21:48:57.750	0.00030143	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1139
1144	21:48:57.750	0.00019753	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1140
1145	21:48:57.750	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1141
1146	21:48:57.750	0.00032277	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1142
1147	21:48:57.750	0.00023427	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 08 	
1143
1148	21:48:57.750	0.00024375	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0A 	
1144
1149	21:48:57.750	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1145
1150	21:48:57.750	0.00020780	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1146
1151	21:48:57.750	0.00020741	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 08 	
1147
1152	21:48:57.750	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1148
1153	21:48:57.750	0.00014815	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1149
1154	21:48:57.750	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1150
1155	21:48:57.750	0.00019753	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1151
1156	21:48:57.750	0.00013156	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0A 	
1152
1157	21:48:57.750	0.00018568	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 08 	
1153
1158	21:48:57.750	0.00009640	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1154
1159	21:48:57.750	0.00009640	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1155
1160	21:48:57.750	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: FF 	
1156
1161	21:48:57.750	0.00011615	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1157
1162	21:48:57.750	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1158
1169	21:48:57.750	0.00005452	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1159
1170	21:48:57.750	0.00023190	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1160
1171	21:48:57.750	0.00025402	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1161
1172	21:48:57.750	0.00022795	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1162
1173	21:48:57.750	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1163
1174	21:48:57.750	0.00017699	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1164
1175	21:48:57.750	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1165
1176	21:48:57.750	0.00017304	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1166
1177	21:48:57.750	0.00023585	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1167
1178	21:48:57.750	0.00013551	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1168
1179	21:48:57.750	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1169
1180	21:48:57.750	0.00008454	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1170
1181	21:48:57.750	0.00016277	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1171
1182	21:48:57.750	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1172
1183	21:48:57.750	0.00017580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1173
1184	21:48:57.750	0.00019002	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1174
1185	21:48:57.750	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1175
1186	21:48:57.750	0.00009758	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1176
1187	21:48:57.750	0.00020938	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1177
1188	21:48:57.750	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1178
1189	21:48:57.750	0.00011338	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1179
1190	21:48:57.750	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: FF 	
1180
1191	21:48:57.750	0.00019674	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1181
1192	21:48:57.750	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1182
1195	21:48:57.782	0.00012049	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1183
1196	21:48:57.782	0.00000277	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1184
1197	21:48:57.782	0.01202094	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1185
1198	21:48:57.797	0.00028761	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1186
1199	21:48:57.797	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1187
1200	21:48:57.797	0.00028721	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1188
1201	21:48:57.797	0.00023032	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1189
1202	21:48:57.797	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1190
1203	21:48:57.797	0.00018291	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
1191
1204	21:48:57.797	0.00049146	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1192
1205	21:48:57.797	0.00024059	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: E0 	
1193
1206	21:48:57.797	0.00020741	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1194
1207	21:48:57.797	0.00002489	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1195
1208	21:48:57.797	0.00020148	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1196
1209	21:48:57.797	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1197
1210	21:48:57.797	0.00001896	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1198
1211	21:48:57.797	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1199
1212	21:48:57.797	0.00027931	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1200
1213	21:48:57.797	0.00021057	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
1201
1214	21:48:57.797	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1202
1215	21:48:57.797	0.00029827	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1203
1216	21:48:57.797	0.00024928	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
1204
1217	21:48:57.797	0.00017936	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
1205
1218	21:48:57.797	0.00006519	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1206
1219	21:48:57.797	0.00010548	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1207
1220	21:48:57.797	0.00013472	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 04 	
1208
1221	21:48:57.797	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1209
1222	21:48:57.797	0.00008849	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1210
1223	21:48:57.797	0.00011220	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1211
1224	21:48:57.797	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1212
1225	21:48:57.797	0.00001304	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1213
1226	21:48:57.797	0.00014420	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1214
1227	21:48:57.797	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1215
1228	21:48:57.797	0.00001659	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1216
1229	21:48:57.797	0.00019398	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1217
1230	21:48:57.797	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1218
1231	21:48:57.797	0.00015328	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1219
1232	21:48:57.797	0.00009758	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1220
1233	21:48:57.797	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1221
1234	21:48:57.797	0.00005333	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1222
1235	21:48:57.797	0.00008928	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1223
1236	21:48:57.797	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1224
1237	21:48:57.797	0.00004978	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1225
1238	21:48:57.797	0.00008691	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1226
1239	21:48:57.797	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1227
1240	21:48:57.797	0.00003042	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1228
1241	21:48:57.797	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1229
1242	21:48:57.797	0.00016593	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1230
1243	21:48:57.797	0.00015921	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1231
1244	21:48:57.797	0.00010825	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1232
1245	21:48:57.797	0.00004820	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1233
1246	21:48:57.797	0.00011970	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1234
1247	21:48:57.797	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1235
1248	21:48:57.797	0.00016316	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1236
1250	21:48:57.797	0.00009679	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1237
1251	21:48:57.797	0.00004069	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1238
1252	21:48:57.797	0.00005333	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1239
1253	21:48:57.797	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1240
1254	21:48:57.797	0.00011694	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1241
1255	21:48:57.797	0.00016948	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1242
1256	21:48:57.797	0.00012207	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1243
1257	21:48:57.797	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1244
1258	21:48:57.797	0.00007625	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1245
1259	21:48:57.797	0.00005728	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1246
1260	21:48:57.797	0.02659952	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1247
1261	21:48:57.829	0.00002331	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1248
1262	21:48:57.829	0.01448218	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1249
1263	21:48:57.829	0.00001304	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1250
1264	21:48:57.844	0.00030222	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1251
1265	21:48:57.844	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1252
1266	21:48:57.844	0.00032158	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1253
1267	21:48:57.844	0.00026667	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1254
1268	21:48:57.844	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1255
1269	21:48:57.844	0.00043931	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1256
1270	21:48:57.844	0.00035516	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
1257
1271	21:48:57.844	0.00028089	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: F0 	
1258
1272	21:48:57.844	0.00020504	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1259
1273	21:48:57.844	0.00001620	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1260
1274	21:48:57.844	0.00002528	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1261
1275	21:48:57.844	0.00033383	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1262
1276	21:48:57.844	0.00033936	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1263
1277	21:48:57.844	0.00033067	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 09 	
1264
1278	21:48:57.844	0.00014657	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1265
1279	21:48:57.844	0.00017896	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1266
1280	21:48:57.844	0.00022361	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 08 	
1267
1281	21:48:57.844	0.00009916	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1268
1282	21:48:57.844	0.00017620	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1269
1283	21:48:57.844	0.00011338	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 07 	
1270
1284	21:48:57.844	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1271
1285	21:48:57.844	0.00002884	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1272
1286	21:48:57.844	0.00020583	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1273
1287	21:48:57.844	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1274
1288	21:48:57.844	0.00011378	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1275
1289	21:48:57.844	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1276
1290	21:48:57.844	0.00014025	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1277
1291	21:48:57.844	0.00011457	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1278
1292	21:48:57.844	0.00033857	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1279
1293	21:48:57.844	0.00019358	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1280
1294	21:48:57.844	0.00012563	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1281
1295	21:48:57.844	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1282
1296	21:48:57.844	0.00030657	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1283
1297	21:48:57.844	0.00033146	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1284
1298	21:48:57.844	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1285
1299	21:48:57.844	0.00020622	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1286
1300	21:48:57.844	0.00021057	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1287
1301	21:48:57.844	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1288
1302	21:48:57.844	0.00028681	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1289
1303	21:48:57.844	0.00030617	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1290
1304	21:48:57.844	0.00023032	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1291
1305	21:48:57.844	0.00001975	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1292
1306	21:48:57.844	0.00015921	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1293
1307	21:48:57.844	0.00030301	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1294
1308	21:48:57.844	0.00017343	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1295
1309	21:48:57.844	0.00012089	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1296
1310	21:48:57.844	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: FF 	
1297
1311	21:48:57.844	0.00007980	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1298
1312	21:48:57.844	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1299
1316	21:48:57.844	0.00001659	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1300
1317	21:48:57.844	0.00027062	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1301
1318	21:48:57.844	0.00027259	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1302
1319	21:48:57.844	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1303
1320	21:48:57.844	0.00019002	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1304
1321	21:48:57.844	0.00017185	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1305
1322	21:48:57.844	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1306
1323	21:48:57.844	0.00017659	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1307
1324	21:48:57.844	0.00020504	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1308
1325	21:48:57.844	0.00002054	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1309
1326	21:48:57.844	0.02617127	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1310
1327	21:48:57.875	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1311
1328	21:48:57.875	0.01303981	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1312
1329	21:48:57.875	0.00000237	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1313
1330	21:48:57.891	0.00030736	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1314
1331	21:48:57.891	0.00000514	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1315
1332	21:48:57.891	0.00028444	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1316
1333	21:48:57.891	0.00019161	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1317
1334	21:48:57.891	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1318
1335	21:48:57.891	0.00034923	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1319
1336	21:48:57.891	0.00029551	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1320
1337	21:48:57.891	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1321
1338	21:48:57.891	0.00016079	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1322
1339	21:48:57.891	0.00020267	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1323
1340	21:48:57.891	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1324
1341	21:48:57.891	0.00025679	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1325
1342	21:48:57.891	0.00029511	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1326
1343	21:48:57.891	0.00025007	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
1327
1344	21:48:57.891	0.00014301	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1328
1345	21:48:57.891	0.00009126	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1329
1346	21:48:57.891	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1330
1347	21:48:57.891	0.00018528	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1331
1348	21:48:57.891	0.00015723	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
1332
1349	21:48:57.891	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1333
1350	21:48:57.891	0.00021215	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1334
1351	21:48:57.891	0.00029788	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1335
1352	21:48:57.891	0.00021175	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1336
1353	21:48:57.891	0.00008099	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1337
1354	21:48:57.891	0.00003358	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1338
1355	21:48:57.891	0.00017936	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
1339
1356	21:48:57.891	0.00006005	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1340
1357	21:48:57.891	0.00007111	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1341
1358	21:48:57.891	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1342
1359	21:48:57.891	0.00020464	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1343
1360	21:48:57.891	0.00014301	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1344
1361	21:48:57.891	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1345
1362	21:48:57.891	0.00011220	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1346
1363	21:48:57.891	0.00015012	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1347
1364	21:48:57.891	0.00006756	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1348
1365	21:48:57.891	0.00026746	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1349
1366	21:48:57.891	0.00018805	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1350
1367	21:48:57.891	0.00017620	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1351
1368	21:48:57.891	0.00005965	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1352
1369	21:48:57.891	0.00009126	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1353
1370	21:48:57.891	0.00009205	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1354
1371	21:48:57.891	0.00007427	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1355
1372	21:48:57.891	0.00005689	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1356
1373	21:48:57.891	0.00009244	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
1357
1374	21:48:57.891	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1358
1375	21:48:57.891	0.00006440	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1359
1376	21:48:57.891	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1360
1377	21:48:57.891	0.00012049	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1361
1378	21:48:57.891	0.00013788	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1362
1379	21:48:57.891	0.00004583	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1363
1380	21:48:57.891	0.00017225	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1364
1381	21:48:57.891	0.00020346	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1365
1382	21:48:57.891	0.00004267	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1366
1383	21:48:57.891	0.00008928	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1367
1384	21:48:57.891	0.00010904	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1368
1385	21:48:57.891	0.00003200	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1369
1386	21:48:57.891	0.00019595	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1370
1387	21:48:57.891	0.00011180	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1371
1388	21:48:57.891	0.00002726	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1372
1389	21:48:57.891	0.00016356	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1373
1390	21:48:57.891	0.00013037	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1374
1391	21:48:57.891	0.00003516	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1375
1392	21:48:57.891	0.02707517	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1376
1393	21:48:57.922	0.00006242	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1377
1394	21:48:57.922	0.01330568	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1378
1395	21:48:57.922	0.00001383	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1379
1396	21:48:57.938	0.00029590	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1380
1397	21:48:57.938	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1381
1398	21:48:57.938	0.00038519	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1382
1399	21:48:57.938	0.00022123	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1383
1400	21:48:57.938	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1384
1401	21:48:57.938	0.00021452	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1385
1402	21:48:57.938	0.00018923	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1386
1403	21:48:57.938	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1387
1404	21:48:57.938	0.00041086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1388
1405	21:48:57.938	0.00042311	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1389
1406	21:48:57.938	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1390
1407	21:48:57.938	0.00024928	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1391
1408	21:48:57.938	0.00021531	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1392
1409	21:48:57.938	0.00000553	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1393
1410	21:48:57.938	0.00014736	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1394
1411	21:48:57.938	0.00011101	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1395
1412	21:48:57.938	0.00012089	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1396
1413	21:48:57.938	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1397
1414	21:48:57.938	0.00009126	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1398
1415	21:48:57.938	0.00012010	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1399
1416	21:48:57.938	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1400
1417	21:48:57.938	0.00006479	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1401
1418	21:48:57.938	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1402
1419	21:48:57.938	0.00017027	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1403
1420	21:48:57.938	0.00020346	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1404
1421	21:48:57.938	0.00012721	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1405
1422	21:48:57.938	0.00004306	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1406
1423	21:48:57.938	0.00008178	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1407
1424	21:48:57.938	0.00013393	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1408
1425	21:48:57.938	0.00008612	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1409
1426	21:48:57.938	0.00006953	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1410
1427	21:48:57.938	0.00009402	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1411
1428	21:48:57.938	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1412
1429	21:48:57.938	0.00009956	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1413
1430	21:48:57.938	0.00013788	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1414
1431	21:48:57.938	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1415
1432	21:48:57.938	0.00011378	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1416
1433	21:48:57.938	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1417
1434	21:48:57.938	0.00141748	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1418
1435	21:48:57.938	0.00022558	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1419
1436	21:48:57.938	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1420
1437	21:48:57.938	0.00018528	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1421
1438	21:48:57.938	0.00010153	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1422
1439	21:48:57.938	0.00008652	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1423
1440	21:48:57.938	0.00010548	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1424
1441	21:48:57.938	0.00006558	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1425
1442	21:48:57.938	0.00013669	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1426
1443	21:48:57.938	0.00003477	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1427
1444	21:48:57.938	0.00011615	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1428
1445	21:48:57.938	0.00014657	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1429
1446	21:48:57.938	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1430
1447	21:48:57.938	0.00009719	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1431
1448	21:48:57.938	0.00014222	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1432
1449	21:48:57.938	0.00005768	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1433
1450	21:48:57.938	0.00001264	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1434
1451	21:48:57.938	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1435
1452	21:48:57.938	0.00018173	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1436
1453	21:48:57.938	0.00011022	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1437
1454	21:48:57.938	0.00018133	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1438
1455	21:48:57.938	0.00006242	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1439
1456	21:48:57.938	0.00016119	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1440
1457	21:48:57.938	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1441
1458	21:48:57.938	0.02506115	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1442
1459	21:48:57.969	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1443
1460	21:48:57.969	0.01469591	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1444
1461	21:48:57.969	0.00001383	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1445
1462	21:48:57.985	0.00036109	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1446
1463	21:48:57.985	0.00024454	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1447
1464	21:48:57.985	0.00006400	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1448
1465	21:48:57.985	0.00019911	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1449
1466	21:48:57.985	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1450
1467	21:48:57.985	0.00015368	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1451
1468	21:48:57.985	0.00013630	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1452
1469	21:48:57.985	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1453
1470	21:48:57.985	0.00022440	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1454
1471	21:48:57.985	0.00021610	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1455
1472	21:48:57.985	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1456
1473	21:48:57.985	0.00026469	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1457
1474	21:48:57.985	0.00023822	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1458
1475	21:48:57.985	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1459
1476	21:48:57.985	0.00032198	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1460
1477	21:48:57.985	0.00025402	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
1461
1478	21:48:57.985	0.00024020	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
1462
1479	21:48:57.985	0.00005175	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1463
1480	21:48:57.985	0.00017343	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1464
1481	21:48:57.985	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1465
1482	21:48:57.985	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 06 	
1466
1483	21:48:57.985	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1467
1484	21:48:57.985	0.00028207	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1468
1485	21:48:57.985	0.00033738	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1469
1486	21:48:57.985	0.00007625	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1470
1487	21:48:57.985	0.00024928	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
1471
1488	21:48:57.985	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1472
1489	21:48:57.985	0.00022163	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1473
1490	21:48:57.985	0.00016790	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1474
1491	21:48:57.985	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1475
1492	21:48:57.985	0.00009363	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1476
1493	21:48:57.985	0.00011773	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1477
1494	21:48:57.985	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1478
1495	21:48:57.985	0.00002765	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1479
1496	21:48:57.985	0.00015131	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1480
1497	21:48:57.985	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1481
1498	21:48:57.985	0.00003160	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1482
1499	21:48:57.985	0.00008257	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1483
1500	21:48:57.985	0.00003674	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1484
1501	21:48:57.985	0.00007032	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1485
1502	21:48:57.985	0.00013077	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1486
1503	21:48:57.985	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1487
1504	21:48:57.985	0.00005215	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1488
1505	21:48:57.985	0.00013985	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
1489
1506	21:48:57.985	0.00006519	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1490
1507	21:48:57.985	0.00011812	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1491
1508	21:48:57.985	0.00015170	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1492
1509	21:48:57.985	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1493
1510	21:48:57.985	0.00003200	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1494
1511	21:48:57.985	0.00012089	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1495
1512	21:48:57.985	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1496
1513	21:48:57.985	0.00011615	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1497
1514	21:48:57.985	0.00011891	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1498
1515	21:48:57.985	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1499
1516	21:48:57.985	0.00004306	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1500
1517	21:48:57.985	0.00014380	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1501
1518	21:48:57.985	0.00016672	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1502
1519	21:48:57.985	0.00012958	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1503
1520	21:48:57.985	0.00003358	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1504
1521	21:48:57.985	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1505
1522	21:48:57.985	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1506
1523	21:48:57.985	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1507
1524	21:48:57.985	0.02695310	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1508
1525	21:48:58.016	0.00000632	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1509
1526	21:48:58.016	0.01361818	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1510
1527	21:48:58.016	0.00001699	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1511
1528	21:48:58.032	0.00038558	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1512
1529	21:48:58.032	0.00018923	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1513
1530	21:48:58.032	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1514
1531	21:48:58.032	0.00016909	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1515
1532	21:48:58.032	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1516
1533	21:48:58.032	0.00027891	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1517
1534	21:48:58.032	0.00021649	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1518
1535	21:48:58.032	0.00018884	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 30 	
1519
1536	21:48:58.032	0.00012523	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1520
1537	21:48:58.032	0.00012998	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1521
1538	21:48:58.032	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1522
1539	21:48:58.032	0.00024217	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1523
1540	21:48:58.032	0.00025956	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1524
1541	21:48:58.032	0.00006360	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1525
1542	21:48:58.032	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 00 	
1526
1543	21:48:58.032	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1527
1547	21:48:58.032	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1528
1548	21:48:58.032	0.00021886	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1529
1549	21:48:58.032	0.00023111	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1530
1550	21:48:58.032	0.00026351	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1531
1551	21:48:58.032	0.00009560	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1532
1552	21:48:58.032	0.00012602	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1533
1553	21:48:58.032	0.00017343	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1534
1554	21:48:58.032	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1535
1555	21:48:58.032	0.00017462	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1536
1556	21:48:58.032	0.00036622	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1537
1557	21:48:58.032	0.00009640	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1538
1558	21:48:58.032	0.00023546	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1539
1559	21:48:58.032	0.00020425	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1540
1560	21:48:58.032	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1541
1561	21:48:58.032	0.00010272	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1542
1562	21:48:58.032	0.00020820	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1543
1563	21:48:58.032	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1544
1564	21:48:58.032	0.00010311	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1545
1565	21:48:58.032	0.00033225	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1546
1566	21:48:58.032	0.00012089	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1547
1567	21:48:58.032	0.00007506	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1548
1568	21:48:58.032	0.00012602	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1549
1569	21:48:58.032	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1550
1570	21:48:58.032	0.00006123	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1551
1571	21:48:58.032	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1552
1572	21:48:58.032	0.00027615	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1553
1573	21:48:58.032	0.00021649	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1554
1574	21:48:58.032	0.00015091	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1555
1575	21:48:58.032	0.00006202	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1556
1576	21:48:58.032	0.00009481	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1557
1577	21:48:58.032	0.00018212	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1558
1578	21:48:58.032	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1559
1579	21:48:58.032	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1560
1580	21:48:58.032	0.00000119	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1561
1581	21:48:58.032	0.00019161	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1562
1582	21:48:58.032	0.00014459	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1563
1583	21:48:58.032	0.00016158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1564
1584	21:48:58.032	0.00031170	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1565
1585	21:48:58.032	0.00036978	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1566
1586	21:48:58.032	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1567
1587	21:48:58.032	0.00016395	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1568
1588	21:48:58.032	0.00011417	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1569
1589	21:48:58.032	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1570
1590	21:48:58.032	0.02734105	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1571
1591	21:48:58.063	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1572
1592	21:48:58.063	0.01212129	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1573
1593	21:48:58.063	0.00000277	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1574
1594	21:48:58.078	0.00025679	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1575
1595	21:48:58.078	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1576
1596	21:48:58.078	0.00026193	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1577
1597	21:48:58.078	0.00022953	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1578
1598	21:48:58.078	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1579
1599	21:48:58.078	0.00024731	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1580
1600	21:48:58.078	0.00017185	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1581
1601	21:48:58.078	0.00020780	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 40 	
1582
1602	21:48:58.078	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1583
1603	21:48:58.078	0.00015486	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1584
1604	21:48:58.078	0.00014301	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1585
1605	21:48:58.078	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1586
1606	21:48:58.078	0.00001580	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1587
1607	21:48:58.078	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1588
1608	21:48:58.078	0.00017027	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1589
1609	21:48:58.078	0.00011141	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 03 	
1590
1610	21:48:58.078	0.00008573	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1591
1611	21:48:58.078	0.00013314	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1592
1612	21:48:58.078	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1593
1613	21:48:58.078	0.00001699	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1594
1614	21:48:58.078	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1595
1615	21:48:58.078	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1596
1616	21:48:58.078	0.00004899	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1597
1617	21:48:58.078	0.00028405	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1598
1618	21:48:58.078	0.00019477	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1599
1619	21:48:58.078	0.00019200	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
1600
1620	21:48:58.078	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1601
1621	21:48:58.078	0.00015961	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1602
1622	21:48:58.078	0.00030973	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1603
1623	21:48:58.078	0.00024810	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1604
1624	21:48:58.078	0.00004938	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1605
1625	21:48:58.078	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1606
1626	21:48:58.078	0.00021057	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1607
1627	21:48:58.078	0.00014617	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1608
1628	21:48:58.078	0.00021373	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1609
1629	21:48:58.078	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1		Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1610
1630	21:48:58.078	0.00012840	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1611
1631	21:48:58.078	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1612
1632	21:48:58.078	0.00023980	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1613
1633	21:48:58.078	0.00016790	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1614
1634	21:48:58.078	0.00016395	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 01 	
1615
1635	21:48:58.078	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1616
1636	21:48:58.078	0.00006202	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1617
1637	21:48:58.078	0.00015881	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1618
1638	21:48:58.078	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1619
1639	21:48:58.078	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1620
1640	21:48:58.078	0.00016672	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1621
1641	21:48:58.078	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1622
1642	21:48:58.078	0.00013432	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1623
1643	21:48:58.078	0.00017225	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1624
1644	21:48:58.078	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1625
1645	21:48:58.078	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1626
1646	21:48:58.078	0.00017462	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1627
1647	21:48:58.078	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1628
1648	21:48:58.078	0.00007032	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1629
1649	21:48:58.078	0.00017620	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1630
1650	21:48:58.078	0.00001778	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1631
1651	21:48:58.078	0.00008770	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1632
1652	21:48:58.078	0.00012523	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1633
1653	21:48:58.078	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1634
1654	21:48:58.078	0.00001462	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1635
1655	21:48:58.078	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1636
1656	21:48:58.078	0.02640791	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1637
1657	21:48:58.110	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1638
1658	21:48:58.110	0.01493136	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1639
1659	21:48:58.110	0.00001501	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1640
1660	21:48:58.125	0.00023664	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1641
1661	21:48:58.125	0.00025442	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1642
1662	21:48:58.125	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1643
1663	21:48:58.125	0.00015289	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1644
1664	21:48:58.125	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1		Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1645
1665	21:48:58.125	0.00061788	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1646
1667	21:48:58.125	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1647
1668	21:48:58.125	0.00018963	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1648
1669	21:48:58.125	0.00015881	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 50 	
1649
1670	21:48:58.125	0.00019437	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1650
1671	21:48:58.125	0.00004148	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1651
1672	21:48:58.125	0.00010706	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1652
1673	21:48:58.125	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1653
1674	21:48:58.125	0.00018133	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1654
1675	21:48:58.125	0.00020859	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1655
1676	21:48:58.125	0.00014222	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1656
1677	21:48:58.125	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1657
1678	21:48:58.125	0.00009284	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1658
1679	21:48:58.125	0.00020741	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1659
1680	21:48:58.125	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1660
1681	21:48:58.125	0.00014578	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1661
1682	21:48:58.125	0.00013274	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1662
1683	21:48:58.125	0.00007072	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1663
1684	21:48:58.125	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1664
1685	21:48:58.125	0.00013709	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1665
1686	21:48:58.125	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1666
1687	21:48:58.125	0.00011062	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1667
1688	21:48:58.125	0.00000948	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1668
1689	21:48:58.125	0.00032948	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1669
1691	21:48:58.125	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1670
1692	21:48:58.125	0.00032277	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1671
1693	21:48:58.125	0.00025402	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1672
1694	21:48:58.125	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1673
1695	21:48:58.125	0.00020306	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1674
1696	21:48:58.125	0.00014499	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1675
1697	21:48:58.125	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1676
1698	21:48:58.125	0.00035674	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1677
1699	21:48:58.125	0.00030341	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1678
1700	21:48:58.125	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1679
1701	21:48:58.125	0.00023309	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1680
1702	21:48:58.125	0.00020425	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1681
1703	21:48:58.125	0.00022044	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1682
1704	21:48:58.125	0.00001778	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1683
1705	21:48:58.125	0.00014894	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1684
1706	21:48:58.125	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 00 	
1685
1707	21:48:58.125	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1686
1708	21:48:58.125	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1687
1711	21:48:58.125	0.00035911	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1688
1712	21:48:58.125	0.00016158	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1689
1713	21:48:58.125	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1690
1714	21:48:58.125	0.00012286	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1691
1715	21:48:58.125	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1692
1716	21:48:58.125	0.00032790	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1693
1717	21:48:58.125	0.00023427	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1694
1718	21:48:58.125	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: FF 	
1695
1719	21:48:58.125	0.00012089	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1696
1720	21:48:58.125	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1697
1723	21:48:58.157	0.00007427	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1698
1724	21:48:58.157	0.01327447	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1699
1725	21:48:58.157	0.00012128	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1700
1726	21:48:58.172	0.00019437	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1701
1727	21:48:58.172	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1702
1728	21:48:58.172	0.00025600	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1703
1729	21:48:58.172	0.00019793	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1704
1730	21:48:58.172	0.00019714	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1705
1731	21:48:58.172	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1706
1732	21:48:58.172	0.00006677	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1707
1733	21:48:58.172	0.00018449	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 60 	
1708
1734	21:48:58.172	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1709
1735	21:48:58.172	0.00007190	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1710
1736	21:48:58.172	0.00019516	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1711
1737	21:48:58.172	0.00007230	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1712
1738	21:48:58.172	0.00008770	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 04 	
1713
1739	21:48:58.172	0.00008928	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1714
1740	21:48:58.172	0.00003832	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1715
1741	21:48:58.172	0.00001659	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1716
1742	21:48:58.172	0.00009837	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1717
1743	21:48:58.172	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1718
1744	21:48:58.172	0.00009323	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1719
1745	21:48:58.172	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 00 	
1720
1746	21:48:58.172	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1721
1747	21:48:58.172	0.00010785	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1722
1748	21:48:58.172	0.00003674	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1723
1749	21:48:58.172	0.00036306	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1724
1751	21:48:58.172	0.00001580	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1725
1752	21:48:58.172	0.00015249	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
1726
1753	21:48:58.172	0.00017106	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1727
1754	21:48:58.172	0.00017225	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1728
1755	21:48:58.172	0.00008099	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1729
1756	21:48:58.172	0.00012010	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1730
1757	21:48:58.172	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1731
1758	21:48:58.172	0.00025877	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1732
1759	21:48:58.172	0.00021175	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1733
1760	21:48:58.172	0.00013867	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1734
1761	21:48:58.172	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1735
1762	21:48:58.172	0.00008533	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1736
1763	21:48:58.172	0.00016316	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1737
1764	21:48:58.172	0.00006321	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1738
1765	21:48:58.172	0.00012168	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1739
1766	21:48:58.172	0.00011259	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1740
1767	21:48:58.172	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1741
1768	21:48:58.172	0.00005649	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1742
1769	21:48:58.172	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 01 	
1743
1770	21:48:58.172	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1744
1771	21:48:58.172	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
1745
1773	21:48:58.172	0.00029788	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1746
1774	21:48:58.172	0.00005017	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1747
1775	21:48:58.172	0.00021175	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 02 	
1748
1776	21:48:58.172	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1749
1777	21:48:58.172	0.00012326	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1750
1778	21:48:58.172	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1751
1779	21:48:58.172	0.00014736	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1752
1780	21:48:58.172	0.00015131	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 05 	
1753
1781	21:48:58.172	0.00009798	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1754
1782	21:48:58.172	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1755
1783	21:48:58.172	0.00008296	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1756
1784	21:48:58.172	0.00013946	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1757
1785	21:48:58.172	0.00005728	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1758
1786	21:48:58.172	0.00011378	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1759
1787	21:48:58.172	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1760
1788	21:48:58.172	0.02667458	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1761
1789	21:48:58.204	0.00002331	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1762
1790	21:48:58.204	0.01446361	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1763
1791	21:48:58.204	0.00003753	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1764
1792	21:48:58.219	0.00033817	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1765
1793	21:48:58.219	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1766
1794	21:48:58.219	0.00041640	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1767
1795	21:48:58.219	0.00031684	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1768
1796	21:48:58.219	0.00029827	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1769
1797	21:48:58.219	0.00016948	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1770
1798	21:48:58.219	0.00002212	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1771
1799	21:48:58.219	0.00010746	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1772
1800	21:48:58.219	0.00022321	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 70 	
1773
1801	21:48:58.219	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1774
1802	21:48:58.219	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1775
1803	21:48:58.219	0.00019793	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1776
1804	21:48:58.219	0.00022084	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1777
1805	21:48:58.219	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1778
1806	21:48:58.219	0.00021570	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1779
1807	21:48:58.219	0.00016988	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1780
1808	21:48:58.219	0.00016790	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1781
1809	21:48:58.219	0.00003358	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1782
1810	21:48:58.219	0.00012563	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1783
1811	21:48:58.219	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1784
1812	21:48:58.219	0.00026627	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1785
1813	21:48:58.219	0.00013867	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1786
1814	21:48:58.219	0.00006716	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1787
1815	21:48:58.219	0.00035753	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1788
1816	21:48:58.219	0.00017422	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1789
1817	21:48:58.219	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1790
1818	21:48:58.219	0.00022874	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1791
1819	21:48:58.219	0.00016948	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0E 	
1792
1820	21:48:58.219	0.00002015	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1793
1821	21:48:58.219	0.00019319	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1794
1823	21:48:58.219	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1795
1824	21:48:58.219	0.00021807	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1796
1825	21:48:58.219	0.00019516	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1797
1826	21:48:58.219	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1798
1827	21:48:58.219	0.00026548	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1799
1828	21:48:58.219	0.00021491	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1800
1829	21:48:58.219	0.00022400	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1801
1830	21:48:58.219	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1802
1831	21:48:58.219	0.00006479	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1803
1832	21:48:58.219	0.00014380	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1804
1833	21:48:58.219	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1805
1834	21:48:58.219	0.00013274	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1806
1835	21:48:58.219	0.00016356	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1807
1836	21:48:58.219	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1808
1837	21:48:58.219	0.00001817	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1809
1838	21:48:58.219	0.00018884	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 00 	
1810
1839	21:48:58.219	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1811
1840	21:48:58.219	0.00008138	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1812
1841	21:48:58.219	0.00018607	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1813
1842	21:48:58.219	0.00000553	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1814
1843	21:48:58.219	0.00015447	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1815
1844	21:48:58.219	0.00017422	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1816
1845	21:48:58.219	0.00006321	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1817
1846	21:48:58.219	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1818
1847	21:48:58.219	0.00019042	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1819
1848	21:48:58.219	0.00005768	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1820
1849	21:48:58.219	0.00011220	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1821
1850	21:48:58.219	0.00025995	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
1822
1851	21:48:58.219	0.00009640	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1823
1852	21:48:58.219	0.00021728	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1824
1853	21:48:58.219	0.00002884	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1825
1854	21:48:58.219	0.02551586	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1826
1855	21:48:58.251	0.00002489	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1827
1856	21:48:58.251	0.02981651	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1828
1857	21:48:58.251	0.00000277	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1829
1858	21:48:58.281	0.00039506	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1830
1859	21:48:58.281	0.00002647	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1831
1860	21:48:58.281	0.00043062	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1832
1861	21:48:58.281	0.00035635	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1833
1862	21:48:58.281	0.00024494	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1834
1863	21:48:58.281	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1835
1864	21:48:58.281	0.00017659	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1836
1865	21:48:58.281	0.00031091	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 80 	
1837
1866	21:48:58.281	0.00002923	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1838
1867	21:48:58.281	0.00028049	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1839
1868	21:48:58.281	0.00019674	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1840
1869	21:48:58.281	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1841
1870	21:48:58.281	0.00013353	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1842
1871	21:48:58.281	0.00012326	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1843
1872	21:48:58.281	0.00012247	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1844
1873	21:48:58.281	0.00008731	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1845
1874	21:48:58.281	0.00013314	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1846
1875	21:48:58.281	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1847
1876	21:48:58.281	0.00009126	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1848
1877	21:48:58.281	0.00009956	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1849
1878	21:48:58.281	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1850
1879	21:48:58.281	0.00006123	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1851
1880	21:48:58.281	0.00012642	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1852
1881	21:48:58.281	0.00015091	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1853
1882	21:48:58.281	0.00015763	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1854
1883	21:48:58.281	0.00009758	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1855
1884	21:48:58.281	0.00000948	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1856
1885	21:48:58.281	0.00013630	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1857
1886	21:48:58.281	0.00015921	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1858
1887	21:48:58.281	0.00013393	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1859
1888	21:48:58.281	0.00021096	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1860
1889	21:48:58.281	0.00010825	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1861
1890	21:48:58.281	0.00019437	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1862
1891	21:48:58.281	0.00009600	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1863
1892	21:48:58.281	0.00002765	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1864
1893	21:48:58.281	0.00018449	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1865
1894	21:48:58.281	0.00006637	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1866
1895	21:48:58.281	0.00002923	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1867
1896	21:48:58.281	0.00015565	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1868
1897	21:48:58.281	0.00022361	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1869
1898	21:48:58.281	0.00001817	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1870
1899	21:48:58.281	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1871
1900	21:48:58.281	0.00014736	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1872
1901	21:48:58.281	0.00022874	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1873
1902	21:48:58.281	0.00013906	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1874
1903	21:48:58.281	0.00025402	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1875
1904	21:48:58.281	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1876
1905	21:48:58.281	0.00001462	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1877
1906	21:48:58.281	0.00019872	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1878
1907	21:48:58.281	0.00022519	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1879
1908	21:48:58.281	0.00001738	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1880
1909	21:48:58.281	0.00018489	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1881
1910	21:48:58.281	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1882
1911	21:48:58.281	0.00007862	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1883
1912	21:48:58.281	0.00015842	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1884
1913	21:48:58.281	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1885
1914	21:48:58.281	0.00010035	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1886
1915	21:48:58.281	0.00001817	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1887
1916	21:48:58.281	0.02721818	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1888
1917	21:48:58.313	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1889
1918	21:48:58.313	0.01383309	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1890
1919	21:48:58.313	0.00001185	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1891
1920	21:48:58.328	0.00047486	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1892
1921	21:48:58.328	0.00000948	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1893
1922	21:48:58.328	0.00041284	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1894
1923	21:48:58.328	0.00027694	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1895
1924	21:48:58.328	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1896
1925	21:48:58.328	0.00017857	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1897
1926	21:48:58.328	0.00014301	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1898
1927	21:48:58.328	0.00006163	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1899
1928	21:48:58.328	0.00047052	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 90 	
1900
1929	21:48:58.328	0.00038677	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1901
1930	21:48:58.328	0.00033541	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1902
1931	21:48:58.328	0.00016237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1903
1932	21:48:58.328	0.00019516	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1904
1933	21:48:58.328	0.00017817	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 57 	
1905
1934	21:48:58.328	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1906
1935	21:48:58.328	0.00006005	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1907
1936	21:48:58.328	0.00027101	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 45 	
1908
1937	21:48:58.328	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1909
1938	21:48:58.328	0.00008178	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1910
1939	21:48:58.328	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1911
1940	21:48:58.328	0.00019753	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 4C 	
1912
1941	21:48:58.328	0.00019951	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1913
1942	21:48:58.328	0.00015447	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 43 	
1914
1943	21:48:58.328	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1915
1944	21:48:58.328	0.00006598	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1916
1945	21:48:58.328	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1917
1946	21:48:58.328	0.00020701	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 4F 	
1918
1947	21:48:58.328	0.00024178	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1919
1948	21:48:58.328	0.00022123	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 4D 	
1920
1949	21:48:58.328	0.00009007	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1921
1950	21:48:58.328	0.00016514	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1922
1951	21:48:58.328	0.00021807	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 45 	
1923
1952	21:48:58.328	0.00012642	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1924
1953	21:48:58.328	0.00008296	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1925
1954	21:48:58.328	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1926
1955	21:48:58.328	0.00020820	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1927
1956	21:48:58.328	0.00017146	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1928
1957	21:48:58.328	0.00013432	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1929
1958	21:48:58.328	0.00003002	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1930
1959	21:48:58.328	0.00011417	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1931
1960	21:48:58.328	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1932
1961	21:48:58.328	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1933
1962	21:48:58.328	0.00007585	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1934
1963	21:48:58.328	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1935
1964	21:48:58.328	0.00017185	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1936
1965	21:48:58.328	0.00021531	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1937
1966	21:48:58.328	0.00002252	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1938
1967	21:48:58.328	0.00016711	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1939
1968	21:48:58.328	0.00011180	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1940
1969	21:48:58.328	0.00010232	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1941
1970	21:48:58.328	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1942
1971	21:48:58.328	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1943
1972	21:48:58.328	0.00007506	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1944
1973	21:48:58.328	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1945
1974	21:48:58.328	0.00005649	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1946
1975	21:48:58.328	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1947
1976	21:48:58.328	0.00013669	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1948
1977	21:48:58.328	0.00016751	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1949
1978	21:48:58.328	0.00011259	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1950
1979	21:48:58.328	0.00024573	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1951
1980	21:48:58.328	0.00017067	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1952
1981	21:48:58.328	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1953
1982	21:48:58.328	0.02592515	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1954
1983	21:48:58.360	0.00000751	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1955
1984	21:48:58.360	0.01482944	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1956
1985	21:48:58.360	0.00006519	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
1957
1986	21:48:58.376	0.00025126	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
1958
1987	21:48:58.376	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1959
1988	21:48:58.376	0.00032751	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1960
1989	21:48:58.376	0.00026469	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
1961
1990	21:48:58.376	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1962
1991	21:48:58.376	0.00049304	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1963
1992	21:48:58.376	0.00039664	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
1964
1993	21:48:58.376	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1965
1994	21:48:58.376	0.00014025	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: A0 	
1966
1995	21:48:58.376	0.00017422	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1967
1996	21:48:58.376	0.00015407	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
1968
1997	21:48:58.376	0.00016395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1969
1998	21:48:58.376	0.00003595	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1970
1999	21:48:58.376	0.00025086	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1971
2000	21:48:58.376	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1972
2001	21:48:58.376	0.00023585	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1973
2002	21:48:58.376	0.00012958	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1974
2003	21:48:58.376	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1975
2004	21:48:58.376	0.00014973	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1976
2005	21:48:58.376	0.00013985	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1977
2006	21:48:58.376	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1978
2007	21:48:58.376	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1979
2008	21:48:58.376	0.00012405	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1980
2009	21:48:58.376	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1981
2010	21:48:58.376	0.00011378	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1982
2011	21:48:58.376	0.00020267	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1983
2012	21:48:58.376	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1984
2013	21:48:58.376	0.00014301	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1985
2014	21:48:58.376	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 20 	
1986
2015	21:48:58.376	0.00008652	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1987
2021	21:48:58.376	0.00003595	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1988
2022	21:48:58.376	0.00010469	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1989
2023	21:48:58.376	0.00011101	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1990
2024	21:48:58.376	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1991
2025	21:48:58.376	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1992
2026	21:48:58.376	0.00013709	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1993
2027	21:48:58.376	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1994
2028	21:48:58.376	0.00001778	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1995
2029	21:48:58.376	0.00013709	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1996
2030	21:48:58.376	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
1997
2031	21:48:58.376	0.00012286	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
1998
2032	21:48:58.376	0.00014657	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
1999
2033	21:48:58.376	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2000
2034	21:48:58.376	0.00005136	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2001
2035	21:48:58.376	0.00001659	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2002
2036	21:48:58.376	0.00019911	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2003
2037	21:48:58.376	0.00013235	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2004
2038	21:48:58.376	0.00012642	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2005
2039	21:48:58.376	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2006
2040	21:48:58.376	0.00001462	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2007
2041	21:48:58.376	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2008
2042	21:48:58.376	0.00018923	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2009
2043	21:48:58.376	0.00018133	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2010
2044	21:48:58.376	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2011
2045	21:48:58.376	0.00014341	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2012
2046	21:48:58.376	0.00014775	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2013
2047	21:48:58.376	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2014
2048	21:48:58.376	0.02722767	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2015
2049	21:48:58.407	0.00002963	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2016
2050	21:48:58.407	0.02856574	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2017
2051	21:48:58.407	0.00000316	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
2018
2052	21:48:58.438	0.00037965	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
2019
2053	21:48:58.438	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2020
2054	21:48:58.438	0.00031802	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2021
2055	21:48:58.438	0.00025837	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
2022
2056	21:48:58.438	0.00001541	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2023
2058	21:48:58.438	0.00025758	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
2024
2059	21:48:58.438	0.00007506	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2025
2060	21:48:58.438	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
2026
2061	21:48:58.438	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: B0 	
2027
2062	21:48:58.438	0.00015407	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2028
2063	21:48:58.438	0.00037886	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
2029
2064	21:48:58.438	0.00026193	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2030
2065	21:48:58.438	0.00018331	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2031
2066	21:48:58.438	0.00010588	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2032
2067	21:48:58.438	0.00009521	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2033
2068	21:48:58.438	0.00032395	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2034
2069	21:48:58.438	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2035
2070	21:48:58.438	0.00019793	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2036
2071	21:48:58.438	0.00017778	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2037
2072	21:48:58.438	0.00003951	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2038
2073	21:48:58.438	0.00018568	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2039
2074	21:48:58.438	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2040
2075	21:48:58.438	0.00016000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2041
2076	21:48:58.438	0.00015210	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2042
2077	21:48:58.438	0.00019674	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2043
2078	21:48:58.438	0.00007980	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2044
2079	21:48:58.438	0.00011773	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2045
2080	21:48:58.438	0.00029985	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2046
2081	21:48:58.438	0.00019714	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2047
2082	21:48:58.438	0.00016790	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2048
2083	21:48:58.438	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2049
2084	21:48:58.438	0.00052780	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2050
2085	21:48:58.438	0.00045274	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2051
2086	21:48:58.438	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2052
2087	21:48:58.438	0.00027891	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2053
2088	21:48:58.438	0.00021175	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 20 	
2054
2089	21:48:58.438	0.00025995	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 4B 	
2055
2090	21:48:58.438	0.00008336	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2056
2091	21:48:58.438	0.00012998	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2057
2092	21:48:58.438	0.00013827	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 54 	
2058
2093	21:48:58.438	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2059
2094	21:48:58.438	0.00012840	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2060
2095	21:48:58.438	0.00029235	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 2D 	
2061
2096	21:48:58.438	0.00016593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2062
2097	21:48:58.438	0.00012128	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 37 	
2063
2098	21:48:58.438	0.00012958	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2064
2099	21:48:58.438	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2065
2100	21:48:58.438	0.00001975	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2066
2101	21:48:58.438	0.00011180	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 39 	
2067
2102	21:48:58.438	0.00004701	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2068
2103	21:48:58.438	0.00009877	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2069
2104	21:48:58.438	0.00011733	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 30 	
2070
2105	21:48:58.438	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2071
2106	21:48:58.438	0.00003042	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2072
2107	21:48:58.438	0.00003516	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2073
2108	21:48:58.438	0.00020425	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2074
2109	21:48:58.438	0.00023664	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 30 	
2075
2110	21:48:58.438	0.00015170	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 44 	
2076
2111	21:48:58.438	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2077
2112	21:48:58.438	0.00012365	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2078
2113	21:48:58.438	0.00004425	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2079
2114	21:48:58.438	0.02456811	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2080
2115	21:48:58.469	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2081
2116	21:48:58.469	0.01479349	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2082
2117	21:48:58.469	0.00000237	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
2083
2118	21:48:58.484	0.00039664	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
2084
2119	21:48:58.484	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2085
2120	21:48:58.484	0.00082212	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2086
2121	21:48:58.484	0.00069531	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
2087
2122	21:48:58.484	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2088
2123	21:48:58.484	0.00031486	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2089
2124	21:48:58.484	0.00022281	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
2090
2125	21:48:58.484	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2091
2126	21:48:58.484	0.00032395	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2092
2127	21:48:58.484	0.00021215	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: C0 	
2093
2128	21:48:58.484	0.00026074	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
2094
2129	21:48:58.484	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2095
2130	21:48:58.484	0.00021728	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2096
2131	21:48:58.484	0.00000435	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2097
2132	21:48:58.484	0.00024375	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2098
2133	21:48:58.484	0.00031012	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2099
2134	21:48:58.484	0.00005886	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2100
2135	21:48:58.484	0.00026588	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2101
2136	21:48:58.484	0.00025877	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2102
2137	21:48:58.484	0.00017225	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2103
2138	21:48:58.484	0.00006005	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2104
2139	21:48:58.484	0.00014894	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2105
2140	21:48:58.484	0.00008494	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2106
2141	21:48:58.484	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2107
2142	21:48:58.484	0.00006914	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2108
2143	21:48:58.484	0.00016988	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2109
2144	21:48:58.484	0.00010272	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2110
2145	21:48:58.484	0.00006360	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2111
2146	21:48:58.484	0.00014183	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2112
2147	21:48:58.484	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2113
2148	21:48:58.484	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2114
2149	21:48:58.484	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2115
2150	21:48:58.484	0.00018410	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2116
2151	21:48:58.484	0.00011141	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2117
2152	21:48:58.484	0.00023427	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2118
2153	21:48:58.484	0.00010785	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2119
2154	21:48:58.484	0.00015328	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2120
2155	21:48:58.484	0.00011773	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2121
2156	21:48:58.484	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1		Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2122
2157	21:48:58.484	0.00004820	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2123
2158	21:48:58.484	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2124
2159	21:48:58.484	0.00017501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2125
2160	21:48:58.484	0.00009995	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2126
2161	21:48:58.484	0.00010785	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2127
2162	21:48:58.484	0.00007980	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2128
2163	21:48:58.484	0.00007506	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2129
2164	21:48:58.484	0.00014696	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2130
2165	21:48:58.484	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2131
2166	21:48:58.484	0.00007980	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2132
2167	21:48:58.484	0.00011457	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2133
2168	21:48:58.484	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2134
2169	21:48:58.484	0.00008415	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2135
2170	21:48:58.484	0.00008020	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2136
2171	21:48:58.484	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2137
2172	21:48:58.484	0.00003793	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2138
2173	21:48:58.484	0.00014420	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2139
2174	21:48:58.484	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2140
2175	21:48:58.484	0.00004820	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2141
2176	21:48:58.484	0.00013867	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2142
2177	21:48:58.484	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2143
2178	21:48:58.484	0.00001343	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2144
2179	21:48:58.484	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2145
2180	21:48:58.484	0.02733631	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2146
2181	21:48:58.516	0.00000711	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2147
2182	21:48:58.516	0.01343092	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2148
2183	21:48:58.516	0.00000237	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
2149
2184	21:48:58.532	0.00021412	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
2150
2185	21:48:58.532	0.00006123	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2151
2186	21:48:58.532	0.00044286	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2152
2187	21:48:58.532	0.00029748	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
2153
2188	21:48:58.532	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2154
2189	21:48:58.532	0.00041323	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2155
2190	21:48:58.532	0.00031091	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
2156
2191	21:48:58.532	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2157
2192	21:48:58.532	0.00029985	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2158
2193	21:48:58.532	0.00022361	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: D0 	
2159
2194	21:48:58.532	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2160
2195	21:48:58.532	0.00027891	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2161
2196	21:48:58.532	0.00016672	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
2162
2197	21:48:58.532	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2163
2198	21:48:58.532	0.00027378	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2164
2199	21:48:58.532	0.00021175	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2165
2200	21:48:58.532	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2166
2201	21:48:58.532	0.00036306	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2167
2202	21:48:58.532	0.00035398	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2168
2203	21:48:58.532	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2169
2204	21:48:58.532	0.00003872	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2170
2205	21:48:58.532	0.00011812	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2171
2206	21:48:58.532	0.00011575	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2172
2207	21:48:58.532	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2173
2208	21:48:58.532	0.00006795	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2174
2209	21:48:58.532	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2175
2210	21:48:58.532	0.00018252	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2176
2211	21:48:58.532	0.00014538	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2177
2212	21:48:58.532	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2178
2213	21:48:58.532	0.00018212	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2179
2214	21:48:58.532	0.00019398	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2180
2215	21:48:58.532	0.00013077	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2181
2216	21:48:58.532	0.00008573	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2182
2217	21:48:58.532	0.00007585	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2183
2218	21:48:58.532	0.00013037	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2184
2219	21:48:58.532	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2185
2220	21:48:58.532	0.00007230	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2186
2221	21:48:58.532	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2187
2222	21:48:58.532	0.00023664	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2188
2223	21:48:58.532	0.00023467	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2189
2224	21:48:58.532	0.00010706	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2190
2225	21:48:58.532	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2191
2226	21:48:58.532	0.00006202	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2192
2227	21:48:58.532	0.00010074	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2193
2228	21:48:58.532	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2194
2229	21:48:58.532	0.00009205	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2195
2230	21:48:58.532	0.00007546	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2196
2231	21:48:58.532	0.00010667	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2197
2232	21:48:58.532	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2198
2233	21:48:58.532	0.00001343	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2199
2234	21:48:58.532	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2200
2235	21:48:58.532	0.00001738	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2201
2236	21:48:58.532	0.00014262	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2202
2237	21:48:58.532	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2203
2238	21:48:58.532	0.00005175	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2204
2239	21:48:58.532	0.00008375	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2205
2240	21:48:58.532	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2206
2241	21:48:58.532	0.00004425	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2207
2242	21:48:58.532	0.00012049	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2208
2243	21:48:58.532	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2209
2244	21:48:58.532	0.00005768	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2210
2245	21:48:58.532	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2211
2246	21:48:58.532	0.02869413	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2212
2247	21:48:58.563	0.00002212	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2213
2248	21:48:58.563	0.01269413	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2214
2249	21:48:58.563	0.00002212	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
2215
2250	21:48:58.578	0.00048079	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
2216
2251	21:48:58.578	0.00001699	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2217
2252	21:48:58.578	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1			
2218
2253	21:48:58.578	0.00000000	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1		Length: 1, Data: 58 	
2219
2257	21:48:58.578	0.00019753	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: E0 	
2220
2258	21:48:58.578	0.00001857	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2221
2259	21:48:58.578	0.00013195	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2222
2260	21:48:58.578	0.00018410	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2223
2261	21:48:58.578	0.00021057	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
2224
2262	21:48:58.578	0.00008770	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2225
2263	21:48:58.578	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2226
2264	21:48:58.578	0.00020741	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2227
2265	21:48:58.578	0.00014222	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2228
2266	21:48:58.578	0.00010785	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2229
2267	21:48:58.578	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2230
2268	21:48:58.578	0.00001936	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2231
2269	21:48:58.578	0.00049936	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2232
2270	21:48:58.578	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2233
2271	21:48:58.578	0.00045946	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2234
2272	21:48:58.578	0.00004583	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2235
2273	21:48:58.578	0.00019990	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2236
2274	21:48:58.578	0.00026943	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2237
2275	21:48:58.578	0.00015052	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2238
2276	21:48:58.578	0.00012840	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2239
2277	21:48:58.578	0.00003358	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2240
2278	21:48:58.578	0.00028444	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2241
2279	21:48:58.578	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2242
2280	21:48:58.578	0.00013669	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2243
2281	21:48:58.578	0.00025916	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2244
2282	21:48:58.578	0.00004188	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2245
2284	21:48:58.578	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2246
2285	21:48:58.578	0.00017027	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2247
2286	21:48:58.578	0.00009798	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2248
2287	21:48:58.578	0.00011575	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2249
2288	21:48:58.578	0.00006479	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2250
2289	21:48:58.578	0.00009086	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2251
2290	21:48:58.578	0.00008178	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2252
2291	21:48:58.578	0.00013235	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2253
2292	21:48:58.578	0.00000395	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2254
2293	21:48:58.578	0.00001501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2255
2294	21:48:58.578	0.00010548	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2256
2295	21:48:58.578	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2257
2296	21:48:58.578	0.00002449	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2258
2297	21:48:58.578	0.00010232	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2259
2298	21:48:58.578	0.00000158	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2260
2299	21:48:58.578	0.00007704	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2261
2300	21:48:58.578	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2262
2301	21:48:58.578	0.00017501	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2263
2302	21:48:58.578	0.00014933	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2264
2303	21:48:58.578	0.00003714	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2265
2304	21:48:58.578	0.00027259	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2266
2305	21:48:58.578	0.00027733	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2267
2306	21:48:58.578	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2268
2307	21:48:58.578	0.00016711	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2269
2308	21:48:58.578	0.00014104	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2270
2309	21:48:58.578	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2271
2310	21:48:58.578	0.02554115	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2272
2311	21:48:58.610	0.00000672	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2273
2312	21:48:58.610	0.01529917	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2274
2313	21:48:58.610	0.00003279	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
2275
2314	21:48:58.626	0.00028642	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 06 	
2276
2315	21:48:58.626	0.00000474	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2277
2316	21:48:58.626	0.00018923	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2278
2317	21:48:58.626	0.00013314	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 58 	
2279
2318	21:48:58.626	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2280
2319	21:48:58.626	0.00016040	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2281
2320	21:48:58.626	0.00013709	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 0F 	
2282
2321	21:48:58.626	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2283
2322	21:48:58.626	0.00039980	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2284
2323	21:48:58.626	0.00033422	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: F0 	
2285
2324	21:48:58.626	0.00017975	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: 10 	
2286
2325	21:48:58.626	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2287
2326	21:48:58.626	0.00019674	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2288
2327	21:48:58.626	0.00014143	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2289
2328	21:48:58.626	0.00000237	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2290
2329	21:48:58.626	0.00013037	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2291
2330	21:48:58.626	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2292
2331	21:48:58.626	0.00011812	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2293
2332	21:48:58.626	0.00017383	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2294
2333	21:48:58.626	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2295
2334	21:48:58.626	0.00021254	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2296
2335	21:48:58.626	0.00014301	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2297
2336	21:48:58.626	0.00013353	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2298
2337	21:48:58.626	0.00001975	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2299
2338	21:48:58.626	0.00007230	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2300
2339	21:48:58.626	0.00005373	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2301
2340	21:48:58.626	0.00020938	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2302
2341	21:48:58.626	0.00017067	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2303
2342	21:48:58.626	0.00009640	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2304
2343	21:48:58.626	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2305
2344	21:48:58.626	0.00004978	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2306
2345	21:48:58.626	0.00014933	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2307
2346	21:48:58.626	0.00000356	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2308
2347	21:48:58.626	0.00005215	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2309
2348	21:48:58.626	0.00000000	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1		Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2310
2350	21:48:58.626	0.00011180	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2311
2351	21:48:58.626	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2312
2352	21:48:58.626	0.00010469	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2313
2353	21:48:58.626	0.00014420	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2314
2354	21:48:58.626	0.00021926	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2315
2355	21:48:58.626	0.00016514	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2316
2356	21:48:58.626	0.00007072	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2317
2357	21:48:58.626	0.00010272	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2318
2358	21:48:58.626	0.00015170	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2319
2359	21:48:58.626	0.00007822	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2320
2360	21:48:58.626	0.00022558	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2321
2361	21:48:58.626	0.00010627	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2322
2362	21:48:58.626	0.00013195	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2323
2363	21:48:58.626	0.00004069	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2324
2364	21:48:58.626	0.00012049	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2325
2365	21:48:58.626	0.00010153	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2326
2366	21:48:58.626	0.00001146	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2327
2367	21:48:58.626	0.00022677	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2328
2368	21:48:58.626	0.00013432	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2329
2369	21:48:58.626	0.00010588	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2330
2370	21:48:58.626	0.00000198	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2331
2371	21:48:58.626	0.00010627	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2332
2372	21:48:58.626	0.00011694	UV4BAND_E_CPS.	IRP_MJ_WRITE                        	COM1	SUCCESS	Length: 1, Data: FF 	
2333
2373	21:48:58.626	0.00000316	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2334
2374	21:48:58.626	0.00007427	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2335
2375	21:48:58.626	0.00000277	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2336
2376	21:48:58.626	0.02698312	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2337
2377	21:48:58.657	0.00000593	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING	
2338
2378	21:48:58.657	0.00042272	UV4BAND_E_CPS.	IOCTL_SERIAL_WAIT_ON_MASK           	COM1	SUCCESS		
2339
2379	21:48:58.657	0.00000277	UV4BAND_E_CPS.	IRP_MJ_READ                         	COM1	SUCCESS	Length: 1, Data: 06 	
2340
2380	21:48:58.657	0.00017659	UV4BAND_E_CPS.	IOCTL_SERIAL_SET_WAIT_MASK          	COM1	SUCCESS	Mask:	
2341
2381	21:48:58.657	0.00018647	UV4BAND_E_CPS.	IOCTL_SERIAL_CLR_DTR                	COM1	SUCCESS		
2342
2382	21:48:58.657	0.00006993	UV4BAND_E_CPS.	IOCTL_SERIAL_PURGE                  	COM1	SUCCESS	Purge: TXABORT RXABORT TXCLEAR RXCLEAR	
2343
2383	21:48:58.657	0.01677156	UV4BAND_E_CPS.	IRP_MJ_CLOSE                        	COM1	SUCCESS	Port Closed