SUDT ACCESSPORT LOG FILE - Monitor mode Monitor: COM1 Create Time: 2016-12-01, 21:41:01 Computer Name: Ðüø£µF System version: (Build 9200) # Time Duration (s) Process Request Port Result Data ( Hex ) 1 21:40:22.500 0.11692884 UV4BAND_E_CPS. IRP_MJ_CREATE COM1 SUCCESS Port Opened 2 21:40:22.625 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3 21:40:22.625 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE COM1 SUCCESS InSize: 1024, OutSize: 512 4 21:40:22.625 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 5 21:40:22.625 0.00000079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_TIMEOUTS COM1 SUCCESS ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000 6 21:40:22.625 0.06179953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_BAUD_RATE COM1 SUCCESS Baud Rate: 9600 7 21:40:22.625 0.06173869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8 21:40:22.688 0.00054123 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_RTS COM1 SUCCESS 9 21:40:22.688 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10 21:40:22.688 0.00194884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11 21:40:22.688 0.00044128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_DTR COM1 SUCCESS 12 21:40:22.688 0.00043536 UV4BAND_E_CPS. IOCTL_SERIAL_SET_LINE_CONTROL COM1 SUCCESS StopBits: 1, Parity: No, DataBits: 8 13 21:40:22.688 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_CHARS COM1 SUCCESS EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13 14 21:40:22.688 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_HANDFLOW COM1 SUCCESS ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256 15 21:40:22.688 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: 16 21:40:22.688 0.00027733 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_DTR COM1 SUCCESS 17 21:40:22.688 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 18 21:40:22.688 0.05216950 UV4BAND_E_CPS. IRP_MJ_CLOSE COM1 SUCCESS Port Closed 19 21:40:22.734 0.11786158 UV4BAND_E_CPS. IRP_MJ_CREATE COM1 SUCCESS Port Opened 20 21:40:22.860 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21 21:40:22.860 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE COM1 SUCCESS InSize: 1024, OutSize: 512 22 21:40:22.860 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 23 21:40:22.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_TIMEOUTS COM1 SUCCESS ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000 24 21:40:22.860 0.06105128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_BAUD_RATE COM1 SUCCESS Baud Rate: 9600 25 21:40:22.860 0.06138985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26 21:40:22.922 0.00037926 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_RTS COM1 SUCCESS 27 21:40:22.922 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_DTR COM1 SUCCESS 28 21:40:22.922 0.00125116 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 29 21:40:22.922 0.00045630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_LINE_CONTROL COM1 SUCCESS StopBits: 1, Parity: No, DataBits: 8 30 21:40:22.922 0.00035951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_CHARS COM1 SUCCESS EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13 31 21:40:22.922 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_HANDFLOW COM1 SUCCESS ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256 32 21:40:22.922 0.33480151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 33 21:40:22.922 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 34 21:40:23.250 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 35 21:40:23.250 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 36 21:40:23.250 0.00648455 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 37 21:40:23.266 0.00036820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 38 21:40:23.266 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 39 21:40:23.266 0.01538094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 40 21:40:23.281 0.00031921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 41 21:40:23.281 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 42 21:40:23.281 0.01566657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 43 21:40:23.297 0.00034094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 44 21:40:23.297 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 45 21:40:23.297 0.01556465 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 46 21:40:23.313 0.00037610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 47 21:40:23.313 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 48 21:40:23.313 0.01539793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 49 21:40:23.328 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 50 21:40:23.328 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 51 21:40:23.328 0.01573848 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 52 21:40:23.344 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: DC 53 21:40:23.344 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 54 21:40:23.344 0.01537897 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 55 21:40:23.360 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 56 21:40:23.360 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 57 21:40:23.360 0.00216296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 58 21:40:23.360 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 59 21:40:23.360 0.00683339 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 60 21:40:23.360 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 61 21:40:23.360 0.00598124 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 62 21:40:23.375 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 63 21:40:23.375 0.00981136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 64 21:40:23.375 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 65 21:40:23.375 0.00947121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 66 21:40:23.391 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 67 21:40:23.391 0.01001482 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 68 21:40:23.391 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 69 21:40:23.391 0.01010331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 70 21:40:23.407 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 71 21:40:23.407 0.00961028 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 72 21:40:23.422 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 73 21:40:23.422 0.00980978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 74 21:40:23.422 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 75 21:40:23.422 0.00981215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 76 21:40:23.438 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 77 21:40:23.438 0.00947240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 78 21:40:23.453 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 79 21:40:23.453 0.00976316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 80 21:40:23.453 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 81 21:40:23.453 0.01013097 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 82 21:40:23.469 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 83 21:40:23.469 0.00926894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 84 21:40:23.485 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 85 21:40:23.485 0.00985166 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 86 21:40:23.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 87 21:40:23.485 0.00992988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 88 21:40:23.500 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 89 21:40:23.500 0.00969403 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 90 21:40:23.516 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 91 21:40:23.516 0.01004445 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 92 21:40:23.516 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 93 21:40:23.516 0.00950440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 94 21:40:23.532 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 95 21:40:23.532 0.00990104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 96 21:40:23.532 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 97 21:40:23.532 0.01017126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 98 21:40:23.547 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 99 21:40:23.547 0.00940405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 100 21:40:23.563 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 101 21:40:23.563 0.00970272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 102 21:40:23.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 103 21:40:23.563 0.00989907 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 104 21:40:23.579 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 105 21:40:23.579 0.00973353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 106 21:40:23.594 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 107 21:40:23.594 0.00978805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 108 21:40:23.594 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 109 21:40:23.594 0.00979161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 110 21:40:23.610 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 111 21:40:23.610 0.00977897 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 112 21:40:23.626 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 113 21:40:23.626 0.01016692 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 115 21:40:23.626 0.00929107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 116 21:40:23.641 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 117 21:40:23.641 0.00976119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 118 21:40:23.641 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 119 21:40:23.641 0.01012030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 120 21:40:23.657 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 121 21:40:23.657 0.00925709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 122 21:40:23.672 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 123 21:40:23.672 0.00996860 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 124 21:40:23.672 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 125 21:40:23.672 0.00947674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 126 21:40:23.688 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 127 21:40:23.688 0.00961462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 128 21:40:23.704 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 129 21:40:23.704 0.00992830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 130 21:40:23.704 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 131 21:40:23.704 0.00954628 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 132 21:40:23.719 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 133 21:40:23.719 0.00982479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 134 21:40:23.735 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 135 21:40:23.735 0.01016850 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 136 21:40:23.735 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 137 21:40:23.735 0.00929107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 138 21:40:23.751 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 139 21:40:23.751 0.00965176 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 140 21:40:23.766 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 141 21:40:23.766 0.00995991 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 142 21:40:23.766 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 143 21:40:23.766 0.00986153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 144 21:40:23.782 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 145 21:40:23.782 0.00971418 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 146 21:40:23.782 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 147 21:40:23.782 0.00974855 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 148 21:40:23.797 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 149 21:40:23.797 0.00978173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 150 21:40:23.813 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 151 21:40:23.813 0.00995595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 152 21:40:23.813 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 153 21:40:23.813 0.00971141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 154 21:40:23.828 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 155 21:40:23.828 0.00964623 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 156 21:40:23.844 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 157 21:40:23.844 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 158 21:40:23.844 0.01007013 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 159 21:40:23.844 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 160 21:40:23.844 0.00004622 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 161 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 162 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 163 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07 164 21:40:23.844 0.00012879 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 165 21:40:23.844 0.00002568 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 166 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 167 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 168 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 169 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 170 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 171 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 172 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 173 21:40:23.844 0.00009481 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 174 21:40:23.844 0.00004662 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 175 21:40:23.844 0.00008849 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02 176 21:40:23.844 0.00001106 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 177 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 178 21:40:23.844 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02 179 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07 180 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 181 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 182 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 183 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 184 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 185 21:40:23.844 0.00005649 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 56 186 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 43 187 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32 188 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30 189 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30 190 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32 191 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 192 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 193 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 194 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 195 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 08 196 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 197 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 198 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 199 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 200 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 05 201 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 202 21:40:23.844 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 203 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 09 204 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 205 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 206 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 207 21:40:23.844 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 55 208 21:40:23.844 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 209 21:40:23.844 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 210 21:40:23.844 0.04479449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 211 21:40:23.891 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: 212 21:40:23.891 0.00041798 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_DTR COM1 SUCCESS 213 21:40:23.891 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 214 21:40:23.891 0.02377719 UV4BAND_E_CPS. IRP_MJ_CLOSE COM1 SUCCESS Port Closed