SUDT ACCESSPORT LOG FILE - Monitor mode Monitor: COM1 Create Time: 2016-12-01, 21:47:35 Computer Name: ÐüB£µF System version: (Build 9200) # Time Duration (s) Process Request Port Result Data ( Hex ) 1 21:46:54.235 0.12950247 UV4BAND_E_CPS. IRP_MJ_CREATE COM1 SUCCESS Port Opened 2 21:46:54.376 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3 21:46:54.376 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE COM1 SUCCESS InSize: 1024, OutSize: 512 4 21:46:54.376 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 5 21:46:54.376 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_TIMEOUTS COM1 SUCCESS ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000 6 21:46:54.376 0.06108249 UV4BAND_E_CPS. IOCTL_SERIAL_SET_BAUD_RATE COM1 SUCCESS Baud Rate: 9600 7 21:46:54.376 0.06102560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8 21:46:54.438 0.00067753 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_RTS COM1 SUCCESS 9 21:46:54.438 0.00106983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10 21:46:54.438 0.00035081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_DTR COM1 SUCCESS 11 21:46:54.438 0.00034173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_LINE_CONTROL COM1 SUCCESS StopBits: 1, Parity: No, DataBits: 8 12 21:46:54.438 0.02996268 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13 21:46:54.438 0.00028444 UV4BAND_E_CPS. IOCTL_SERIAL_SET_CHARS COM1 SUCCESS EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13 14 21:46:54.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_HANDFLOW COM1 SUCCESS ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256 15 21:46:54.438 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 16 21:46:54.438 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 17 21:46:54.469 0.00041086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 18 21:46:54.469 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 20 19 21:46:54.469 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21 21:46:54.469 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22 21:46:54.469 0.00033067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23 21:46:54.469 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 24 21:46:54.469 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 25 21:46:54.469 0.00022716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26 21:46:54.469 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 27 21:46:54.469 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 28 21:46:54.469 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 29 21:46:54.469 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 30 21:46:54.469 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 32 21:46:54.469 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 33 21:46:54.469 0.00036622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: DC 34 21:46:54.469 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 35 21:46:54.469 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 36 21:46:54.469 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 37 21:46:54.469 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 38 21:46:54.469 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 39 21:46:54.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 40 21:46:54.469 0.00646598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 41 21:46:54.469 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 42 21:46:54.469 0.00653472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 43 21:46:54.484 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 44 21:46:54.484 0.00578055 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 45 21:46:54.484 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 46 21:46:54.484 0.01001442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 47 21:46:54.500 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 48 21:46:54.500 0.00997966 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 49 21:46:54.500 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 50 21:46:54.500 0.00954549 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 51 21:46:54.516 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 52 21:46:54.516 0.00950716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 53 21:46:54.531 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 54 21:46:54.531 0.01060583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 55 21:46:54.531 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 56 21:46:54.531 0.00886084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 57 21:46:54.547 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 58 21:46:54.547 0.00959645 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 59 21:46:54.547 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 60 21:46:54.547 0.00945620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 61 21:46:54.563 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 62 21:46:54.563 0.01001837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 63 21:46:54.578 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 64 21:46:54.578 0.00981531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 65 21:46:54.578 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 66 21:46:54.578 0.00956445 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 67 21:46:54.594 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 68 21:46:54.594 0.00987418 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 69 21:46:54.610 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 70 21:46:54.610 0.01035813 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 71 21:46:54.610 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 72 21:46:54.610 0.00914331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 73 21:46:54.625 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 74 21:46:54.625 0.00990420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 75 21:46:54.641 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 76 21:46:54.641 0.00980386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 77 21:46:54.641 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 78 21:46:54.641 0.00978292 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 79 21:46:54.657 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 80 21:46:54.657 0.01008474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 81 21:46:54.672 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 82 21:46:54.672 0.00929107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 83 21:46:54.672 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 84 21:46:54.672 0.00979319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 85 21:46:54.688 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 86 21:46:54.688 0.00985640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 87 21:46:54.688 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 88 21:46:54.688 0.00947279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 89 21:46:54.704 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 90 21:46:54.704 0.00960040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 91 21:46:54.719 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 92 21:46:54.719 0.00964070 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 93 21:46:54.719 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 94 21:46:54.719 0.00974736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 95 21:46:54.735 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 96 21:46:54.735 0.00977620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 97 21:46:54.751 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 98 21:46:54.751 0.00979437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 99 21:46:54.751 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 100 21:46:54.751 0.00969995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 101 21:46:54.766 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 102 21:46:54.766 0.00979595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 103 21:46:54.782 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 104 21:46:54.782 0.00961936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 105 21:46:54.782 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 106 21:46:54.782 0.00989353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 107 21:46:54.798 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 108 21:46:54.798 0.01020524 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 109 21:46:54.798 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 110 21:46:54.798 0.00951625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 111 21:46:54.813 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 112 21:46:54.813 0.00965768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 113 21:46:54.828 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 114 21:46:54.828 0.00991289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 115 21:46:54.828 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 116 21:46:54.828 0.00981136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 117 21:46:54.844 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 118 21:46:54.844 0.00979437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 119 21:46:54.859 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 120 21:46:54.859 0.00955931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 121 21:46:54.859 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 122 21:46:54.859 0.00990025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 123 21:46:54.875 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 124 21:46:54.875 0.00996702 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 125 21:46:54.891 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 126 21:46:54.891 0.00937126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 127 21:46:54.891 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 129 21:46:54.906 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 130 21:46:54.906 0.00984494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 131 21:46:54.922 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 132 21:46:54.922 0.00991013 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 133 21:46:54.922 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 134 21:46:54.922 0.00989314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 135 21:46:54.938 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 136 21:46:54.938 0.00952929 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 137 21:46:54.938 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 138 21:46:54.938 0.00983823 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 139 21:46:54.953 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 140 21:46:54.953 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 141 21:46:54.953 0.00142736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 142 21:46:54.953 0.00023348 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 143 21:46:54.953 0.00008573 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 144 21:46:54.953 0.00009837 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 145 21:46:54.953 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 146 21:46:54.953 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07 147 21:46:54.953 0.00006637 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 148 21:46:54.953 0.00000119 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 149 21:46:54.953 0.00000119 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 150 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 151 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 152 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 153 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 154 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 155 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 156 21:46:54.953 0.00007309 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 157 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 158 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02 159 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 160 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 161 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02 162 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07 163 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 164 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 165 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 166 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 167 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 168 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 56 169 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 43 170 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32 171 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30 172 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30 173 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32 174 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 175 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 176 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 177 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 178 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 08 179 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 180 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 181 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 182 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 183 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 05 184 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 185 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 186 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 09 187 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 188 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 189 21:46:54.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 190 21:46:54.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 55 191 21:46:54.953 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 192 21:46:54.953 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 193 21:46:54.953 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 194 21:46:54.953 0.00793719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 195 21:46:54.969 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 196 21:46:54.969 0.01257956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 197 21:46:54.969 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 198 21:46:54.985 0.00029077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 53 199 21:46:54.985 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 200 21:46:54.985 0.00039941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 201 21:46:54.985 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 3D 202 21:46:54.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 203 21:46:54.985 0.00028049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 204 21:46:54.985 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 205 21:46:54.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 206 21:46:54.985 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 207 21:46:54.985 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 208 21:46:54.985 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 209 21:46:54.985 0.08960794 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 210 21:46:55.063 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 211 21:46:55.063 0.00077116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 212 21:46:55.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 213 21:46:55.063 0.00101649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 214 21:46:55.063 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 215 21:46:55.063 0.00081383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 216 21:46:55.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 217 21:46:55.079 0.00118756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 218 21:46:55.079 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 219 21:46:55.079 0.00142933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 220 21:46:55.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 221 21:46:55.079 0.00127091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 222 21:46:55.079 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 223 21:46:55.079 0.00117333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 224 21:46:55.079 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 225 21:46:55.079 0.00135032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 226 21:46:55.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 227 21:46:55.079 0.00129975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 228 21:46:55.079 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 229 21:46:55.079 0.00107852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 230 21:46:55.079 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 231 21:46:55.079 0.00129343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 232 21:46:55.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 233 21:46:55.079 0.00130291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 234 21:46:55.079 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 235 21:46:55.079 0.00130133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 236 21:46:55.079 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 237 21:46:55.079 0.00121482 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 238 21:46:55.094 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 239 21:46:55.094 0.00129501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 240 21:46:55.094 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 241 21:46:55.094 0.00135862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 242 21:46:55.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 243 21:46:55.094 0.00131674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 244 21:46:55.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 245 21:46:55.094 0.00135862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 246 21:46:55.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 247 21:46:55.094 0.00109432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 248 21:46:55.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 249 21:46:55.094 0.00069452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 250 21:46:55.094 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 58 251 21:46:55.094 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 3D 252 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: F0 253 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 10 254 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 255 21:46:55.094 0.00004148 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 256 21:46:55.094 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 257 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 258 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 259 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 260 21:46:55.094 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 261 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 262 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 263 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 264 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 265 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 266 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 267 21:46:55.094 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 268 21:46:55.094 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 269 21:46:55.094 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 270 21:46:55.094 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 271 21:46:55.094 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 272 21:46:55.094 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 273 21:46:55.094 0.00184296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 274 21:46:55.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 275 21:46:55.094 0.00494578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 276 21:46:55.094 0.00000158 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 277 21:46:55.110 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 278 21:46:55.110 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 279 21:46:55.110 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 280 21:46:55.110 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 281 21:46:55.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 282 21:46:55.110 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 283 21:46:55.110 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 284 21:46:55.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 285 21:46:55.110 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 286 21:46:55.110 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 287 21:46:55.110 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 288 21:46:55.110 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 289 21:46:55.110 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 290 21:46:55.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 291 21:46:55.110 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 292 21:46:55.110 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 293 21:46:55.110 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 294 21:46:55.110 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 295 21:46:55.110 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 296 21:46:55.110 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 297 21:46:55.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 298 21:46:55.110 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 299 21:46:55.110 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 300 21:46:55.110 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 301 21:46:55.110 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 302 21:46:55.110 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 303 21:46:55.110 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 304 21:46:55.110 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 305 21:46:55.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 306 21:46:55.110 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 307 21:46:55.110 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 309 21:46:55.110 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 310 21:46:55.110 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 311 21:46:55.110 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 312 21:46:55.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 313 21:46:55.110 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 314 21:46:55.110 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 315 21:46:55.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 316 21:46:55.110 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 317 21:46:55.110 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 318 21:46:55.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 319 21:46:55.110 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 320 21:46:55.110 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 321 21:46:55.110 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 322 21:46:55.110 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 323 21:46:55.110 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 324 21:46:55.110 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 325 21:46:55.110 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 326 21:46:55.110 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 327 21:46:55.110 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 328 21:46:55.110 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 329 21:46:55.110 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 330 21:46:55.110 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 331 21:46:55.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 332 21:46:55.110 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 333 21:46:55.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 334 21:46:55.110 0.07368852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 335 21:46:55.188 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 336 21:46:55.188 0.01504672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 337 21:46:55.188 0.00014380 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 338 21:46:55.203 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 339 21:46:55.203 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 340 21:46:55.203 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 341 21:46:55.203 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 342 21:46:55.203 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 343 21:46:55.203 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 344 21:46:55.203 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 345 21:46:55.203 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 346 21:46:55.203 0.00048119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 347 21:46:55.203 0.00036425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 348 21:46:55.203 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 349 21:46:55.203 0.00043615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 350 21:46:55.203 0.00031565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 351 21:46:55.203 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 352 21:46:55.203 0.00040020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 353 21:46:55.203 0.00032593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 354 21:46:55.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 355 21:46:55.203 0.00032830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 356 21:46:55.203 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 360 21:46:55.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 361 21:46:55.203 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 362 21:46:55.203 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 363 21:46:55.203 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 364 21:46:55.203 0.00031802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 365 21:46:55.203 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 366 21:46:55.203 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 367 21:46:55.203 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 368 21:46:55.203 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 369 21:46:55.203 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 370 21:46:55.203 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 372 21:46:55.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 373 21:46:55.203 0.00031210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 374 21:46:55.203 0.00026983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 375 21:46:55.203 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 376 21:46:55.203 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 377 21:46:55.203 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 378 21:46:55.203 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 379 21:46:55.203 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 380 21:46:55.203 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 381 21:46:55.203 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 382 21:46:55.203 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 383 21:46:55.203 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 384 21:46:55.203 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 385 21:46:55.203 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 386 21:46:55.203 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 387 21:46:55.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 388 21:46:55.203 0.00032198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 389 21:46:55.203 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 390 21:46:55.203 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 391 21:46:55.203 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 392 21:46:55.203 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 393 21:46:55.203 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 394 21:46:55.203 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 395 21:46:55.203 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 396 21:46:55.203 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 397 21:46:55.203 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 398 21:46:55.203 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 400 21:46:55.203 0.02603181 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 401 21:46:55.235 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 402 21:46:55.235 0.01355181 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 403 21:46:55.235 0.00002173 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 404 21:46:55.250 0.00035437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 405 21:46:55.250 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 406 21:46:55.250 0.00024454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 407 21:46:55.250 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 408 21:46:55.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 409 21:46:55.250 0.00033383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 410 21:46:55.250 0.00028286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 411 21:46:55.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 412 21:46:55.250 0.00033896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 413 21:46:55.250 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 414 21:46:55.250 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 415 21:46:55.250 0.00030183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 416 21:46:55.250 0.00029669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 417 21:46:55.250 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 418 21:46:55.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 419 21:46:55.250 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 420 21:46:55.250 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 421 21:46:55.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 422 21:46:55.250 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 423 21:46:55.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 424 21:46:55.250 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 425 21:46:55.250 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 426 21:46:55.250 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 427 21:46:55.250 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 428 21:46:55.250 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 429 21:46:55.250 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 430 21:46:55.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 431 21:46:55.250 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 432 21:46:55.250 0.00027852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 433 21:46:55.250 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 434 21:46:55.250 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 435 21:46:55.250 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 436 21:46:55.250 0.00032158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 437 21:46:55.250 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 438 21:46:55.250 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 439 21:46:55.250 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 440 21:46:55.250 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 441 21:46:55.250 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 442 21:46:55.250 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 443 21:46:55.250 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 444 21:46:55.250 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 445 21:46:55.250 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 446 21:46:55.250 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 447 21:46:55.250 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 448 21:46:55.250 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 449 21:46:55.250 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 450 21:46:55.250 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 451 21:46:55.250 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 452 21:46:55.250 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 453 21:46:55.250 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 454 21:46:55.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 455 21:46:55.250 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 456 21:46:55.250 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 457 21:46:55.250 0.00031328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 459 21:46:55.250 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 460 21:46:55.250 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 461 21:46:55.250 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 462 21:46:55.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 463 21:46:55.250 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 464 21:46:55.250 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 465 21:46:55.250 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 466 21:46:55.250 0.02739794 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 467 21:46:55.281 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 468 21:46:55.281 0.01295210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 469 21:46:55.281 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 470 21:46:55.297 0.00032119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 471 21:46:55.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 472 21:46:55.297 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 473 21:46:55.297 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 474 21:46:55.297 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 475 21:46:55.297 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 476 21:46:55.297 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 477 21:46:55.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 478 21:46:55.297 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 479 21:46:55.297 0.00037531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 480 21:46:55.297 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 481 21:46:55.297 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 482 21:46:55.297 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 485 21:46:55.297 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 486 21:46:55.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 487 21:46:55.297 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 488 21:46:55.297 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 489 21:46:55.297 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 490 21:46:55.297 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 491 21:46:55.297 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 492 21:46:55.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 493 21:46:55.297 0.00033501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 494 21:46:55.297 0.00026153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 495 21:46:55.297 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 496 21:46:55.297 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 497 21:46:55.297 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 498 21:46:55.297 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 499 21:46:55.297 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 500 21:46:55.297 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 501 21:46:55.297 0.00027654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 502 21:46:55.297 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 503 21:46:55.297 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 504 21:46:55.297 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 509 21:46:55.297 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 510 21:46:55.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 511 21:46:55.297 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 512 21:46:55.297 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 513 21:46:55.297 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 514 21:46:55.297 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 515 21:46:55.297 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 516 21:46:55.297 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 517 21:46:55.297 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 518 21:46:55.297 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 519 21:46:55.297 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 520 21:46:55.297 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 521 21:46:55.297 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 522 21:46:55.297 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 523 21:46:55.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 524 21:46:55.297 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 525 21:46:55.297 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 526 21:46:55.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 527 21:46:55.297 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 528 21:46:55.297 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 529 21:46:55.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 530 21:46:55.297 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 531 21:46:55.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 532 21:46:55.297 0.02686618 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 533 21:46:55.328 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 534 21:46:55.328 0.01312356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 535 21:46:55.328 0.00003121 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 536 21:46:55.344 0.00028721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 537 21:46:55.344 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 538 21:46:55.344 0.00100504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 539 21:46:55.344 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 540 21:46:55.344 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 541 21:46:55.344 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 542 21:46:55.344 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 543 21:46:55.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 544 21:46:55.344 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 545 21:46:55.344 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 546 21:46:55.344 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 547 21:46:55.344 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 548 21:46:55.344 0.00028405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 549 21:46:55.344 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 550 21:46:55.344 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 551 21:46:55.344 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 552 21:46:55.344 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 553 21:46:55.344 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 554 21:46:55.344 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 555 21:46:55.344 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 556 21:46:55.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 557 21:46:55.344 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 558 21:46:55.344 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 559 21:46:55.344 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 560 21:46:55.344 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 561 21:46:55.344 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 562 21:46:55.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 563 21:46:55.344 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 564 21:46:55.344 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 565 21:46:55.344 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 566 21:46:55.344 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 567 21:46:55.344 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 568 21:46:55.344 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 569 21:46:55.344 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 570 21:46:55.344 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 571 21:46:55.344 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 572 21:46:55.344 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 573 21:46:55.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 574 21:46:55.344 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 575 21:46:55.344 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 576 21:46:55.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 577 21:46:55.344 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 578 21:46:55.344 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 579 21:46:55.344 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 580 21:46:55.344 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 581 21:46:55.344 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 585 21:46:55.344 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 586 21:46:55.344 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 587 21:46:55.344 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 588 21:46:55.344 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 589 21:46:55.344 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 590 21:46:55.344 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 591 21:46:55.344 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 592 21:46:55.344 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 593 21:46:55.344 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 594 21:46:55.344 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 595 21:46:55.344 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 596 21:46:55.344 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 597 21:46:55.344 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 598 21:46:55.344 0.02580663 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 599 21:46:55.375 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 600 21:46:55.375 0.01407092 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 601 21:46:55.375 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 602 21:46:55.391 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 603 21:46:55.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 604 21:46:55.391 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 605 21:46:55.391 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 606 21:46:55.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 607 21:46:55.391 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 608 21:46:55.391 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 609 21:46:55.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 610 21:46:55.391 0.00027536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 611 21:46:55.391 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 612 21:46:55.391 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 613 21:46:55.391 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 614 21:46:55.391 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 615 21:46:55.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 616 21:46:55.391 0.00025363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 617 21:46:55.391 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 618 21:46:55.391 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 619 21:46:55.391 0.00024099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 620 21:46:55.391 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 621 21:46:55.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 622 21:46:55.391 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 623 21:46:55.391 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 624 21:46:55.391 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 625 21:46:55.391 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 626 21:46:55.391 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 627 21:46:55.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 628 21:46:55.391 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 629 21:46:55.391 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 630 21:46:55.391 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 631 21:46:55.391 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 632 21:46:55.391 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 633 21:46:55.391 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 634 21:46:55.391 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 635 21:46:55.391 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 636 21:46:55.391 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 637 21:46:55.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 638 21:46:55.391 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 639 21:46:55.391 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 640 21:46:55.391 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 641 21:46:55.391 0.00024454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 642 21:46:55.391 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 643 21:46:55.391 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 644 21:46:55.391 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 645 21:46:55.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 646 21:46:55.391 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 647 21:46:55.391 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 648 21:46:55.391 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 649 21:46:55.391 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 650 21:46:55.391 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 651 21:46:55.391 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 652 21:46:55.391 0.00030499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 653 21:46:55.391 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 654 21:46:55.391 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 655 21:46:55.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 656 21:46:55.391 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 658 21:46:55.391 0.00030775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 659 21:46:55.391 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 660 21:46:55.391 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 661 21:46:55.391 0.00027259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 662 21:46:55.391 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 663 21:46:55.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 664 21:46:55.391 0.02674371 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 665 21:46:55.422 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 666 21:46:55.422 0.01363517 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 668 21:46:55.438 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 669 21:46:55.438 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 670 21:46:55.438 0.00033067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 671 21:46:55.438 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 672 21:46:55.438 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 673 21:46:55.438 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 674 21:46:55.438 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 675 21:46:55.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 676 21:46:55.438 0.00051358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 677 21:46:55.438 0.00040849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 678 21:46:55.438 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 679 21:46:55.438 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 680 21:46:55.438 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 681 21:46:55.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 682 21:46:55.438 0.00038598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 683 21:46:55.438 0.00028563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 684 21:46:55.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 685 21:46:55.438 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 686 21:46:55.438 0.00023506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 687 21:46:55.438 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 688 21:46:55.438 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 689 21:46:55.438 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 690 21:46:55.438 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 691 21:46:55.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 692 21:46:55.438 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 693 21:46:55.438 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 694 21:46:55.438 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 695 21:46:55.438 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 696 21:46:55.438 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 697 21:46:55.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 698 21:46:55.438 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 699 21:46:55.438 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 700 21:46:55.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 701 21:46:55.438 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 702 21:46:55.438 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 703 21:46:55.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 704 21:46:55.438 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 705 21:46:55.438 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 706 21:46:55.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 707 21:46:55.438 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 708 21:46:55.438 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 709 21:46:55.438 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 710 21:46:55.438 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 711 21:46:55.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 712 21:46:55.438 0.00037610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 713 21:46:55.438 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 714 21:46:55.438 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 715 21:46:55.438 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 716 21:46:55.438 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 717 21:46:55.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 718 21:46:55.438 0.00029195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 719 21:46:55.438 0.00033975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 720 21:46:55.438 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 721 21:46:55.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 722 21:46:55.438 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 723 21:46:55.438 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 724 21:46:55.438 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 725 21:46:55.438 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 726 21:46:55.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 727 21:46:55.438 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 728 21:46:55.438 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 729 21:46:55.438 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 730 21:46:55.438 0.02552100 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 731 21:46:55.469 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 732 21:46:55.469 0.02871744 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 733 21:46:55.469 0.00002607 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 734 21:46:55.500 0.00034331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 735 21:46:55.500 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 736 21:46:55.500 0.00036504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 737 21:46:55.500 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 738 21:46:55.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 739 21:46:55.500 0.00040178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 740 21:46:55.500 0.00031881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 741 21:46:55.500 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 742 21:46:55.500 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 743 21:46:55.500 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 744 21:46:55.500 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 745 21:46:55.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 746 21:46:55.500 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 747 21:46:55.500 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 748 21:46:55.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 749 21:46:55.500 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 750 21:46:55.500 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 751 21:46:55.500 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 752 21:46:55.500 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 753 21:46:55.500 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 754 21:46:55.500 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 755 21:46:55.500 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 756 21:46:55.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 757 21:46:55.500 0.00037333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 758 21:46:55.500 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 759 21:46:55.500 0.00030262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 760 21:46:55.500 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 761 21:46:55.500 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 762 21:46:55.500 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 763 21:46:55.500 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 764 21:46:55.500 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 765 21:46:55.500 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 766 21:46:55.500 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 767 21:46:55.500 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 768 21:46:55.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 769 21:46:55.500 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 770 21:46:55.500 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 771 21:46:55.500 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 772 21:46:55.500 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 773 21:46:55.500 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 774 21:46:55.500 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 775 21:46:55.500 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 776 21:46:55.500 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 777 21:46:55.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 778 21:46:55.500 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 779 21:46:55.500 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 780 21:46:55.500 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 783 21:46:55.500 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 784 21:46:55.500 0.00030973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 785 21:46:55.500 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 786 21:46:55.500 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 787 21:46:55.500 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 788 21:46:55.500 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 789 21:46:55.500 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 790 21:46:55.500 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 791 21:46:55.500 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 792 21:46:55.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 793 21:46:55.500 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 794 21:46:55.500 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 795 21:46:55.500 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 796 21:46:55.500 0.02646362 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 797 21:46:55.531 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 798 21:46:55.531 0.01328870 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 799 21:46:55.531 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 800 21:46:55.547 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 801 21:46:55.547 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 802 21:46:55.547 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 803 21:46:55.547 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 804 21:46:55.547 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 805 21:46:55.547 0.00028484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 806 21:46:55.547 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 807 21:46:55.547 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 40 808 21:46:55.547 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 809 21:46:55.547 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 812 21:46:55.547 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 813 21:46:55.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 814 21:46:55.547 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 815 21:46:55.547 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 816 21:46:55.547 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 817 21:46:55.547 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 818 21:46:55.547 0.00025047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 819 21:46:55.547 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 820 21:46:55.547 0.00030262 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 821 21:46:55.547 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 822 21:46:55.547 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 823 21:46:55.547 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 826 21:46:55.547 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 827 21:46:55.547 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 828 21:46:55.547 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 829 21:46:55.547 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 830 21:46:55.547 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 831 21:46:55.547 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 834 21:46:55.547 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 835 21:46:55.547 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 836 21:46:55.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 837 21:46:55.547 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 838 21:46:55.547 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 839 21:46:55.547 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 840 21:46:55.547 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 841 21:46:55.547 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 842 21:46:55.547 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 843 21:46:55.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 844 21:46:55.547 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 845 21:46:55.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 846 21:46:55.547 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 847 21:46:55.547 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 848 21:46:55.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 849 21:46:55.547 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 850 21:46:55.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 851 21:46:55.547 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 852 21:46:55.547 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 853 21:46:55.547 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 854 21:46:55.547 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 856 21:46:55.547 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 857 21:46:55.547 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 858 21:46:55.547 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 859 21:46:55.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 860 21:46:55.547 0.02589631 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 861 21:46:55.578 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 862 21:46:55.578 0.01440435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 863 21:46:55.578 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 864 21:46:55.594 0.00029946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 865 21:46:55.594 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 866 21:46:55.594 0.00030933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 867 21:46:55.594 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 868 21:46:55.594 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 869 21:46:55.594 0.00039625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 870 21:46:55.594 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 871 21:46:55.594 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 872 21:46:55.594 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 873 21:46:55.594 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 874 21:46:55.594 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 875 21:46:55.594 0.00027852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 876 21:46:55.594 0.00029867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 877 21:46:55.594 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 878 21:46:55.594 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 879 21:46:55.594 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 880 21:46:55.594 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 881 21:46:55.594 0.00034647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 883 21:46:55.594 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 884 21:46:55.594 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 885 21:46:55.594 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 886 21:46:55.594 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 887 21:46:55.594 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 888 21:46:55.594 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 889 21:46:55.594 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 890 21:46:55.594 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 891 21:46:55.594 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 892 21:46:55.594 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 893 21:46:55.594 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 894 21:46:55.594 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 895 21:46:55.594 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 896 21:46:55.594 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 897 21:46:55.594 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 898 21:46:55.594 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 899 21:46:55.594 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 900 21:46:55.594 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 901 21:46:55.594 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 902 21:46:55.594 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 903 21:46:55.594 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 904 21:46:55.594 0.00033225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 905 21:46:55.594 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 906 21:46:55.594 0.00028168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 907 21:46:55.594 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 908 21:46:55.594 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 909 21:46:55.594 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 910 21:46:55.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 911 21:46:55.594 0.00029037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 912 21:46:55.594 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 913 21:46:55.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 914 21:46:55.594 0.00032790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 915 21:46:55.594 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 916 21:46:55.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 917 21:46:55.594 0.00026390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 918 21:46:55.594 0.00026667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 919 21:46:55.594 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 920 21:46:55.594 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 921 21:46:55.594 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 922 21:46:55.594 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 923 21:46:55.594 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 924 21:46:55.594 0.02625068 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 925 21:46:55.625 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 926 21:46:55.625 0.01343684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 927 21:46:55.625 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 928 21:46:55.641 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 929 21:46:55.641 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 930 21:46:55.641 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 931 21:46:55.641 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 932 21:46:55.641 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 933 21:46:55.641 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 934 21:46:55.641 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 935 21:46:55.641 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 936 21:46:55.641 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 937 21:46:55.641 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 938 21:46:55.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 939 21:46:55.641 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 940 21:46:55.641 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 941 21:46:55.641 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 942 21:46:55.641 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 943 21:46:55.641 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 944 21:46:55.641 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 945 21:46:55.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 946 21:46:55.641 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 947 21:46:55.641 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 948 21:46:55.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 949 21:46:55.641 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 950 21:46:55.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 951 21:46:55.641 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 952 21:46:55.641 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 953 21:46:55.641 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 954 21:46:55.641 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 955 21:46:55.641 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 956 21:46:55.641 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 957 21:46:55.641 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 958 21:46:55.641 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 959 21:46:55.641 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 960 21:46:55.641 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 961 21:46:55.641 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 962 21:46:55.641 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 963 21:46:55.641 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 964 21:46:55.641 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 965 21:46:55.641 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 966 21:46:55.641 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 967 21:46:55.641 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 968 21:46:55.641 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 969 21:46:55.641 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 970 21:46:55.641 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 971 21:46:55.641 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 972 21:46:55.641 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 973 21:46:55.641 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 974 21:46:55.641 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 975 21:46:55.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 976 21:46:55.641 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 977 21:46:55.641 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 978 21:46:55.641 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 979 21:46:55.641 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 980 21:46:55.641 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 981 21:46:55.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 982 21:46:55.641 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 983 21:46:55.641 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 984 21:46:55.641 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 985 21:46:55.641 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 986 21:46:55.641 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 987 21:46:55.641 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 988 21:46:55.641 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 989 21:46:55.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 990 21:46:55.641 0.02806164 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 991 21:46:55.673 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 992 21:46:55.673 0.00011891 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 993 21:46:55.673 0.02974065 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 994 21:46:55.703 0.00027180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 995 21:46:55.703 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 996 21:46:55.703 0.00031644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 997 21:46:55.703 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 998 21:46:55.703 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 999 21:46:55.703 0.00033778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1000 21:46:55.703 0.00023664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1001 21:46:55.703 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1002 21:46:55.703 0.00046775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1003 21:46:55.703 0.00033185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1004 21:46:55.703 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1005 21:46:55.703 0.00029709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1006 21:46:55.703 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1007 21:46:55.703 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1008 21:46:55.703 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1009 21:46:55.703 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1010 21:46:55.703 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1011 21:46:55.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1012 21:46:55.703 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1013 21:46:55.703 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1014 21:46:55.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1015 21:46:55.703 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1016 21:46:55.703 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1017 21:46:55.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1018 21:46:55.703 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1019 21:46:55.703 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1020 21:46:55.703 0.00030183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1021 21:46:55.703 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1022 21:46:55.703 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 1023 21:46:55.703 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1024 21:46:55.703 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1025 21:46:55.703 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1026 21:46:55.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1027 21:46:55.703 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1028 21:46:55.703 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1029 21:46:55.703 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1030 21:46:55.703 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1031 21:46:55.703 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1032 21:46:55.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1033 21:46:55.703 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1034 21:46:55.703 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1035 21:46:55.703 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1036 21:46:55.703 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1037 21:46:55.703 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1038 21:46:55.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1039 21:46:55.703 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1040 21:46:55.703 0.00074390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1041 21:46:55.703 0.00064988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1042 21:46:55.703 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1043 21:46:55.703 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1044 21:46:55.703 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1045 21:46:55.703 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1046 21:46:55.703 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1047 21:46:55.703 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1048 21:46:55.703 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1049 21:46:55.703 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1050 21:46:55.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1051 21:46:55.703 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1052 21:46:55.703 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1053 21:46:55.703 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1054 21:46:55.703 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1055 21:46:55.703 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1056 21:46:55.703 0.02457719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1057 21:46:55.735 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1058 21:46:55.735 0.01439171 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1059 21:46:55.735 0.00001817 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1060 21:46:55.750 0.00033264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1061 21:46:55.750 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1062 21:46:55.750 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1063 21:46:55.750 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1064 21:46:55.750 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1065 21:46:55.750 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1066 21:46:55.750 0.00028484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1067 21:46:55.750 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 1068 21:46:55.750 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1069 21:46:55.750 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1070 21:46:55.750 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1071 21:46:55.750 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1072 21:46:55.750 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1073 21:46:55.750 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1074 21:46:55.750 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1075 21:46:55.750 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1076 21:46:55.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1077 21:46:55.750 0.00028365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1078 21:46:55.750 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1079 21:46:55.750 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1080 21:46:55.750 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1081 21:46:55.750 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1082 21:46:55.750 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1083 21:46:55.750 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1084 21:46:55.750 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1085 21:46:55.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1086 21:46:55.750 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1087 21:46:55.750 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1088 21:46:55.750 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1089 21:46:55.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1090 21:46:55.750 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1091 21:46:55.750 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1092 21:46:55.750 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1093 21:46:55.750 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1094 21:46:55.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1095 21:46:55.750 0.00029748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1096 21:46:55.750 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1097 21:46:55.750 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1098 21:46:55.750 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1099 21:46:55.750 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1100 21:46:55.750 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1101 21:46:55.750 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1102 21:46:55.750 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1103 21:46:55.750 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1104 21:46:55.750 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1105 21:46:55.750 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1106 21:46:55.750 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1107 21:46:55.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1108 21:46:55.750 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1109 21:46:55.750 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1110 21:46:55.750 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1111 21:46:55.750 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1112 21:46:55.750 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1113 21:46:55.750 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1114 21:46:55.750 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1115 21:46:55.750 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1116 21:46:55.750 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1117 21:46:55.750 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1118 21:46:55.750 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1119 21:46:55.750 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1120 21:46:55.750 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1121 21:46:55.750 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1122 21:46:55.750 0.02717749 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1123 21:46:55.782 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1124 21:46:55.782 0.01272771 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1125 21:46:55.782 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1126 21:46:55.797 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1127 21:46:55.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1128 21:46:55.797 0.00032988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1129 21:46:55.797 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1130 21:46:55.797 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1131 21:46:55.797 0.00035437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1132 21:46:55.797 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1133 21:46:55.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1134 21:46:55.797 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1135 21:46:55.797 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 1136 21:46:55.797 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1137 21:46:55.797 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1138 21:46:55.797 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1142 21:46:55.797 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1143 21:46:55.797 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1144 21:46:55.797 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1145 21:46:55.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1146 21:46:55.797 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1147 21:46:55.797 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1148 21:46:55.797 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1149 21:46:55.797 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1150 21:46:55.797 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1151 21:46:55.797 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1152 21:46:55.797 0.00043654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1153 21:46:55.797 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1154 21:46:55.797 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 1155 21:46:55.797 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1156 21:46:55.797 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1157 21:46:55.797 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1158 21:46:55.797 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1159 21:46:55.797 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1160 21:46:55.797 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1161 21:46:55.797 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1163 21:46:55.797 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1164 21:46:55.797 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1165 21:46:55.797 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1166 21:46:55.797 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1167 21:46:55.797 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1168 21:46:55.797 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1169 21:46:55.797 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1170 21:46:55.797 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1171 21:46:55.797 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1172 21:46:55.797 0.00036899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1173 21:46:55.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1174 21:46:55.797 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1175 21:46:55.797 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1176 21:46:55.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1177 21:46:55.797 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1178 21:46:55.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1179 21:46:55.797 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1180 21:46:55.797 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1181 21:46:55.797 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1182 21:46:55.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1183 21:46:55.797 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1184 21:46:55.797 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1185 21:46:55.797 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1186 21:46:55.797 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1187 21:46:55.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1188 21:46:55.797 0.02691991 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1189 21:46:55.829 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1190 21:46:55.829 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1191 21:46:55.829 0.01369956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1192 21:46:55.844 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1193 21:46:55.844 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1194 21:46:55.844 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1195 21:46:55.844 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1196 21:46:55.844 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1197 21:46:55.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1198 21:46:55.844 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1199 21:46:55.844 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 1200 21:46:55.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1201 21:46:55.844 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1202 21:46:55.844 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1203 21:46:55.844 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1204 21:46:55.844 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1205 21:46:55.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1206 21:46:55.844 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1207 21:46:55.844 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1208 21:46:55.844 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1209 21:46:55.844 0.00027338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 1210 21:46:55.844 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1211 21:46:55.844 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1212 21:46:55.844 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1213 21:46:55.844 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1214 21:46:55.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1215 21:46:55.844 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1216 21:46:55.844 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1217 21:46:55.844 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1218 21:46:55.844 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1219 21:46:55.844 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 1220 21:46:55.844 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1221 21:46:55.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1222 21:46:55.844 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1226 21:46:55.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1227 21:46:55.844 0.00028365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1228 21:46:55.844 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1229 21:46:55.844 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1230 21:46:55.844 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1231 21:46:55.844 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1232 21:46:55.844 0.00009126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1233 21:46:55.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1234 21:46:55.844 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1235 21:46:55.844 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1236 21:46:55.844 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1237 21:46:55.844 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1238 21:46:55.844 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1239 21:46:55.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1240 21:46:55.844 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1241 21:46:55.844 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1242 21:46:55.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1243 21:46:55.844 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1244 21:46:55.844 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1245 21:46:55.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1246 21:46:55.844 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1247 21:46:55.844 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1248 21:46:55.844 0.00052227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1249 21:46:55.844 0.00048593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1250 21:46:55.844 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1251 21:46:55.844 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1252 21:46:55.844 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1253 21:46:55.844 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1254 21:46:55.844 0.02792376 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1255 21:46:55.876 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1256 21:46:55.876 0.01586094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1257 21:46:55.876 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1258 21:46:55.893 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1259 21:46:55.893 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1260 21:46:55.893 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1261 21:46:55.893 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1262 21:46:55.893 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1263 21:46:55.893 0.00030301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1264 21:46:55.893 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1265 21:46:55.893 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1266 21:46:55.893 0.00029630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1267 21:46:55.893 0.00025165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 1268 21:46:55.893 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1269 21:46:55.893 0.00035477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1270 21:46:55.893 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1271 21:46:55.893 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1272 21:46:55.893 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1273 21:46:55.893 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1274 21:46:55.893 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1275 21:46:55.893 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1276 21:46:55.893 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1277 21:46:55.893 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1278 21:46:55.893 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1279 21:46:55.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1280 21:46:55.893 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1281 21:46:55.893 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1282 21:46:55.893 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1283 21:46:55.893 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1284 21:46:55.893 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1285 21:46:55.893 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1286 21:46:55.893 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1287 21:46:55.893 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1288 21:46:55.893 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 1289 21:46:55.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1290 21:46:55.893 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1291 21:46:55.893 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1292 21:46:55.893 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1293 21:46:55.893 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1294 21:46:55.893 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1295 21:46:55.893 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1297 21:46:55.893 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1298 21:46:55.893 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1299 21:46:55.893 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1300 21:46:55.893 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1301 21:46:55.893 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1303 21:46:55.893 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1304 21:46:55.893 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1305 21:46:55.893 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1306 21:46:55.893 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1307 21:46:55.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1308 21:46:55.893 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1309 21:46:55.893 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1310 21:46:55.893 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1311 21:46:55.893 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1312 21:46:55.893 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1313 21:46:55.893 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1314 21:46:55.893 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1315 21:46:55.893 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1316 21:46:55.893 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1317 21:46:55.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1318 21:46:55.893 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1319 21:46:55.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1320 21:46:55.893 0.02697364 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1321 21:46:55.922 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1322 21:46:55.922 0.01141571 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1323 21:46:55.922 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1324 21:46:55.938 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1325 21:46:55.938 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1326 21:46:55.938 0.00028681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1327 21:46:55.938 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1328 21:46:55.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1329 21:46:55.938 0.00025521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1330 21:46:55.938 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1331 21:46:55.938 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 1332 21:46:55.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1333 21:46:55.938 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1334 21:46:55.938 0.00047091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1335 21:46:55.938 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1336 21:46:55.938 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1337 21:46:55.938 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1338 21:46:55.938 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1339 21:46:55.938 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1340 21:46:55.938 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1341 21:46:55.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1342 21:46:55.938 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1343 21:46:55.938 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1344 21:46:55.938 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1345 21:46:55.938 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1346 21:46:55.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1347 21:46:55.938 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1348 21:46:55.938 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1349 21:46:55.938 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1350 21:46:55.938 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1351 21:46:55.938 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1352 21:46:55.938 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1353 21:46:55.938 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1354 21:46:55.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1355 21:46:55.938 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1356 21:46:55.938 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1357 21:46:55.938 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1358 21:46:55.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1359 21:46:55.938 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1360 21:46:55.938 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1361 21:46:55.938 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1362 21:46:55.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1363 21:46:55.938 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1364 21:46:55.938 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1365 21:46:55.938 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1366 21:46:55.938 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1367 21:46:55.938 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1368 21:46:55.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1369 21:46:55.938 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1370 21:46:55.938 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1371 21:46:55.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1372 21:46:55.938 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1373 21:46:55.938 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1374 21:46:55.938 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1375 21:46:55.938 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1376 21:46:55.938 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1377 21:46:55.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1378 21:46:55.938 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1379 21:46:55.938 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1380 21:46:55.938 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1381 21:46:55.938 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1382 21:46:55.938 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1383 21:46:55.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1384 21:46:55.938 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1385 21:46:55.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1386 21:46:55.938 0.02827102 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1387 21:46:55.969 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1388 21:46:55.969 0.01302598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1389 21:46:55.969 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1390 21:46:55.984 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1391 21:46:55.984 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1392 21:46:55.984 0.00030143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1393 21:46:55.984 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1394 21:46:55.984 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1395 21:46:55.984 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1396 21:46:55.984 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 1397 21:46:55.984 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1398 21:46:55.984 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1399 21:46:55.984 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1400 21:46:55.984 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1401 21:46:55.984 0.00021096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1402 21:46:55.984 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1403 21:46:55.984 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1404 21:46:55.984 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1405 21:46:55.984 0.00037333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1406 21:46:55.984 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1407 21:46:55.984 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1408 21:46:55.984 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1409 21:46:55.984 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1410 21:46:55.984 0.00029590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1411 21:46:55.984 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1412 21:46:55.984 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1413 21:46:55.984 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1414 21:46:55.984 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1415 21:46:55.984 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1416 21:46:55.984 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1417 21:46:55.984 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1418 21:46:55.984 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1419 21:46:55.984 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1420 21:46:55.984 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 1421 21:46:55.984 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1422 21:46:55.984 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1423 21:46:55.984 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1424 21:46:55.984 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1425 21:46:55.984 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1426 21:46:55.984 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1430 21:46:55.984 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1431 21:46:55.984 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1432 21:46:55.984 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1433 21:46:55.984 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1434 21:46:55.984 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1435 21:46:55.984 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1436 21:46:55.984 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1437 21:46:55.984 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1438 21:46:55.984 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1441 21:46:55.984 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1442 21:46:55.984 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1443 21:46:55.984 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1444 21:46:55.984 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1445 21:46:55.984 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1446 21:46:55.984 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1447 21:46:55.984 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1448 21:46:55.984 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1449 21:46:55.984 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1450 21:46:55.984 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1451 21:46:55.984 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1453 21:46:56.016 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1454 21:46:56.016 0.01395754 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1455 21:46:56.016 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1456 21:46:56.031 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1457 21:46:56.031 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1458 21:46:56.031 0.00044168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1460 21:46:56.031 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1461 21:46:56.031 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1462 21:46:56.031 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1463 21:46:56.031 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1464 21:46:56.031 0.00036938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1465 21:46:56.031 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 1466 21:46:56.031 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1467 21:46:56.031 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1468 21:46:56.031 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1469 21:46:56.031 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1470 21:46:56.031 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1471 21:46:56.031 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1475 21:46:56.031 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1476 21:46:56.031 0.00032751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1477 21:46:56.031 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1478 21:46:56.031 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1479 21:46:56.031 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1480 21:46:56.031 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1481 21:46:56.031 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1483 21:46:56.031 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1484 21:46:56.031 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1485 21:46:56.031 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 1486 21:46:56.031 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1487 21:46:56.031 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1488 21:46:56.031 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1489 21:46:56.031 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1490 21:46:56.031 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1491 21:46:56.031 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1492 21:46:56.031 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1493 21:46:56.031 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1494 21:46:56.031 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1495 21:46:56.031 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1496 21:46:56.031 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1497 21:46:56.031 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1498 21:46:56.031 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1499 21:46:56.031 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1500 21:46:56.031 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1501 21:46:56.031 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1502 21:46:56.031 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1503 21:46:56.031 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1504 21:46:56.031 0.00035872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1505 21:46:56.031 0.00028207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1506 21:46:56.031 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1507 21:46:56.031 0.00036504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1508 21:46:56.031 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1509 21:46:56.031 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1510 21:46:56.031 0.00024889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1511 21:46:56.031 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1512 21:46:56.031 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1513 21:46:56.031 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1514 21:46:56.031 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1515 21:46:56.031 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1516 21:46:56.031 0.02595833 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1517 21:46:56.063 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1518 21:46:56.063 0.01321522 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1519 21:46:56.063 0.00000356 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1520 21:46:56.078 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1521 21:46:56.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1522 21:46:56.078 0.00033659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1523 21:46:56.078 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1524 21:46:56.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1525 21:46:56.078 0.00039664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1526 21:46:56.078 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1527 21:46:56.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1528 21:46:56.078 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 1529 21:46:56.078 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1530 21:46:56.078 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1531 21:46:56.078 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1532 21:46:56.078 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1533 21:46:56.078 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1534 21:46:56.078 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1535 21:46:56.078 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1536 21:46:56.078 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1537 21:46:56.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1538 21:46:56.078 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1539 21:46:56.078 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1540 21:46:56.078 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1541 21:46:56.078 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1542 21:46:56.078 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1543 21:46:56.078 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1544 21:46:56.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1545 21:46:56.078 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1546 21:46:56.078 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1547 21:46:56.078 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1548 21:46:56.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1549 21:46:56.078 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1550 21:46:56.078 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 1551 21:46:56.078 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1552 21:46:56.078 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1553 21:46:56.078 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1554 21:46:56.078 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1555 21:46:56.078 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1556 21:46:56.078 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1557 21:46:56.078 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1558 21:46:56.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1559 21:46:56.078 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1560 21:46:56.078 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1561 21:46:56.078 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1562 21:46:56.078 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1563 21:46:56.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1564 21:46:56.078 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1565 21:46:56.078 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1569 21:46:56.078 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1570 21:46:56.078 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1571 21:46:56.078 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1572 21:46:56.078 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1573 21:46:56.078 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1574 21:46:56.078 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1575 21:46:56.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1576 21:46:56.078 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1577 21:46:56.078 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1578 21:46:56.078 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1579 21:46:56.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1580 21:46:56.078 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1581 21:46:56.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1582 21:46:56.078 0.02672317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1583 21:46:56.110 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1584 21:46:56.110 0.01504791 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1585 21:46:56.110 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1586 21:46:56.125 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1587 21:46:56.125 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1588 21:46:56.125 0.00124247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1589 21:46:56.125 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1590 21:46:56.125 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1591 21:46:56.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1592 21:46:56.125 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1593 21:46:56.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1594 21:46:56.125 0.00052306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1595 21:46:56.125 0.00038756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 1596 21:46:56.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1597 21:46:56.125 0.00039822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1598 21:46:56.125 0.00034054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1599 21:46:56.125 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1600 21:46:56.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1601 21:46:56.125 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1602 21:46:56.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 1603 21:46:56.125 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1604 21:46:56.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1607 21:46:56.125 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1608 21:46:56.125 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1609 21:46:56.125 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1610 21:46:56.125 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1611 21:46:56.125 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1612 21:46:56.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1613 21:46:56.125 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1614 21:46:56.125 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1615 21:46:56.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1616 21:46:56.125 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1617 21:46:56.125 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 1618 21:46:56.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1619 21:46:56.125 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1620 21:46:56.125 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1621 21:46:56.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1622 21:46:56.125 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1623 21:46:56.125 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1624 21:46:56.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1625 21:46:56.125 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1626 21:46:56.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1627 21:46:56.125 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1628 21:46:56.125 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1629 21:46:56.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1630 21:46:56.125 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1631 21:46:56.125 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1632 21:46:56.125 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1633 21:46:56.125 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1634 21:46:56.125 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1635 21:46:56.125 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1636 21:46:56.125 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1637 21:46:56.125 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1638 21:46:56.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1639 21:46:56.125 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1640 21:46:56.125 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1641 21:46:56.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1642 21:46:56.125 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1643 21:46:56.125 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1644 21:46:56.125 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1645 21:46:56.125 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1646 21:46:56.125 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1647 21:46:56.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1648 21:46:56.125 0.02689700 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1649 21:46:56.157 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1650 21:46:56.157 0.01329976 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1651 21:46:56.157 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1652 21:46:56.172 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1653 21:46:56.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1654 21:46:56.172 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1655 21:46:56.172 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1656 21:46:56.172 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1657 21:46:56.172 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1658 21:46:56.172 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1659 21:46:56.172 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1660 21:46:56.172 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 1661 21:46:56.172 0.00020425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1662 21:46:56.172 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1663 21:46:56.172 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1664 21:46:56.172 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1665 21:46:56.172 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1666 21:46:56.172 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1667 21:46:56.172 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1668 21:46:56.172 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1669 21:46:56.172 0.00029748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1670 21:46:56.172 0.00031170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1671 21:46:56.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1672 21:46:56.172 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1673 21:46:56.172 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1674 21:46:56.172 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1675 21:46:56.172 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1676 21:46:56.172 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1677 21:46:56.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1678 21:46:56.172 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1679 21:46:56.172 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 1680 21:46:56.172 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1681 21:46:56.172 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1682 21:46:56.172 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1683 21:46:56.172 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1684 21:46:56.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1685 21:46:56.172 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1686 21:46:56.172 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1687 21:46:56.172 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1688 21:46:56.172 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1689 21:46:56.172 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1690 21:46:56.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1691 21:46:56.172 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1692 21:46:56.172 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1693 21:46:56.172 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1694 21:46:56.172 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1695 21:46:56.172 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1696 21:46:56.172 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1697 21:46:56.172 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1698 21:46:56.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1699 21:46:56.172 0.00029037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1700 21:46:56.172 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1701 21:46:56.172 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1702 21:46:56.172 0.00024770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1703 21:46:56.172 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1704 21:46:56.172 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1705 21:46:56.172 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1706 21:46:56.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1707 21:46:56.172 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1708 21:46:56.172 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1709 21:46:56.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1710 21:46:56.172 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1711 21:46:56.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1712 21:46:56.172 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1713 21:46:56.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1714 21:46:56.172 0.02692386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1715 21:46:56.203 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1716 21:46:56.203 0.01356959 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1717 21:46:56.203 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1718 21:46:56.219 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1719 21:46:56.219 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1720 21:46:56.219 0.00054677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1721 21:46:56.219 0.00035714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1722 21:46:56.219 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1723 21:46:56.219 0.00051951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1724 21:46:56.219 0.00044681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1725 21:46:56.219 0.00141077 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1726 21:46:56.219 0.00050173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1727 21:46:56.219 0.00039664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 1728 21:46:56.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1729 21:46:56.219 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1730 21:46:56.219 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1731 21:46:56.219 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1732 21:46:56.219 0.00032277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1733 21:46:56.219 0.00026864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1734 21:46:56.219 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 1735 21:46:56.219 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1736 21:46:56.219 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1737 21:46:56.219 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 1738 21:46:56.219 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1739 21:46:56.219 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1740 21:46:56.219 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1741 21:46:56.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1742 21:46:56.219 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1743 21:46:56.219 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1744 21:46:56.219 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1746 21:46:56.219 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1747 21:46:56.219 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1748 21:46:56.219 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 1749 21:46:56.219 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1750 21:46:56.219 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1751 21:46:56.219 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 1752 21:46:56.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1753 21:46:56.219 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1754 21:46:56.219 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1755 21:46:56.219 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1756 21:46:56.219 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1757 21:46:56.219 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1758 21:46:56.219 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1759 21:46:56.219 0.00030064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1760 21:46:56.219 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1761 21:46:56.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1762 21:46:56.219 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1763 21:46:56.219 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1764 21:46:56.219 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1765 21:46:56.219 0.00029235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1766 21:46:56.219 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1767 21:46:56.219 0.00033580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1768 21:46:56.219 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1769 21:46:56.219 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1770 21:46:56.219 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1771 21:46:56.219 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1772 21:46:56.219 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1773 21:46:56.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1774 21:46:56.219 0.00028602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1775 21:46:56.219 0.00027299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1776 21:46:56.219 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1777 21:46:56.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1778 21:46:56.219 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1779 21:46:56.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1780 21:46:56.219 0.02368594 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1781 21:46:56.251 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1782 21:46:56.251 0.01458687 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1783 21:46:56.251 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1784 21:46:56.266 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1785 21:46:56.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1786 21:46:56.266 0.00052741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1787 21:46:56.266 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1788 21:46:56.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1789 21:46:56.266 0.00025995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1790 21:46:56.266 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1791 21:46:56.266 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 1792 21:46:56.266 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1793 21:46:56.266 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1794 21:46:56.266 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1795 21:46:56.266 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1796 21:46:56.266 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1797 21:46:56.266 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1798 21:46:56.266 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1799 21:46:56.266 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1800 21:46:56.266 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1801 21:46:56.266 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1802 21:46:56.266 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1803 21:46:56.266 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1804 21:46:56.266 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1805 21:46:56.266 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1806 21:46:56.266 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1807 21:46:56.266 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1808 21:46:56.266 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1809 21:46:56.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1810 21:46:56.266 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 1811 21:46:56.266 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1812 21:46:56.266 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 1813 21:46:56.266 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1814 21:46:56.266 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1815 21:46:56.266 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1816 21:46:56.266 0.00037333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1817 21:46:56.266 0.00045630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1818 21:46:56.266 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1819 21:46:56.266 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1820 21:46:56.266 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1821 21:46:56.266 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1822 21:46:56.266 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1823 21:46:56.266 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1824 21:46:56.266 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1825 21:46:56.266 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1826 21:46:56.266 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1827 21:46:56.266 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1828 21:46:56.266 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1829 21:46:56.266 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1830 21:46:56.266 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1831 21:46:56.266 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1832 21:46:56.266 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1833 21:46:56.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1834 21:46:56.266 0.00026351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1835 21:46:56.266 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1836 21:46:56.266 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1837 21:46:56.266 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1838 21:46:56.266 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1839 21:46:56.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1840 21:46:56.266 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1841 21:46:56.266 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1842 21:46:56.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1843 21:46:56.266 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1844 21:46:56.266 0.00025995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1845 21:46:56.266 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1846 21:46:56.266 0.02711428 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1847 21:46:56.297 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1848 21:46:56.297 0.01308050 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1849 21:46:56.297 0.00001699 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1850 21:46:56.313 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1851 21:46:56.313 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1852 21:46:56.313 0.00029353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1853 21:46:56.313 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1854 21:46:56.313 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1855 21:46:56.313 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1856 21:46:56.313 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1857 21:46:56.313 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 1858 21:46:56.313 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1859 21:46:56.313 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1860 21:46:56.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1861 21:46:56.313 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1862 21:46:56.313 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1863 21:46:56.313 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1864 21:46:56.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1865 21:46:56.313 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1866 21:46:56.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1867 21:46:56.313 0.00035358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1868 21:46:56.313 0.00029353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1869 21:46:56.313 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 1870 21:46:56.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1871 21:46:56.313 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1872 21:46:56.313 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1873 21:46:56.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1874 21:46:56.313 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1875 21:46:56.313 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1876 21:46:56.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1877 21:46:56.313 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1878 21:46:56.313 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1879 21:46:56.313 0.00036543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1880 21:46:56.313 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 1881 21:46:56.313 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1882 21:46:56.313 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1883 21:46:56.313 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1884 21:46:56.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1885 21:46:56.313 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1886 21:46:56.313 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1887 21:46:56.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1888 21:46:56.313 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1889 21:46:56.313 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1890 21:46:56.313 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1891 21:46:56.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1892 21:46:56.313 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1893 21:46:56.313 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1894 21:46:56.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1895 21:46:56.313 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1896 21:46:56.313 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1897 21:46:56.313 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1898 21:46:56.313 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1899 21:46:56.313 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1900 21:46:56.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1901 21:46:56.313 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1902 21:46:56.313 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1903 21:46:56.313 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1904 21:46:56.313 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1905 21:46:56.313 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1906 21:46:56.313 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1907 21:46:56.313 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1908 21:46:56.313 0.00024257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1909 21:46:56.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1910 21:46:56.313 0.02569957 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1911 21:46:56.344 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1912 21:46:56.344 0.02898846 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1913 21:46:56.344 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1914 21:46:56.375 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1915 21:46:56.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1916 21:46:56.375 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1917 21:46:56.375 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 58 1921 21:46:56.375 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1922 21:46:56.375 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 1923 21:46:56.375 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1924 21:46:56.375 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1925 21:46:56.375 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1926 21:46:56.375 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1927 21:46:56.375 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1928 21:46:56.375 0.00032079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1929 21:46:56.375 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1930 21:46:56.375 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1931 21:46:56.375 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1932 21:46:56.375 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1933 21:46:56.375 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 1934 21:46:56.375 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1935 21:46:56.375 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1936 21:46:56.375 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1937 21:46:56.375 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1938 21:46:56.375 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1939 21:46:56.375 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 1940 21:46:56.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1941 21:46:56.375 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1942 21:46:56.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1943 21:46:56.375 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1944 21:46:56.375 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 1945 21:46:56.375 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1946 21:46:56.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1947 21:46:56.375 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1948 21:46:56.375 0.00009047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1949 21:46:56.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1950 21:46:56.375 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1951 21:46:56.375 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1952 21:46:56.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1953 21:46:56.375 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1954 21:46:56.375 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1955 21:46:56.375 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1956 21:46:56.375 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1957 21:46:56.375 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1958 21:46:56.375 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1959 21:46:56.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1960 21:46:56.375 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1961 21:46:56.375 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1962 21:46:56.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1963 21:46:56.375 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1964 21:46:56.375 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1965 21:46:56.375 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1966 21:46:56.375 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1967 21:46:56.375 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1968 21:46:56.375 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1969 21:46:56.375 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1970 21:46:56.375 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1971 21:46:56.375 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1972 21:46:56.375 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1973 21:46:56.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1974 21:46:56.375 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1975 21:46:56.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1976 21:46:56.375 0.02784910 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1977 21:46:56.406 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1978 21:46:56.406 0.01352534 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1979 21:46:56.406 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1980 21:46:56.422 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1981 21:46:56.422 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1982 21:46:56.422 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1983 21:46:56.422 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1984 21:46:56.422 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1985 21:46:56.422 0.00110499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1986 21:46:56.422 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1987 21:46:56.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1988 21:46:56.422 0.00030617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1989 21:46:56.422 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 1990 21:46:56.422 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1991 21:46:56.422 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1992 21:46:56.422 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1993 21:46:56.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1994 21:46:56.422 0.00029906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1995 21:46:56.422 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1996 21:46:56.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1997 21:46:56.422 0.00031565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1999 21:46:56.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2000 21:46:56.422 0.00031684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2001 21:46:56.422 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 2002 21:46:56.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2003 21:46:56.422 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2004 21:46:56.422 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2005 21:46:56.422 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2006 21:46:56.422 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2007 21:46:56.422 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2008 21:46:56.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2009 21:46:56.422 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2010 21:46:56.422 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 2011 21:46:56.422 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2012 21:46:56.422 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 2013 21:46:56.422 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2014 21:46:56.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2015 21:46:56.422 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2016 21:46:56.422 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2017 21:46:56.422 0.00026153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2018 21:46:56.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2019 21:46:56.422 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2020 21:46:56.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2021 21:46:56.422 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2022 21:46:56.422 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2023 21:46:56.422 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2024 21:46:56.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2025 21:46:56.422 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2026 21:46:56.422 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 2027 21:46:56.422 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2028 21:46:56.422 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2032 21:46:56.422 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2033 21:46:56.422 0.00030538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2034 21:46:56.422 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2035 21:46:56.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2036 21:46:56.422 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2037 21:46:56.422 0.00026469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2038 21:46:56.422 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2039 21:46:56.422 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2040 21:46:56.422 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2041 21:46:56.422 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2042 21:46:56.422 0.02592080 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2043 21:46:56.453 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2044 21:46:56.453 0.01361462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2045 21:46:56.453 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2046 21:46:56.469 0.00033027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2047 21:46:56.469 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2048 21:46:56.469 0.00041521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2049 21:46:56.469 0.00032079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2050 21:46:56.469 0.00027694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2051 21:46:56.469 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2052 21:46:56.469 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2053 21:46:56.469 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2054 21:46:56.469 0.00029630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 2055 21:46:56.469 0.00034133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2056 21:46:56.469 0.00032316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2057 21:46:56.469 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2058 21:46:56.469 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2059 21:46:56.469 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2060 21:46:56.469 0.00032632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2061 21:46:56.469 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2062 21:46:56.469 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2063 21:46:56.469 0.00030222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2064 21:46:56.469 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2065 21:46:56.469 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2066 21:46:56.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2067 21:46:56.469 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2068 21:46:56.469 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2069 21:46:56.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2070 21:46:56.469 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2071 21:46:56.469 0.00031289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2072 21:46:56.469 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2073 21:46:56.469 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2074 21:46:56.469 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 2075 21:46:56.469 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2076 21:46:56.469 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2077 21:46:56.469 0.00029472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2078 21:46:56.469 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2079 21:46:56.469 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2080 21:46:56.469 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2081 21:46:56.469 0.00027496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2082 21:46:56.469 0.00028247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2083 21:46:56.469 0.00025521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2084 21:46:56.469 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2085 21:46:56.469 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2086 21:46:56.469 0.00028879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2087 21:46:56.469 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2088 21:46:56.469 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2089 21:46:56.469 0.00035200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2090 21:46:56.469 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2091 21:46:56.469 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2094 21:46:56.469 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2095 21:46:56.469 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2096 21:46:56.469 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2097 21:46:56.469 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2098 21:46:56.469 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2099 21:46:56.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2100 21:46:56.469 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2101 21:46:56.469 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2102 21:46:56.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2103 21:46:56.469 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2104 21:46:56.469 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2105 21:46:56.469 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2106 21:46:56.469 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2107 21:46:56.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2108 21:46:56.469 0.02600179 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2109 21:46:56.500 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2110 21:46:56.500 0.01332030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2111 21:46:56.500 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2112 21:46:56.516 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2113 21:46:56.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2114 21:46:56.516 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2115 21:46:56.516 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2116 21:46:56.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2117 21:46:56.516 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2118 21:46:56.516 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2119 21:46:56.516 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2120 21:46:56.516 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2121 21:46:56.516 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 2122 21:46:56.516 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2123 21:46:56.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2124 21:46:56.516 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2125 21:46:56.516 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2126 21:46:56.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2127 21:46:56.516 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2128 21:46:56.516 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2129 21:46:56.516 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2130 21:46:56.516 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2131 21:46:56.516 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2132 21:46:56.516 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2133 21:46:56.516 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2134 21:46:56.516 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 43 2135 21:46:56.516 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2136 21:46:56.516 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2138 21:46:56.516 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2139 21:46:56.516 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2140 21:46:56.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2141 21:46:56.516 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2142 21:46:56.516 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2143 21:46:56.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2144 21:46:56.516 0.00021294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2145 21:46:56.516 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2146 21:46:56.516 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2147 21:46:56.516 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2148 21:46:56.516 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2149 21:46:56.516 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2150 21:46:56.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2151 21:46:56.516 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2152 21:46:56.516 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2153 21:46:56.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2154 21:46:56.516 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2155 21:46:56.516 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2156 21:46:56.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2157 21:46:56.516 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2158 21:46:56.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2159 21:46:56.516 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 2160 21:46:56.516 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2163 21:46:56.516 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2164 21:46:56.516 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2165 21:46:56.516 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2166 21:46:56.516 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2167 21:46:56.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2168 21:46:56.516 0.00036030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2169 21:46:56.516 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2170 21:46:56.516 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2171 21:46:56.516 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2172 21:46:56.516 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2173 21:46:56.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2174 21:46:56.516 0.02728811 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2175 21:46:56.547 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2176 21:46:56.547 0.01380504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2177 21:46:56.547 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2178 21:46:56.563 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2179 21:46:56.563 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2180 21:46:56.563 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2181 21:46:56.563 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2182 21:46:56.563 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2183 21:46:56.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2184 21:46:56.563 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2185 21:46:56.563 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 2186 21:46:56.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2187 21:46:56.563 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2188 21:46:56.563 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2189 21:46:56.563 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2190 21:46:56.563 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2191 21:46:56.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2192 21:46:56.563 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2193 21:46:56.563 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2194 21:46:56.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2195 21:46:56.563 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2196 21:46:56.563 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2197 21:46:56.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2198 21:46:56.563 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2199 21:46:56.563 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2200 21:46:56.563 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2201 21:46:56.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2202 21:46:56.563 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2203 21:46:56.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2204 21:46:56.563 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2205 21:46:56.563 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2206 21:46:56.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2207 21:46:56.563 0.00033185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2208 21:46:56.563 0.00029748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2209 21:46:56.563 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2210 21:46:56.563 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2211 21:46:56.563 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2212 21:46:56.563 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2213 21:46:56.563 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2214 21:46:56.563 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2215 21:46:56.563 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2216 21:46:56.563 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2217 21:46:56.563 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2218 21:46:56.563 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2219 21:46:56.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2220 21:46:56.563 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2221 21:46:56.563 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 2224 21:46:56.563 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2225 21:46:56.563 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2226 21:46:56.563 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2227 21:46:56.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2228 21:46:56.563 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2229 21:46:56.563 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2230 21:46:56.563 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2233 21:46:56.563 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2234 21:46:56.563 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2235 21:46:56.563 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2236 21:46:56.563 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2237 21:46:56.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2238 21:46:56.563 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2239 21:46:56.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2240 21:46:56.563 0.02864633 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2241 21:46:56.594 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2242 21:46:56.594 0.01297857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2243 21:46:56.594 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2244 21:46:56.610 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2245 21:46:56.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2246 21:46:56.610 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2247 21:46:56.610 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2248 21:46:56.610 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2249 21:46:56.610 0.00030933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2250 21:46:56.610 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2251 21:46:56.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2252 21:46:56.610 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2253 21:46:56.610 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 2254 21:46:56.610 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2255 21:46:56.610 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2256 21:46:56.610 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2257 21:46:56.610 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2258 21:46:56.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2259 21:46:56.610 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2260 21:46:56.610 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2261 21:46:56.610 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 2262 21:46:56.610 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2263 21:46:56.610 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2264 21:46:56.610 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2265 21:46:56.610 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2266 21:46:56.610 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2267 21:46:56.610 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2268 21:46:56.610 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2269 21:46:56.610 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2270 21:46:56.610 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2271 21:46:56.610 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2272 21:46:56.610 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 2273 21:46:56.610 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2274 21:46:56.610 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2275 21:46:56.610 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2276 21:46:56.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2277 21:46:56.610 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2278 21:46:56.610 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2279 21:46:56.610 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2280 21:46:56.610 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2281 21:46:56.610 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2282 21:46:56.610 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2283 21:46:56.610 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2284 21:46:56.610 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2285 21:46:56.610 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2286 21:46:56.610 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2287 21:46:56.610 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2288 21:46:56.610 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2289 21:46:56.610 0.00024138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2290 21:46:56.610 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2291 21:46:56.610 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2292 21:46:56.610 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2293 21:46:56.610 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2294 21:46:56.610 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2295 21:46:56.610 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2296 21:46:56.610 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2297 21:46:56.610 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2298 21:46:56.610 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2299 21:46:56.610 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2300 21:46:56.610 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2301 21:46:56.610 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2302 21:46:56.610 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2303 21:46:56.610 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2304 21:46:56.610 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2305 21:46:56.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2306 21:46:56.610 0.02803517 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2307 21:46:56.641 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2308 21:46:56.641 0.01328791 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2309 21:46:56.641 0.00001422 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2310 21:46:56.657 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2311 21:46:56.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2312 21:46:56.657 0.00038598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2313 21:46:56.657 0.00026153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2314 21:46:56.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2315 21:46:56.657 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2316 21:46:56.657 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2317 21:46:56.657 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 2318 21:46:56.657 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2319 21:46:56.657 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2320 21:46:56.657 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2321 21:46:56.657 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2322 21:46:56.657 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2323 21:46:56.657 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2324 21:46:56.657 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2325 21:46:56.657 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2326 21:46:56.657 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2327 21:46:56.657 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2328 21:46:56.657 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2329 21:46:56.657 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2330 21:46:56.657 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2331 21:46:56.657 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2332 21:46:56.657 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2333 21:46:56.657 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2334 21:46:56.657 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2335 21:46:56.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2336 21:46:56.657 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2337 21:46:56.657 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2338 21:46:56.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2339 21:46:56.657 0.00009047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2340 21:46:56.657 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2341 21:46:56.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2342 21:46:56.657 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2343 21:46:56.657 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2344 21:46:56.657 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2345 21:46:56.657 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2346 21:46:56.657 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2347 21:46:56.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2348 21:46:56.657 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2349 21:46:56.657 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2350 21:46:56.657 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2351 21:46:56.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2352 21:46:56.657 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2353 21:46:56.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2354 21:46:56.657 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2355 21:46:56.657 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2356 21:46:56.657 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2357 21:46:56.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2358 21:46:56.657 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2359 21:46:56.657 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2360 21:46:56.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2361 21:46:56.657 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2362 21:46:56.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2363 21:46:56.657 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2364 21:46:56.657 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2365 21:46:56.657 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2366 21:46:56.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2367 21:46:56.657 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2368 21:46:56.657 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2369 21:46:56.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2370 21:46:56.657 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2371 21:46:56.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2372 21:46:56.657 0.02803794 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2373 21:46:56.688 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2374 21:46:56.688 0.01364386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2375 21:46:56.688 0.00002686 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2376 21:46:56.703 0.00046499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2377 21:46:56.703 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2378 21:46:56.703 0.00037570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2379 21:46:56.703 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2380 21:46:56.703 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2381 21:46:56.703 0.00032356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2382 21:46:56.703 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2383 21:46:56.703 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2384 21:46:56.703 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2385 21:46:56.703 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2386 21:46:56.703 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2387 21:46:56.703 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2389 21:46:56.703 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2390 21:46:56.703 0.00027931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2391 21:46:56.703 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2392 21:46:56.703 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2393 21:46:56.703 0.00034370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2394 21:46:56.703 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2395 21:46:56.703 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2396 21:46:56.703 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2397 21:46:56.703 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2398 21:46:56.703 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2399 21:46:56.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2400 21:46:56.703 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2401 21:46:56.703 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2402 21:46:56.703 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2403 21:46:56.703 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2404 21:46:56.703 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2405 21:46:56.703 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2406 21:46:56.703 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2407 21:46:56.703 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2408 21:46:56.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2409 21:46:56.703 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2410 21:46:56.703 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2411 21:46:56.703 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2412 21:46:56.703 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2413 21:46:56.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2414 21:46:56.703 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2415 21:46:56.703 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2416 21:46:56.703 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2417 21:46:56.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2418 21:46:56.703 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2419 21:46:56.703 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2420 21:46:56.703 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2421 21:46:56.703 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2422 21:46:56.703 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2423 21:46:56.703 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2424 21:46:56.703 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2425 21:46:56.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2426 21:46:56.703 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2427 21:46:56.703 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2428 21:46:56.703 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2429 21:46:56.703 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2430 21:46:56.703 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2431 21:46:56.703 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2432 21:46:56.703 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2433 21:46:56.703 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2434 21:46:56.703 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2435 21:46:56.703 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2436 21:46:56.703 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2437 21:46:56.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2438 21:46:56.703 0.02667655 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2439 21:46:56.734 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2440 21:46:56.734 0.01283556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2441 21:46:56.734 0.00000514 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2442 21:46:56.750 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2443 21:46:56.750 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2444 21:46:56.750 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2445 21:46:56.750 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2448 21:46:56.750 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2449 21:46:56.750 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2450 21:46:56.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2451 21:46:56.750 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2452 21:46:56.750 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2453 21:46:56.750 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2454 21:46:56.750 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2455 21:46:56.750 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2456 21:46:56.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2457 21:46:56.750 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2459 21:46:56.750 0.00034528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2460 21:46:56.750 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2461 21:46:56.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2462 21:46:56.750 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2463 21:46:56.750 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2464 21:46:56.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2465 21:46:56.750 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2466 21:46:56.750 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2467 21:46:56.750 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2468 21:46:56.750 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2469 21:46:56.750 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2470 21:46:56.750 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 2471 21:46:56.750 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2472 21:46:56.750 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2473 21:46:56.750 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2474 21:46:56.750 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2475 21:46:56.750 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2477 21:46:56.750 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2478 21:46:56.750 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2479 21:46:56.750 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2480 21:46:56.750 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2481 21:46:56.750 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2482 21:46:56.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2483 21:46:56.750 0.00024217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2484 21:46:56.750 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2485 21:46:56.750 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2486 21:46:56.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2487 21:46:56.750 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2488 21:46:56.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2489 21:46:56.750 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2490 21:46:56.750 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2491 21:46:56.750 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2492 21:46:56.750 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2493 21:46:56.750 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2494 21:46:56.750 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2495 21:46:56.750 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2496 21:46:56.750 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2497 21:46:56.750 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2498 21:46:56.750 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2499 21:46:56.750 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2500 21:46:56.750 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2501 21:46:56.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2502 21:46:56.750 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2503 21:46:56.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2504 21:46:56.750 0.02765828 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2505 21:46:56.781 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2506 21:46:56.781 0.01329225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2507 21:46:56.781 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2508 21:46:56.797 0.00030657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2509 21:46:56.797 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2510 21:46:56.797 0.00036227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2511 21:46:56.797 0.00032751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2512 21:46:56.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2513 21:46:56.797 0.00035595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2514 21:46:56.797 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2515 21:46:56.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2516 21:46:56.797 0.00047289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2517 21:46:56.797 0.00036306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2518 21:46:56.797 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2519 21:46:56.797 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2520 21:46:56.797 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2521 21:46:56.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2522 21:46:56.797 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2523 21:46:56.797 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2524 21:46:56.797 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 2525 21:46:56.797 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2526 21:46:56.797 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2527 21:46:56.797 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2528 21:46:56.797 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2529 21:46:56.797 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2530 21:46:56.797 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 43 2531 21:46:56.797 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2532 21:46:56.797 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2535 21:46:56.797 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2536 21:46:56.797 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 2537 21:46:56.797 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2538 21:46:56.797 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2539 21:46:56.797 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 2540 21:46:56.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2541 21:46:56.797 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2542 21:46:56.797 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2543 21:46:56.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2544 21:46:56.797 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2545 21:46:56.797 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2546 21:46:56.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2547 21:46:56.797 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2548 21:46:56.797 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2549 21:46:56.797 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2550 21:46:56.797 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2551 21:46:56.797 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2552 21:46:56.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2553 21:46:56.797 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2554 21:46:56.797 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2555 21:46:56.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2556 21:46:56.797 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2557 21:46:56.797 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2558 21:46:56.797 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2559 21:46:56.797 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2560 21:46:56.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2561 21:46:56.797 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2562 21:46:56.797 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2563 21:46:56.797 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2564 21:46:56.797 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2565 21:46:56.797 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2566 21:46:56.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2567 21:46:56.797 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2568 21:46:56.797 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2569 21:46:56.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2570 21:46:56.797 0.02626213 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2571 21:46:56.828 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2572 21:46:56.828 0.01444188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2573 21:46:56.828 0.00001541 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2574 21:46:56.844 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2575 21:46:56.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2576 21:46:56.844 0.00046025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2577 21:46:56.844 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2578 21:46:56.844 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 2579 21:46:56.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2580 21:46:56.844 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2581 21:46:56.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2582 21:46:56.844 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2583 21:46:56.844 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2584 21:46:56.844 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2585 21:46:56.844 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2586 21:46:56.844 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2587 21:46:56.844 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2588 21:46:56.844 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2589 21:46:56.844 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2590 21:46:56.844 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2591 21:46:56.844 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2592 21:46:56.844 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2593 21:46:56.844 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2594 21:46:56.844 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2595 21:46:56.844 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2596 21:46:56.844 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2597 21:46:56.844 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2598 21:46:56.844 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2599 21:46:56.844 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2600 21:46:56.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2601 21:46:56.844 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2602 21:46:56.844 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 2603 21:46:56.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2604 21:46:56.844 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2605 21:46:56.844 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2606 21:46:56.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2607 21:46:56.844 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2608 21:46:56.844 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2609 21:46:56.844 0.00027496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2610 21:46:56.844 0.00029235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2611 21:46:56.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2612 21:46:56.844 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2613 21:46:56.844 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2614 21:46:56.844 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2615 21:46:56.844 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2616 21:46:56.844 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2617 21:46:56.844 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2618 21:46:56.844 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2619 21:46:56.844 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2620 21:46:56.844 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2621 21:46:56.844 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2622 21:46:56.844 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2623 21:46:56.844 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2624 21:46:56.844 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2625 21:46:56.844 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2626 21:46:56.844 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2627 21:46:56.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2628 21:46:56.844 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2629 21:46:56.844 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2630 21:46:56.844 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2631 21:46:56.844 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2632 21:46:56.844 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2633 21:46:56.844 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2634 21:46:56.844 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2635 21:46:56.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2636 21:46:56.844 0.02755399 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2637 21:46:56.875 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2638 21:46:56.875 0.01515931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2639 21:46:56.875 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2640 21:46:56.893 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2641 21:46:56.893 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2642 21:46:56.893 0.00102005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2643 21:46:56.893 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2644 21:46:56.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2645 21:46:56.893 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2646 21:46:56.893 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2647 21:46:56.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2648 21:46:56.893 0.00036741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2649 21:46:56.893 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2650 21:46:56.893 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2651 21:46:56.893 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2652 21:46:56.893 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2653 21:46:56.893 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2654 21:46:56.893 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2655 21:46:56.893 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2656 21:46:56.893 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2657 21:46:56.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2658 21:46:56.893 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2659 21:46:56.893 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2660 21:46:56.893 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2661 21:46:56.893 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2662 21:46:56.893 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2663 21:46:56.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2664 21:46:56.893 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2665 21:46:56.893 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2666 21:46:56.893 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2667 21:46:56.893 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2668 21:46:56.893 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2669 21:46:56.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2670 21:46:56.893 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2671 21:46:56.893 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2672 21:46:56.893 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2673 21:46:56.893 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2674 21:46:56.893 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2675 21:46:56.893 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2676 21:46:56.893 0.00007941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2677 21:46:56.893 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2678 21:46:56.893 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 2679 21:46:56.893 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2683 21:46:56.893 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2684 21:46:56.893 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2685 21:46:56.893 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2686 21:46:56.893 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2687 21:46:56.893 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2688 21:46:56.893 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2689 21:46:56.893 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2690 21:46:56.893 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2691 21:46:56.893 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2692 21:46:56.893 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2693 21:46:56.893 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2694 21:46:56.893 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2695 21:46:56.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2696 21:46:56.893 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2697 21:46:56.893 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2698 21:46:56.893 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2699 21:46:56.893 0.00036346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2700 21:46:56.893 0.00037570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2701 21:46:56.893 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2702 21:46:56.893 0.02675675 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2703 21:46:56.922 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2704 21:46:56.922 0.01210391 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2705 21:46:56.922 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2706 21:46:56.938 0.00033462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2707 21:46:56.938 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2708 21:46:56.938 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2709 21:46:56.938 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2710 21:46:56.938 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 2711 21:46:56.938 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2712 21:46:56.938 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2713 21:46:56.938 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2714 21:46:56.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2715 21:46:56.938 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2716 21:46:56.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2717 21:46:56.938 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2718 21:46:56.938 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2719 21:46:56.938 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2720 21:46:56.938 0.00030815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2721 21:46:56.938 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2722 21:46:56.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2723 21:46:56.938 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2725 21:46:56.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2726 21:46:56.938 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2727 21:46:56.938 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2728 21:46:56.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2729 21:46:56.938 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2730 21:46:56.938 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2731 21:46:56.938 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2732 21:46:56.938 0.00027496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2733 21:46:56.938 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2734 21:46:56.938 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 2735 21:46:56.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2736 21:46:56.938 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2737 21:46:56.938 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2738 21:46:56.938 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2739 21:46:56.938 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2740 21:46:56.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 2741 21:46:56.938 0.00018726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2742 21:46:56.938 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2743 21:46:56.938 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2744 21:46:56.938 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2745 21:46:56.938 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2746 21:46:56.938 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2747 21:46:56.938 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2748 21:46:56.938 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2749 21:46:56.938 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2750 21:46:56.938 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2751 21:46:56.938 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2752 21:46:56.938 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2753 21:46:56.938 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2754 21:46:56.938 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2755 21:46:56.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2756 21:46:56.938 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2757 21:46:56.938 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2758 21:46:56.938 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2759 21:46:56.938 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2760 21:46:56.938 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2761 21:46:56.938 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2762 21:46:56.938 0.00030262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2763 21:46:56.938 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2764 21:46:56.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 2765 21:46:56.938 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2766 21:46:56.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2769 21:46:56.969 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2770 21:46:56.969 0.01390776 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2771 21:46:56.969 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2772 21:46:56.985 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2773 21:46:56.985 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2774 21:46:56.985 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2775 21:46:56.985 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2776 21:46:56.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2777 21:46:56.985 0.00127921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2778 21:46:56.985 0.00035793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2779 21:46:56.985 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 2780 21:46:56.985 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2781 21:46:56.985 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2782 21:46:56.985 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2783 21:46:56.985 0.00032356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2784 21:46:56.985 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2785 21:46:56.985 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2786 21:46:56.985 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2787 21:46:56.985 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2788 21:46:56.985 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 2789 21:46:56.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2790 21:46:56.985 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2791 21:46:56.985 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2792 21:46:56.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2793 21:46:56.985 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2794 21:46:56.985 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2795 21:46:56.985 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2796 21:46:56.985 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2797 21:46:56.985 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2798 21:46:56.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2799 21:46:56.985 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2800 21:46:56.985 0.00032198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 2801 21:46:56.985 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2802 21:46:56.985 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2803 21:46:56.985 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2804 21:46:56.985 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2805 21:46:56.985 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2806 21:46:56.985 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2807 21:46:56.985 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2808 21:46:56.985 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2809 21:46:56.985 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2810 21:46:56.985 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2811 21:46:56.985 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2812 21:46:56.985 0.00008810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2813 21:46:56.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2814 21:46:56.985 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2815 21:46:56.985 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2816 21:46:56.985 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2817 21:46:56.985 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2818 21:46:56.985 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2819 21:46:56.985 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2820 21:46:56.985 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2821 21:46:56.985 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2822 21:46:56.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2823 21:46:56.985 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2824 21:46:56.985 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2825 21:46:56.985 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2826 21:46:56.985 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2827 21:46:56.985 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2828 21:46:56.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2829 21:46:56.985 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2830 21:46:56.985 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2831 21:46:56.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2832 21:46:56.985 0.02631547 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2833 21:46:57.016 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2834 21:46:57.016 0.01355852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2835 21:46:57.016 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2836 21:46:57.032 0.00030617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2837 21:46:57.032 0.00032909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2838 21:46:57.032 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2839 21:46:57.032 0.00050686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2840 21:46:57.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2841 21:46:57.032 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 2842 21:46:57.032 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2843 21:46:57.032 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 2844 21:46:57.032 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2845 21:46:57.032 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2846 21:46:57.032 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2847 21:46:57.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2848 21:46:57.032 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2849 21:46:57.032 0.00037649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2850 21:46:57.032 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2851 21:46:57.032 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2852 21:46:57.032 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2855 21:46:57.032 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2856 21:46:57.032 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2857 21:46:57.032 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2858 21:46:57.032 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2859 21:46:57.032 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2860 21:46:57.032 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2861 21:46:57.032 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 2862 21:46:57.032 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2863 21:46:57.032 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2864 21:46:57.032 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 2865 21:46:57.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2866 21:46:57.032 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2867 21:46:57.032 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2868 21:46:57.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2869 21:46:57.032 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2872 21:46:57.032 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2873 21:46:57.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2874 21:46:57.032 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2875 21:46:57.032 0.00020425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2876 21:46:57.032 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2877 21:46:57.032 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2878 21:46:57.032 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2879 21:46:57.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2880 21:46:57.032 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2881 21:46:57.032 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2882 21:46:57.032 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2883 21:46:57.032 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2884 21:46:57.032 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2885 21:46:57.032 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2886 21:46:57.032 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2887 21:46:57.032 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2888 21:46:57.032 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2889 21:46:57.032 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2890 21:46:57.032 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2891 21:46:57.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2892 21:46:57.032 0.00032079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2893 21:46:57.032 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2894 21:46:57.032 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2895 21:46:57.032 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2896 21:46:57.032 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2897 21:46:57.032 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2898 21:46:57.032 0.02842905 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2899 21:46:57.063 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2900 21:46:57.063 0.01165749 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2901 21:46:57.063 0.00002607 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2902 21:46:57.078 0.00031961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2903 21:46:57.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2904 21:46:57.078 0.00028563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2905 21:46:57.078 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2906 21:46:57.078 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2907 21:46:57.078 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2908 21:46:57.078 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2909 21:46:57.078 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2910 21:46:57.078 0.00033936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 2911 21:46:57.078 0.00030854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2912 21:46:57.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2913 21:46:57.078 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2914 21:46:57.078 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2915 21:46:57.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2916 21:46:57.078 0.00030499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2917 21:46:57.078 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2918 21:46:57.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2919 21:46:57.078 0.00029432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2920 21:46:57.078 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2921 21:46:57.078 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2922 21:46:57.078 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2923 21:46:57.078 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2924 21:46:57.078 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2925 21:46:57.078 0.00039388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2926 21:46:57.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2927 21:46:57.078 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2928 21:46:57.078 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2929 21:46:57.078 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2930 21:46:57.078 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2931 21:46:57.078 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 2932 21:46:57.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2933 21:46:57.078 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2934 21:46:57.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2935 21:46:57.078 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2936 21:46:57.078 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2937 21:46:57.078 0.00024138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 2938 21:46:57.078 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2939 21:46:57.078 0.00025165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2940 21:46:57.078 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2941 21:46:57.078 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2942 21:46:57.078 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2943 21:46:57.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2944 21:46:57.078 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2945 21:46:57.078 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2946 21:46:57.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2947 21:46:57.078 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2948 21:46:57.078 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2949 21:46:57.078 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2950 21:46:57.078 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2951 21:46:57.078 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2952 21:46:57.078 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 2953 21:46:57.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2954 21:46:57.078 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2955 21:46:57.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2956 21:46:57.078 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2957 21:46:57.078 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 2958 21:46:57.078 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2959 21:46:57.078 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2960 21:46:57.078 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2961 21:46:57.078 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2962 21:46:57.078 0.02520060 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2963 21:46:57.110 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2964 21:46:57.110 0.01422736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2965 21:46:57.110 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2966 21:46:57.125 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2967 21:46:57.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2968 21:46:57.125 0.00050015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2969 21:46:57.125 0.00045393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2970 21:46:57.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2971 21:46:57.125 0.00034410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2972 21:46:57.125 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 2973 21:46:57.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2974 21:46:57.125 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2975 21:46:57.125 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 2976 21:46:57.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2977 21:46:57.125 0.00032237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2978 21:46:57.125 0.00033501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2979 21:46:57.125 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 2980 21:46:57.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2981 21:46:57.125 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2982 21:46:57.125 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2983 21:46:57.125 0.00030341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2984 21:46:57.125 0.00026864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 2985 21:46:57.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2986 21:46:57.125 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2987 21:46:57.125 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2988 21:46:57.125 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2989 21:46:57.125 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2990 21:46:57.125 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2991 21:46:57.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2992 21:46:57.125 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 2994 21:46:57.125 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 2995 21:46:57.125 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2996 21:46:57.125 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2997 21:46:57.125 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2998 21:46:57.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2999 21:46:57.125 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3000 21:46:57.125 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3001 21:46:57.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3002 21:46:57.125 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3003 21:46:57.125 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3004 21:46:57.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3005 21:46:57.125 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3006 21:46:57.125 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3007 21:46:57.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3008 21:46:57.125 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3009 21:46:57.125 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3010 21:46:57.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3011 21:46:57.125 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3012 21:46:57.125 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3013 21:46:57.125 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3014 21:46:57.125 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3015 21:46:57.125 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3016 21:46:57.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3017 21:46:57.125 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3018 21:46:57.125 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3019 21:46:57.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3020 21:46:57.125 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3021 21:46:57.125 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3022 21:46:57.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3023 21:46:57.125 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3024 21:46:57.125 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3025 21:46:57.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3026 21:46:57.125 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3027 21:46:57.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3028 21:46:57.125 0.02764208 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3029 21:46:57.157 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3030 21:46:57.157 0.01364267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3032 21:46:57.172 0.00039151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3033 21:46:57.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3034 21:46:57.172 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3035 21:46:57.172 0.00024849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3036 21:46:57.172 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3037 21:46:57.172 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3038 21:46:57.172 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3039 21:46:57.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3040 21:46:57.172 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3041 21:46:57.172 0.00026114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3042 21:46:57.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3043 21:46:57.172 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3044 21:46:57.172 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3045 21:46:57.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3046 21:46:57.172 0.00037254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3047 21:46:57.172 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3048 21:46:57.172 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 3049 21:46:57.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3050 21:46:57.172 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3051 21:46:57.172 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 3052 21:46:57.172 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3053 21:46:57.172 0.00033936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3054 21:46:57.172 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3055 21:46:57.172 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3056 21:46:57.172 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3057 21:46:57.172 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3058 21:46:57.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3059 21:46:57.172 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3060 21:46:57.172 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 3061 21:46:57.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3062 21:46:57.172 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3063 21:46:57.172 0.00028286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 3064 21:46:57.172 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3065 21:46:57.172 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3066 21:46:57.172 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3067 21:46:57.172 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3068 21:46:57.172 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3069 21:46:57.172 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3070 21:46:57.172 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3071 21:46:57.172 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3072 21:46:57.172 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3073 21:46:57.172 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3074 21:46:57.172 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3075 21:46:57.172 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3076 21:46:57.172 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3077 21:46:57.172 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3078 21:46:57.172 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3079 21:46:57.172 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3080 21:46:57.172 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3081 21:46:57.172 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3082 21:46:57.172 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3083 21:46:57.172 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3084 21:46:57.172 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3085 21:46:57.172 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3086 21:46:57.172 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3087 21:46:57.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3088 21:46:57.172 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3089 21:46:57.172 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3090 21:46:57.172 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 44 3091 21:46:57.172 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3092 21:46:57.172 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 3095 21:46:57.204 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3096 21:46:57.204 0.01317610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3097 21:46:57.204 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3098 21:46:57.219 0.00045946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3099 21:46:57.219 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3100 21:46:57.219 0.00039309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3101 21:46:57.219 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3102 21:46:57.219 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3103 21:46:57.219 0.00034844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3104 21:46:57.219 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3105 21:46:57.219 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3106 21:46:57.219 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3107 21:46:57.219 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3108 21:46:57.219 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3109 21:46:57.219 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3110 21:46:57.219 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3111 21:46:57.219 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 3112 21:46:57.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3113 21:46:57.219 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3114 21:46:57.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3115 21:46:57.219 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3116 21:46:57.219 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3117 21:46:57.219 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3118 21:46:57.219 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3119 21:46:57.219 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3120 21:46:57.219 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3121 21:46:57.219 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3122 21:46:57.219 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3123 21:46:57.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3124 21:46:57.219 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3125 21:46:57.219 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3126 21:46:57.219 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3127 21:46:57.219 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 3128 21:46:57.219 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3129 21:46:57.219 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3130 21:46:57.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3131 21:46:57.219 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3132 21:46:57.219 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3133 21:46:57.219 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3134 21:46:57.219 0.00021412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3135 21:46:57.219 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3136 21:46:57.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3137 21:46:57.219 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3138 21:46:57.219 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3139 21:46:57.219 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3140 21:46:57.219 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3141 21:46:57.219 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3142 21:46:57.219 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3143 21:46:57.219 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3144 21:46:57.219 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3145 21:46:57.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3146 21:46:57.219 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3147 21:46:57.219 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3148 21:46:57.219 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3149 21:46:57.219 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3150 21:46:57.219 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3151 21:46:57.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3152 21:46:57.219 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3153 21:46:57.219 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3154 21:46:57.219 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3155 21:46:57.219 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3156 21:46:57.219 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3157 21:46:57.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3158 21:46:57.219 0.02737739 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3159 21:46:57.250 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3160 21:46:57.250 0.01162983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3161 21:46:57.250 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3162 21:46:57.266 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3163 21:46:57.266 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3164 21:46:57.266 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3165 21:46:57.266 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3166 21:46:57.266 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3167 21:46:57.266 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3168 21:46:57.266 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3169 21:46:57.266 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 3170 21:46:57.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3171 21:46:57.266 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3172 21:46:57.266 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3173 21:46:57.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3174 21:46:57.266 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3175 21:46:57.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3176 21:46:57.266 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3177 21:46:57.266 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3178 21:46:57.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3179 21:46:57.266 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3180 21:46:57.266 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3181 21:46:57.266 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3182 21:46:57.266 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3183 21:46:57.266 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3184 21:46:57.266 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3185 21:46:57.266 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3186 21:46:57.266 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3187 21:46:57.266 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3188 21:46:57.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3189 21:46:57.266 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3190 21:46:57.266 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3191 21:46:57.266 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3192 21:46:57.266 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3193 21:46:57.266 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3194 21:46:57.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3195 21:46:57.266 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3196 21:46:57.266 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3197 21:46:57.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3198 21:46:57.266 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3199 21:46:57.266 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3200 21:46:57.266 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3201 21:46:57.266 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3202 21:46:57.266 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3203 21:46:57.266 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3204 21:46:57.266 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3205 21:46:57.266 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3206 21:46:57.266 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3207 21:46:57.266 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3208 21:46:57.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3209 21:46:57.266 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3210 21:46:57.266 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3211 21:46:57.266 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3212 21:46:57.266 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3213 21:46:57.266 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3214 21:46:57.266 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3215 21:46:57.266 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3216 21:46:57.266 0.00027378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3217 21:46:57.266 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3218 21:46:57.266 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3219 21:46:57.266 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3220 21:46:57.266 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3221 21:46:57.266 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3222 21:46:57.266 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3223 21:46:57.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3224 21:46:57.266 0.02692781 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3225 21:46:57.297 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3226 21:46:57.297 0.01381176 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3227 21:46:57.297 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3228 21:46:57.313 0.00029472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3229 21:46:57.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3230 21:46:57.313 0.00045709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3231 21:46:57.313 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3232 21:46:57.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3233 21:46:57.313 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3234 21:46:57.313 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3235 21:46:57.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3236 21:46:57.313 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3237 21:46:57.313 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 3238 21:46:57.313 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3239 21:46:57.313 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3240 21:46:57.313 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 3241 21:46:57.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3242 21:46:57.313 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3243 21:46:57.313 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 3244 21:46:57.313 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3245 21:46:57.313 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3246 21:46:57.313 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3247 21:46:57.313 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3248 21:46:57.313 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3249 21:46:57.313 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3250 21:46:57.313 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3251 21:46:57.313 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3252 21:46:57.313 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3253 21:46:57.313 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3254 21:46:57.313 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3255 21:46:57.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3256 21:46:57.313 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3257 21:46:57.313 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3258 21:46:57.313 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3259 21:46:57.313 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3260 21:46:57.313 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3261 21:46:57.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3262 21:46:57.313 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3263 21:46:57.313 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3264 21:46:57.313 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3265 21:46:57.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3266 21:46:57.313 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3268 21:46:57.313 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3269 21:46:57.313 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3270 21:46:57.313 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3271 21:46:57.313 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3272 21:46:57.313 0.00033343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3273 21:46:57.313 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3274 21:46:57.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3275 21:46:57.313 0.00036267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3276 21:46:57.313 0.00028563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3277 21:46:57.313 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3278 21:46:57.313 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3279 21:46:57.313 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3280 21:46:57.313 0.00008138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3281 21:46:57.313 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3282 21:46:57.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3283 21:46:57.313 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3284 21:46:57.313 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3285 21:46:57.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3286 21:46:57.313 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3287 21:46:57.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3288 21:46:57.313 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3289 21:46:57.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3290 21:46:57.313 0.02838401 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3291 21:46:57.344 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3292 21:46:57.344 0.01235596 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3293 21:46:57.344 0.00001185 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3294 21:46:57.360 0.00032000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3295 21:46:57.360 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3296 21:46:57.360 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3297 21:46:57.360 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3298 21:46:57.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3299 21:46:57.360 0.00033580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3300 21:46:57.360 0.00026785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3301 21:46:57.360 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3302 21:46:57.360 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3303 21:46:57.360 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 3304 21:46:57.360 0.00039901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3305 21:46:57.360 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3306 21:46:57.360 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3307 21:46:57.360 0.00030617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3308 21:46:57.360 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3309 21:46:57.360 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3310 21:46:57.360 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3311 21:46:57.360 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3312 21:46:57.360 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 3313 21:46:57.360 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3314 21:46:57.360 0.00036306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3315 21:46:57.360 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3316 21:46:57.360 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3317 21:46:57.360 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3318 21:46:57.360 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3319 21:46:57.360 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3320 21:46:57.360 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3321 21:46:57.360 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3322 21:46:57.360 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 3323 21:46:57.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3324 21:46:57.360 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3325 21:46:57.360 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3326 21:46:57.360 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3327 21:46:57.360 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3328 21:46:57.360 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3329 21:46:57.360 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3330 21:46:57.360 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3331 21:46:57.360 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3332 21:46:57.360 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3333 21:46:57.360 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3334 21:46:57.360 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3335 21:46:57.360 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3336 21:46:57.360 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3337 21:46:57.360 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3338 21:46:57.360 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3339 21:46:57.360 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3340 21:46:57.360 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3341 21:46:57.360 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3342 21:46:57.360 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3343 21:46:57.360 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3344 21:46:57.360 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3345 21:46:57.360 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3346 21:46:57.360 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3347 21:46:57.360 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3348 21:46:57.360 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3349 21:46:57.360 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3350 21:46:57.360 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3351 21:46:57.360 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3352 21:46:57.360 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3353 21:46:57.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3354 21:46:57.360 0.02482332 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3355 21:46:57.391 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3356 21:46:57.391 0.01412544 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3357 21:46:57.391 0.00002015 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3358 21:46:57.406 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3359 21:46:57.406 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3360 21:46:57.406 0.00036267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3361 21:46:57.406 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3362 21:46:57.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3363 21:46:57.406 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3364 21:46:57.406 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3365 21:46:57.406 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3366 21:46:57.406 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3367 21:46:57.406 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 3368 21:46:57.406 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3369 21:46:57.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3370 21:46:57.406 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3371 21:46:57.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3372 21:46:57.406 0.00027733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3373 21:46:57.406 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 3374 21:46:57.406 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3375 21:46:57.406 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3376 21:46:57.406 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3377 21:46:57.406 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3378 21:46:57.406 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3379 21:46:57.406 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3380 21:46:57.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3381 21:46:57.406 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3382 21:46:57.406 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3383 21:46:57.406 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3384 21:46:57.406 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3385 21:46:57.406 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3386 21:46:57.406 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 3387 21:46:57.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3388 21:46:57.406 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3389 21:46:57.406 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3390 21:46:57.406 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3391 21:46:57.406 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3392 21:46:57.406 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3393 21:46:57.406 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3394 21:46:57.406 0.00008296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3395 21:46:57.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3396 21:46:57.406 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3397 21:46:57.406 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3398 21:46:57.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3399 21:46:57.406 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3400 21:46:57.406 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3401 21:46:57.406 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3402 21:46:57.406 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3403 21:46:57.406 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3404 21:46:57.406 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3405 21:46:57.406 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3406 21:46:57.406 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3407 21:46:57.406 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3408 21:46:57.406 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3409 21:46:57.406 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3410 21:46:57.406 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3411 21:46:57.406 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3412 21:46:57.406 0.00032435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3413 21:46:57.406 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3414 21:46:57.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3415 21:46:57.406 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3416 21:46:57.406 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3417 21:46:57.406 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3418 21:46:57.406 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3419 21:46:57.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3420 21:46:57.406 0.02760653 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3421 21:46:57.438 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3422 21:46:57.438 0.01401680 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3424 21:46:57.453 0.00048909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3425 21:46:57.453 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3426 21:46:57.453 0.00048672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3427 21:46:57.453 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3428 21:46:57.453 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3429 21:46:57.453 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3430 21:46:57.453 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3431 21:46:57.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3432 21:46:57.453 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3433 21:46:57.453 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 3434 21:46:57.453 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3435 21:46:57.453 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3436 21:46:57.453 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3437 21:46:57.453 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3438 21:46:57.453 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3439 21:46:57.453 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3440 21:46:57.453 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3441 21:46:57.453 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3442 21:46:57.453 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3443 21:46:57.453 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3444 21:46:57.453 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3445 21:46:57.453 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3446 21:46:57.453 0.00029906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3447 21:46:57.453 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3448 21:46:57.453 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3449 21:46:57.453 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3450 21:46:57.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3451 21:46:57.453 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3452 21:46:57.453 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3453 21:46:57.453 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3454 21:46:57.453 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3455 21:46:57.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3456 21:46:57.453 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3457 21:46:57.453 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3458 21:46:57.453 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3459 21:46:57.453 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3460 21:46:57.453 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3461 21:46:57.453 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3462 21:46:57.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3463 21:46:57.453 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3464 21:46:57.453 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3465 21:46:57.453 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3466 21:46:57.453 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3467 21:46:57.453 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3468 21:46:57.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3469 21:46:57.453 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3470 21:46:57.453 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3471 21:46:57.453 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3472 21:46:57.453 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3473 21:46:57.453 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3474 21:46:57.453 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3475 21:46:57.453 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3476 21:46:57.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3477 21:46:57.453 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3478 21:46:57.453 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3479 21:46:57.453 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3480 21:46:57.453 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3481 21:46:57.453 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3482 21:46:57.453 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3483 21:46:57.453 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3484 21:46:57.453 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3485 21:46:57.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3486 21:46:57.453 0.02748999 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3487 21:46:57.485 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3488 21:46:57.485 0.01276761 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3489 21:46:57.485 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3490 21:46:57.500 0.00031961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3491 21:46:57.500 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3492 21:46:57.500 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3493 21:46:57.500 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3494 21:46:57.500 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3495 21:46:57.500 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3496 21:46:57.500 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3497 21:46:57.500 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3498 21:46:57.500 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 3499 21:46:57.500 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3500 21:46:57.500 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3501 21:46:57.500 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3502 21:46:57.500 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3503 21:46:57.500 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 3504 21:46:57.500 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3505 21:46:57.500 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3506 21:46:57.500 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3507 21:46:57.500 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 3508 21:46:57.500 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 50 3511 21:46:57.500 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3512 21:46:57.500 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3513 21:46:57.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3514 21:46:57.500 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3515 21:46:57.500 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3516 21:46:57.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3517 21:46:57.500 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3518 21:46:57.500 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 3519 21:46:57.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3520 21:46:57.500 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3521 21:46:57.500 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3522 21:46:57.500 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3523 21:46:57.500 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3524 21:46:57.500 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3525 21:46:57.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3526 21:46:57.500 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3527 21:46:57.500 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3528 21:46:57.500 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3529 21:46:57.500 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3530 21:46:57.500 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3531 21:46:57.500 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3532 21:46:57.500 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3533 21:46:57.500 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3534 21:46:57.500 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3535 21:46:57.500 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3536 21:46:57.500 0.00008375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3537 21:46:57.500 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3538 21:46:57.500 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3539 21:46:57.500 0.00007822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3540 21:46:57.500 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3541 21:46:57.500 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3542 21:46:57.500 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3543 21:46:57.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3544 21:46:57.500 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3545 21:46:57.500 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3546 21:46:57.500 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3547 21:46:57.500 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3548 21:46:57.500 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3549 21:46:57.500 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3550 21:46:57.500 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3551 21:46:57.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3552 21:46:57.500 0.02755478 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3553 21:46:57.532 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3554 21:46:57.532 0.01494006 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3555 21:46:57.532 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3556 21:46:57.547 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3557 21:46:57.547 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3558 21:46:57.547 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3559 21:46:57.547 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3560 21:46:57.547 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3561 21:46:57.547 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3562 21:46:57.547 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3563 21:46:57.547 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 3564 21:46:57.547 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3565 21:46:57.547 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3567 21:46:57.547 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3568 21:46:57.547 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3569 21:46:57.547 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3570 21:46:57.547 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3571 21:46:57.547 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3572 21:46:57.547 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3573 21:46:57.547 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 3574 21:46:57.547 0.00024415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3575 21:46:57.547 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3576 21:46:57.547 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3577 21:46:57.547 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3578 21:46:57.547 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3579 21:46:57.547 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3580 21:46:57.547 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3581 21:46:57.547 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3582 21:46:57.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3583 21:46:57.547 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3584 21:46:57.547 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 3585 21:46:57.547 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3586 21:46:57.547 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3587 21:46:57.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3588 21:46:57.547 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3589 21:46:57.547 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3590 21:46:57.547 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3591 21:46:57.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3592 21:46:57.547 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3593 21:46:57.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3594 21:46:57.547 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3595 21:46:57.547 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3596 21:46:57.547 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3597 21:46:57.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3598 21:46:57.547 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3599 21:46:57.547 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3600 21:46:57.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3601 21:46:57.547 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3602 21:46:57.547 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3603 21:46:57.547 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3604 21:46:57.547 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3605 21:46:57.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3606 21:46:57.547 0.00030143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3607 21:46:57.547 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3608 21:46:57.547 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3609 21:46:57.547 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3610 21:46:57.547 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3611 21:46:57.547 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3612 21:46:57.547 0.00027457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3613 21:46:57.547 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3614 21:46:57.547 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3615 21:46:57.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3616 21:46:57.547 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3617 21:46:57.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3618 21:46:57.547 0.02596228 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3619 21:46:57.578 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3620 21:46:57.578 0.01337838 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3621 21:46:57.578 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3622 21:46:57.594 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3623 21:46:57.594 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3624 21:46:57.594 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3625 21:46:57.594 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3626 21:46:57.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3627 21:46:57.594 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3628 21:46:57.594 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3629 21:46:57.594 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3630 21:46:57.594 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3631 21:46:57.594 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 3632 21:46:57.594 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3633 21:46:57.594 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3634 21:46:57.594 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3635 21:46:57.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3636 21:46:57.594 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 3637 21:46:57.594 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3638 21:46:57.594 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3639 21:46:57.594 0.00037689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3640 21:46:57.594 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3641 21:46:57.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3642 21:46:57.594 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3643 21:46:57.594 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3644 21:46:57.594 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3645 21:46:57.594 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3646 21:46:57.594 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3647 21:46:57.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3648 21:46:57.594 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3649 21:46:57.594 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3650 21:46:57.594 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 3651 21:46:57.594 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3652 21:46:57.594 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3653 21:46:57.594 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3654 21:46:57.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3655 21:46:57.594 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3656 21:46:57.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3657 21:46:57.594 0.00020425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3658 21:46:57.594 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3659 21:46:57.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3660 21:46:57.594 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3661 21:46:57.594 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3662 21:46:57.594 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3663 21:46:57.594 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3664 21:46:57.594 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3665 21:46:57.594 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3666 21:46:57.594 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3667 21:46:57.594 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3668 21:46:57.594 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3669 21:46:57.594 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3670 21:46:57.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3671 21:46:57.594 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3672 21:46:57.594 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3673 21:46:57.594 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3674 21:46:57.594 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3675 21:46:57.594 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3676 21:46:57.594 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3677 21:46:57.594 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3678 21:46:57.594 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3679 21:46:57.594 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3680 21:46:57.594 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3681 21:46:57.594 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3682 21:46:57.594 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3683 21:46:57.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3684 21:46:57.594 0.02698036 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3685 21:46:57.625 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3686 21:46:57.625 0.01418272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3687 21:46:57.625 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3688 21:46:57.641 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3689 21:46:57.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3690 21:46:57.641 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3691 21:46:57.641 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3692 21:46:57.641 0.00099832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3693 21:46:57.641 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3694 21:46:57.641 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3695 21:46:57.641 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3696 21:46:57.641 0.00043496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 3697 21:46:57.641 0.00051911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3698 21:46:57.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3699 21:46:57.641 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3700 21:46:57.641 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3701 21:46:57.641 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3702 21:46:57.641 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3703 21:46:57.641 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 3704 21:46:57.641 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3705 21:46:57.641 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3706 21:46:57.641 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3707 21:46:57.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3708 21:46:57.641 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3709 21:46:57.641 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3710 21:46:57.641 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3711 21:46:57.641 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3712 21:46:57.641 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3713 21:46:57.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3714 21:46:57.641 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3715 21:46:57.641 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3716 21:46:57.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3717 21:46:57.641 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3718 21:46:57.641 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3719 21:46:57.641 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3720 21:46:57.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3721 21:46:57.641 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3722 21:46:57.641 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3723 21:46:57.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3724 21:46:57.641 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3725 21:46:57.641 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3726 21:46:57.641 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3727 21:46:57.641 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3728 21:46:57.641 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3729 21:46:57.641 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3730 21:46:57.641 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3731 21:46:57.641 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3732 21:46:57.641 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3733 21:46:57.641 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3734 21:46:57.641 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3735 21:46:57.641 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3736 21:46:57.641 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3737 21:46:57.641 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3738 21:46:57.641 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3739 21:46:57.641 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3740 21:46:57.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3741 21:46:57.641 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3742 21:46:57.641 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3743 21:46:57.641 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3744 21:46:57.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3745 21:46:57.641 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3746 21:46:57.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3747 21:46:57.641 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3748 21:46:57.641 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3749 21:46:57.641 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3750 21:46:57.641 0.02581255 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3751 21:46:57.672 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3752 21:46:57.672 0.01457660 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3753 21:46:57.672 0.00003240 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3754 21:46:57.687 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3755 21:46:57.687 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3756 21:46:57.687 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3757 21:46:57.687 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3758 21:46:57.687 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3759 21:46:57.687 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3760 21:46:57.687 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3761 21:46:57.687 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3762 21:46:57.687 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3763 21:46:57.687 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 3764 21:46:57.687 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 3765 21:46:57.687 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3766 21:46:57.687 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 3768 21:46:57.687 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3769 21:46:57.687 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3770 21:46:57.687 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3771 21:46:57.687 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3772 21:46:57.687 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3773 21:46:57.687 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3774 21:46:57.687 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3775 21:46:57.687 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3776 21:46:57.687 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3777 21:46:57.687 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3778 21:46:57.687 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3779 21:46:57.687 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3780 21:46:57.687 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3781 21:46:57.687 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3782 21:46:57.687 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3783 21:46:57.687 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3784 21:46:57.687 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 3785 21:46:57.687 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3786 21:46:57.687 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3787 21:46:57.687 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3788 21:46:57.687 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3789 21:46:57.687 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3790 21:46:57.687 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3791 21:46:57.687 0.00023546 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3792 21:46:57.687 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3793 21:46:57.687 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3794 21:46:57.687 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3795 21:46:57.687 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3796 21:46:57.687 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3797 21:46:57.687 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3798 21:46:57.687 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3799 21:46:57.687 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3800 21:46:57.687 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3801 21:46:57.687 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3802 21:46:57.687 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3803 21:46:57.687 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3804 21:46:57.687 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3805 21:46:57.687 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3806 21:46:57.687 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3807 21:46:57.687 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3808 21:46:57.687 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3809 21:46:57.687 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3810 21:46:57.687 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3811 21:46:57.687 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3812 21:46:57.687 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3813 21:46:57.687 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3814 21:46:57.687 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3815 21:46:57.687 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3816 21:46:57.687 0.02809838 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3817 21:46:57.719 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3818 21:46:57.719 0.01334598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3819 21:46:57.719 0.00000435 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3820 21:46:57.734 0.00031842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3821 21:46:57.734 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3822 21:46:57.734 0.00033699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3823 21:46:57.734 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3824 21:46:57.734 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3825 21:46:57.734 0.00057758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3826 21:46:57.734 0.00055506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3827 21:46:57.734 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3828 21:46:57.734 0.00040573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3829 21:46:57.734 0.00032948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 3830 21:46:57.734 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3831 21:46:57.734 0.00038321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3832 21:46:57.734 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3833 21:46:57.734 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3834 21:46:57.734 0.00032119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3835 21:46:57.734 0.00031684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3836 21:46:57.734 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 3837 21:46:57.734 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3838 21:46:57.734 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3839 21:46:57.734 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3840 21:46:57.734 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3841 21:46:57.734 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3842 21:46:57.734 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3843 21:46:57.734 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3844 21:46:57.734 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3845 21:46:57.734 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3846 21:46:57.734 0.00036622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3847 21:46:57.734 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3848 21:46:57.734 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 3849 21:46:57.734 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3850 21:46:57.734 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3851 21:46:57.734 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3852 21:46:57.734 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3853 21:46:57.734 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3854 21:46:57.734 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3855 21:46:57.734 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3856 21:46:57.734 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3857 21:46:57.734 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3858 21:46:57.734 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3859 21:46:57.734 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3860 21:46:57.734 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3861 21:46:57.734 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3862 21:46:57.734 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3863 21:46:57.734 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3864 21:46:57.734 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3865 21:46:57.734 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3866 21:46:57.734 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3867 21:46:57.734 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3868 21:46:57.734 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3869 21:46:57.734 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3870 21:46:57.734 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3871 21:46:57.734 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3872 21:46:57.734 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3873 21:46:57.734 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3874 21:46:57.734 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3875 21:46:57.734 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3876 21:46:57.734 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3877 21:46:57.734 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3878 21:46:57.734 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3879 21:46:57.734 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3880 21:46:57.734 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3881 21:46:57.734 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3882 21:46:57.734 0.02570075 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3883 21:46:57.766 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3884 21:46:57.766 0.01287072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3885 21:46:57.766 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3886 21:46:57.781 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3887 21:46:57.781 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3888 21:46:57.781 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3889 21:46:57.781 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3890 21:46:57.781 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3891 21:46:57.781 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3892 21:46:57.781 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 3893 21:46:57.781 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 3894 21:46:57.781 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3895 21:46:57.781 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3896 21:46:57.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3897 21:46:57.781 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3898 21:46:57.781 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3899 21:46:57.781 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3900 21:46:57.781 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3901 21:46:57.781 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 3902 21:46:57.781 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3903 21:46:57.781 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3904 21:46:57.781 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3905 21:46:57.781 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 3906 21:46:57.781 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3907 21:46:57.781 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3908 21:46:57.781 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3909 21:46:57.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3910 21:46:57.781 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3911 21:46:57.781 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 3912 21:46:57.781 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3913 21:46:57.781 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3914 21:46:57.781 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3915 21:46:57.781 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3916 21:46:57.781 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3917 21:46:57.781 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3918 21:46:57.781 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3919 21:46:57.781 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3920 21:46:57.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3921 21:46:57.781 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3922 21:46:57.781 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3923 21:46:57.781 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3924 21:46:57.781 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3925 21:46:57.781 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3926 21:46:57.781 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3927 21:46:57.781 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3928 21:46:57.781 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3929 21:46:57.781 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3930 21:46:57.781 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3931 21:46:57.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3932 21:46:57.781 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3933 21:46:57.781 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3934 21:46:57.781 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3935 21:46:57.781 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3936 21:46:57.781 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3937 21:46:57.781 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3938 21:46:57.781 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3939 21:46:57.781 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3940 21:46:57.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3941 21:46:57.781 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3942 21:46:57.781 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 3943 21:46:57.781 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3944 21:46:57.781 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3945 21:46:57.781 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3946 21:46:57.781 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3947 21:46:57.781 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3948 21:46:57.781 0.02895330 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3949 21:46:57.812 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3950 21:46:57.812 0.01284188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3951 21:46:57.812 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 3952 21:46:57.828 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 3953 21:46:57.828 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3954 21:46:57.828 0.00036425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3955 21:46:57.828 0.00030025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 3956 21:46:57.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3957 21:46:57.828 0.00115911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3958 21:46:57.828 0.00112119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 3959 21:46:57.828 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3960 21:46:57.828 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3961 21:46:57.828 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 3962 21:46:57.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3963 21:46:57.828 0.00032000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3964 21:46:57.828 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 3965 21:46:57.828 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3966 21:46:57.828 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3967 21:46:57.828 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3968 21:46:57.828 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3969 21:46:57.828 0.00026430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3970 21:46:57.828 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3971 21:46:57.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3972 21:46:57.828 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3973 21:46:57.828 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3974 21:46:57.828 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3975 21:46:57.828 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3976 21:46:57.828 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3977 21:46:57.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3978 21:46:57.828 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3979 21:46:57.828 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3980 21:46:57.828 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 3981 21:46:57.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3982 21:46:57.828 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3983 21:46:57.828 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3984 21:46:57.828 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 3985 21:46:57.828 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3986 21:46:57.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3987 21:46:57.828 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 3988 21:46:57.828 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3989 21:46:57.828 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3990 21:46:57.828 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3991 21:46:57.828 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3992 21:46:57.828 0.00028879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3993 21:46:57.828 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3994 21:46:57.828 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3995 21:46:57.828 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3996 21:46:57.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3997 21:46:57.828 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 3998 21:46:57.828 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 3999 21:46:57.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4000 21:46:57.828 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4001 21:46:57.828 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4002 21:46:57.828 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4003 21:46:57.828 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4004 21:46:57.828 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4005 21:46:57.828 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4006 21:46:57.828 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4007 21:46:57.828 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4008 21:46:57.828 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4009 21:46:57.828 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4010 21:46:57.828 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4011 21:46:57.828 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4012 21:46:57.828 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4013 21:46:57.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4014 21:46:57.828 0.02649601 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4015 21:46:57.859 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4016 21:46:57.859 0.01398559 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4017 21:46:57.859 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4018 21:46:57.875 0.00028286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4019 21:46:57.875 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4020 21:46:57.875 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4021 21:46:57.875 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4022 21:46:57.875 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 4023 21:46:57.875 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4024 21:46:57.875 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4025 21:46:57.875 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 4026 21:46:57.875 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4027 21:46:57.875 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4028 21:46:57.875 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4029 21:46:57.875 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4030 21:46:57.875 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4031 21:46:57.875 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4032 21:46:57.875 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4033 21:46:57.875 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4034 21:46:57.875 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4035 21:46:57.875 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4036 21:46:57.875 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4037 21:46:57.875 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4038 21:46:57.875 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4039 21:46:57.875 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4040 21:46:57.875 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4041 21:46:57.875 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4042 21:46:57.875 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4043 21:46:57.875 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 4044 21:46:57.875 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4045 21:46:57.875 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4046 21:46:57.875 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4047 21:46:57.875 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4048 21:46:57.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4049 21:46:57.875 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4050 21:46:57.875 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4051 21:46:57.875 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4052 21:46:57.875 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4053 21:46:57.875 0.00008296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4054 21:46:57.875 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4055 21:46:57.875 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4056 21:46:57.875 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4057 21:46:57.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4058 21:46:57.875 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4059 21:46:57.875 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4060 21:46:57.875 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4061 21:46:57.875 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4062 21:46:57.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4063 21:46:57.875 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4064 21:46:57.875 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4065 21:46:57.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4066 21:46:57.875 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4067 21:46:57.875 0.00025719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4068 21:46:57.875 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4069 21:46:57.875 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4070 21:46:57.875 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4071 21:46:57.875 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4072 21:46:57.875 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4073 21:46:57.875 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4074 21:46:57.875 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4075 21:46:57.875 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4076 21:46:57.875 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4077 21:46:57.875 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4078 21:46:57.875 0.02873088 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4079 21:46:57.906 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4080 21:46:57.906 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4081 21:46:57.906 0.01286005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4082 21:46:57.922 0.00035595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4083 21:46:57.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4084 21:46:57.922 0.00037610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4085 21:46:57.922 0.00033817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4086 21:46:57.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4087 21:46:57.922 0.00031684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4088 21:46:57.922 0.00026548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4089 21:46:57.922 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: D0 4090 21:46:57.922 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4091 21:46:57.922 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4094 21:46:57.922 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4095 21:46:57.922 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4096 21:46:57.922 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4097 21:46:57.922 0.00027259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4098 21:46:57.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4099 21:46:57.922 0.00032040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4100 21:46:57.922 0.00045551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 4101 21:46:57.922 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 4102 21:46:57.922 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4103 21:46:57.922 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4104 21:46:57.922 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4105 21:46:57.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4106 21:46:57.922 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4107 21:46:57.922 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4108 21:46:57.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4109 21:46:57.922 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4110 21:46:57.922 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 4111 21:46:57.922 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4112 21:46:57.922 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4113 21:46:57.922 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 4114 21:46:57.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4115 21:46:57.922 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4116 21:46:57.922 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4117 21:46:57.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4118 21:46:57.922 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4119 21:46:57.922 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4120 21:46:57.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4121 21:46:57.922 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4122 21:46:57.922 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4123 21:46:57.922 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4124 21:46:57.922 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4125 21:46:57.922 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4126 21:46:57.922 0.00027733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4127 21:46:57.922 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4128 21:46:57.922 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4129 21:46:57.922 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4130 21:46:57.922 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4131 21:46:57.922 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4132 21:46:57.922 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4133 21:46:57.922 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4134 21:46:57.922 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4135 21:46:57.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4136 21:46:57.922 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4137 21:46:57.922 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4138 21:46:57.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4139 21:46:57.922 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4140 21:46:57.922 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4141 21:46:57.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4142 21:46:57.922 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4143 21:46:57.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4144 21:46:57.922 0.02421927 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4145 21:46:57.953 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4146 21:46:57.953 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4147 21:46:57.953 0.01481759 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4148 21:46:57.969 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4149 21:46:57.969 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4150 21:46:57.969 0.00046696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4151 21:46:57.969 0.00034410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4152 21:46:57.969 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 11 4153 21:46:57.969 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4156 21:46:57.969 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4157 21:46:57.969 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4158 21:46:57.969 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4159 21:46:57.969 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4160 21:46:57.969 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4161 21:46:57.969 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4162 21:46:57.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4163 21:46:57.969 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4164 21:46:57.969 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4165 21:46:57.969 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4166 21:46:57.969 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4167 21:46:57.969 0.00029906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4168 21:46:57.969 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4169 21:46:57.969 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4170 21:46:57.969 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4171 21:46:57.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4172 21:46:57.969 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4173 21:46:57.969 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4174 21:46:57.969 0.00055348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 4175 21:46:57.969 0.00038874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4176 21:46:57.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4177 21:46:57.969 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4178 21:46:57.969 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 4179 21:46:57.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4180 21:46:57.969 0.00027694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4181 21:46:57.969 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4182 21:46:57.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4183 21:46:57.969 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4184 21:46:57.969 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4185 21:46:57.969 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4186 21:46:57.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4187 21:46:57.969 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4188 21:46:57.969 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4189 21:46:57.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4190 21:46:57.969 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4191 21:46:57.969 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4192 21:46:57.969 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4193 21:46:57.969 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4194 21:46:57.969 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4195 21:46:57.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4196 21:46:57.969 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4197 21:46:57.969 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4198 21:46:57.969 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4199 21:46:57.969 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4200 21:46:57.969 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4201 21:46:57.969 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4202 21:46:57.969 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4203 21:46:57.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4204 21:46:57.969 0.00025521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4205 21:46:57.969 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4206 21:46:57.969 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4207 21:46:57.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4208 21:46:57.969 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4209 21:46:57.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4210 21:46:57.969 0.02637552 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4211 21:46:58.000 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4212 21:46:58.000 0.01333057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4213 21:46:58.000 0.00000395 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4214 21:46:58.016 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4215 21:46:58.016 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4216 21:46:58.016 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4217 21:46:58.016 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4218 21:46:58.016 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4219 21:46:58.016 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4220 21:46:58.016 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4221 21:46:58.016 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 4222 21:46:58.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4223 21:46:58.016 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4224 21:46:58.016 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4225 21:46:58.016 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4226 21:46:58.016 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4227 21:46:58.016 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4228 21:46:58.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4229 21:46:58.016 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4230 21:46:58.016 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4231 21:46:58.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4232 21:46:58.016 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4233 21:46:58.016 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4234 21:46:58.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4235 21:46:58.016 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4236 21:46:58.016 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4237 21:46:58.016 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4238 21:46:58.016 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4239 21:46:58.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4240 21:46:58.016 0.00026667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4241 21:46:58.016 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4242 21:46:58.016 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4243 21:46:58.016 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4244 21:46:58.016 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4245 21:46:58.016 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4246 21:46:58.016 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4247 21:46:58.016 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4248 21:46:58.016 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4249 21:46:58.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4250 21:46:58.016 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4251 21:46:58.016 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4252 21:46:58.016 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4253 21:46:58.016 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4254 21:46:58.016 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4255 21:46:58.016 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4256 21:46:58.016 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4257 21:46:58.016 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4258 21:46:58.016 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4259 21:46:58.016 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4260 21:46:58.016 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4261 21:46:58.016 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4262 21:46:58.016 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4263 21:46:58.016 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4264 21:46:58.016 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4265 21:46:58.016 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4266 21:46:58.016 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4267 21:46:58.016 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4268 21:46:58.016 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4269 21:46:58.016 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4270 21:46:58.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4271 21:46:58.016 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4272 21:46:58.016 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4273 21:46:58.016 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4274 21:46:58.016 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4275 21:46:58.016 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4276 21:46:58.016 0.02636090 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4277 21:46:58.047 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4278 21:46:58.047 0.01543349 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4279 21:46:58.047 0.00003674 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4280 21:46:58.063 0.00036464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4281 21:46:58.063 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4282 21:46:58.063 0.00042193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4283 21:46:58.063 0.00036425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4284 21:46:58.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4285 21:46:58.063 0.00039427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4286 21:46:58.063 0.00032198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 4287 21:46:58.063 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4288 21:46:58.063 0.00023269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4289 21:46:58.063 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 4290 21:46:58.063 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4291 21:46:58.063 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4292 21:46:58.063 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4293 21:46:58.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4294 21:46:58.063 0.00039072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4295 21:46:58.063 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4296 21:46:58.063 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4297 21:46:58.063 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4298 21:46:58.063 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4299 21:46:58.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4300 21:46:58.063 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4301 21:46:58.063 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4302 21:46:58.063 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4303 21:46:58.063 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4304 21:46:58.063 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4305 21:46:58.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4306 21:46:58.063 0.00028840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4307 21:46:58.063 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 4308 21:46:58.063 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4309 21:46:58.063 0.00035516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 4310 21:46:58.063 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4311 21:46:58.063 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4312 21:46:58.063 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4313 21:46:58.063 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4314 21:46:58.063 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4315 21:46:58.063 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4316 21:46:58.063 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4317 21:46:58.063 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4318 21:46:58.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4319 21:46:58.063 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4320 21:46:58.063 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4321 21:46:58.063 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4322 21:46:58.063 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4323 21:46:58.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4324 21:46:58.063 0.00033264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4325 21:46:58.063 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4326 21:46:58.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4327 21:46:58.063 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4328 21:46:58.063 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4329 21:46:58.063 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4330 21:46:58.063 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4331 21:46:58.063 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4332 21:46:58.063 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4333 21:46:58.063 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4334 21:46:58.063 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4335 21:46:58.063 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4336 21:46:58.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4337 21:46:58.063 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4338 21:46:58.063 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4339 21:46:58.063 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4340 21:46:58.063 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4341 21:46:58.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4342 21:46:58.063 0.02849581 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4343 21:46:58.094 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4344 21:46:58.094 0.01203200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4345 21:46:58.094 0.00003002 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4346 21:46:58.110 0.00033383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4347 21:46:58.110 0.00136257 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4348 21:46:58.110 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4349 21:46:58.110 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4350 21:46:58.110 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4351 21:46:58.110 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 4352 21:46:58.110 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4353 21:46:58.110 0.00024217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4354 21:46:58.110 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4355 21:46:58.110 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4356 21:46:58.110 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4357 21:46:58.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4358 21:46:58.110 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4359 21:46:58.110 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4360 21:46:58.110 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 4361 21:46:58.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4362 21:46:58.110 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4363 21:46:58.110 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4364 21:46:58.110 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4365 21:46:58.110 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4366 21:46:58.110 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4367 21:46:58.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4368 21:46:58.110 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4369 21:46:58.110 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4370 21:46:58.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4371 21:46:58.110 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4372 21:46:58.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4373 21:46:58.110 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4374 21:46:58.110 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 4375 21:46:58.110 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 38 4376 21:46:58.110 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4381 21:46:58.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4382 21:46:58.110 0.00031961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4383 21:46:58.110 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4384 21:46:58.110 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4385 21:46:58.110 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4386 21:46:58.110 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4387 21:46:58.110 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4388 21:46:58.110 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4389 21:46:58.110 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4390 21:46:58.110 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4391 21:46:58.110 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4392 21:46:58.110 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4393 21:46:58.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4394 21:46:58.110 0.00031407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4395 21:46:58.110 0.00028128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4396 21:46:58.110 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4397 21:46:58.110 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4398 21:46:58.110 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4399 21:46:58.110 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4400 21:46:58.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4401 21:46:58.110 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4402 21:46:58.110 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4403 21:46:58.110 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4404 21:46:58.110 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4405 21:46:58.110 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4406 21:46:58.110 0.02523418 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4407 21:46:58.141 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4408 21:46:58.141 0.01481206 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4409 21:46:58.141 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4410 21:46:58.157 0.00038005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4411 21:46:58.157 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4412 21:46:58.157 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4413 21:46:58.157 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4414 21:46:58.157 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4415 21:46:58.157 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4416 21:46:58.157 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 11 4417 21:46:58.157 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4418 21:46:58.157 0.00029946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 4419 21:46:58.157 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4420 21:46:58.157 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4421 21:46:58.157 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4422 21:46:58.157 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4423 21:46:58.157 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 4C 4424 21:46:58.157 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4425 21:46:58.157 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4427 21:46:58.157 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4428 21:46:58.157 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4429 21:46:58.157 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4430 21:46:58.157 0.00027022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4431 21:46:58.157 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4432 21:46:58.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4433 21:46:58.157 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4434 21:46:58.157 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4435 21:46:58.157 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 4436 21:46:58.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4437 21:46:58.157 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4438 21:46:58.157 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 4439 21:46:58.157 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4440 21:46:58.157 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4441 21:46:58.157 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4442 21:46:58.157 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4443 21:46:58.157 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4444 21:46:58.157 0.00025719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4445 21:46:58.157 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4446 21:46:58.157 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4447 21:46:58.157 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4448 21:46:58.157 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4449 21:46:58.157 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4450 21:46:58.157 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4451 21:46:58.157 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4452 21:46:58.157 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4453 21:46:58.157 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4454 21:46:58.157 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4455 21:46:58.157 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4456 21:46:58.157 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4457 21:46:58.157 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4458 21:46:58.157 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4459 21:46:58.157 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4460 21:46:58.157 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4461 21:46:58.157 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4462 21:46:58.157 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4463 21:46:58.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4464 21:46:58.157 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4465 21:46:58.157 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4466 21:46:58.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4467 21:46:58.157 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4468 21:46:58.157 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4469 21:46:58.157 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4470 21:46:58.157 0.00020583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4471 21:46:58.157 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4472 21:46:58.157 0.02625660 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4473 21:46:58.188 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4474 21:46:58.188 0.01416968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4475 21:46:58.188 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4476 21:46:58.204 0.00026983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4477 21:46:58.204 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4478 21:46:58.204 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4479 21:46:58.204 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4480 21:46:58.204 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 4481 21:46:58.204 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4482 21:46:58.204 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4483 21:46:58.204 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4484 21:46:58.204 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4485 21:46:58.204 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4486 21:46:58.204 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4487 21:46:58.204 0.00031170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4488 21:46:58.204 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4489 21:46:58.204 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4490 21:46:58.204 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4491 21:46:58.204 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4492 21:46:58.204 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4493 21:46:58.204 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4494 21:46:58.204 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4495 21:46:58.204 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4496 21:46:58.204 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4497 21:46:58.204 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4498 21:46:58.204 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4499 21:46:58.204 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4500 21:46:58.204 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4501 21:46:58.204 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4502 21:46:58.204 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4503 21:46:58.204 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4504 21:46:58.204 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4505 21:46:58.204 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4506 21:46:58.204 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4507 21:46:58.204 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4508 21:46:58.204 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4509 21:46:58.204 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4510 21:46:58.204 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4511 21:46:58.204 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4512 21:46:58.204 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4513 21:46:58.204 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4514 21:46:58.204 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4515 21:46:58.204 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4516 21:46:58.204 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4517 21:46:58.204 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4518 21:46:58.204 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4519 21:46:58.204 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 4522 21:46:58.204 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4523 21:46:58.204 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4524 21:46:58.204 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4525 21:46:58.204 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4526 21:46:58.204 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4527 21:46:58.204 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4528 21:46:58.204 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4529 21:46:58.204 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4530 21:46:58.204 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4531 21:46:58.204 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4532 21:46:58.204 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4533 21:46:58.204 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4534 21:46:58.204 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4535 21:46:58.204 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4536 21:46:58.204 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4537 21:46:58.204 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4538 21:46:58.204 0.02733117 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4539 21:46:58.234 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4540 21:46:58.234 0.01205057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4541 21:46:58.234 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4542 21:46:58.250 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4543 21:46:58.250 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4544 21:46:58.250 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4545 21:46:58.250 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4546 21:46:58.250 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4547 21:46:58.250 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 4548 21:46:58.250 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4549 21:46:58.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4550 21:46:58.250 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4551 21:46:58.250 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4552 21:46:58.250 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4553 21:46:58.250 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4554 21:46:58.250 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4555 21:46:58.250 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4556 21:46:58.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4557 21:46:58.250 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4558 21:46:58.250 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4559 21:46:58.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4560 21:46:58.250 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4561 21:46:58.250 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4562 21:46:58.250 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4563 21:46:58.250 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4564 21:46:58.250 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4565 21:46:58.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4566 21:46:58.250 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4567 21:46:58.250 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 4568 21:46:58.250 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4569 21:46:58.250 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4570 21:46:58.250 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4571 21:46:58.250 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4572 21:46:58.250 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 4573 21:46:58.250 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4574 21:46:58.250 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4575 21:46:58.250 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4576 21:46:58.250 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4577 21:46:58.250 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4579 21:46:58.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4580 21:46:58.250 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4581 21:46:58.250 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4582 21:46:58.250 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4583 21:46:58.250 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4584 21:46:58.250 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4585 21:46:58.250 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4586 21:46:58.250 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4587 21:46:58.250 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4588 21:46:58.250 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4589 21:46:58.250 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4590 21:46:58.250 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4591 21:46:58.250 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4592 21:46:58.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4593 21:46:58.250 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4594 21:46:58.250 0.00023032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4595 21:46:58.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4596 21:46:58.250 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4597 21:46:58.250 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4598 21:46:58.250 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4599 21:46:58.250 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4600 21:46:58.250 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4601 21:46:58.250 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4602 21:46:58.250 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4605 21:46:58.281 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4606 21:46:58.281 0.01470223 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4607 21:46:58.281 0.00001620 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4608 21:46:58.297 0.00030183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4609 21:46:58.297 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4610 21:46:58.297 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4611 21:46:58.297 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4612 21:46:58.297 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 4613 21:46:58.297 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4614 21:46:58.297 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4615 21:46:58.297 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4616 21:46:58.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4617 21:46:58.297 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4618 21:46:58.297 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4619 21:46:58.297 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4620 21:46:58.297 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4621 21:46:58.297 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4622 21:46:58.297 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4623 21:46:58.297 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4624 21:46:58.297 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 4625 21:46:58.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4626 21:46:58.297 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4627 21:46:58.297 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4628 21:46:58.297 0.00020622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4629 21:46:58.297 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4630 21:46:58.297 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4631 21:46:58.297 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4632 21:46:58.297 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4633 21:46:58.297 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4634 21:46:58.297 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4635 21:46:58.297 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4636 21:46:58.297 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 4637 21:46:58.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4638 21:46:58.297 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4639 21:46:58.297 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 4640 21:46:58.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4641 21:46:58.297 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4642 21:46:58.297 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4643 21:46:58.297 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4644 21:46:58.297 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4645 21:46:58.297 0.00007704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4646 21:46:58.297 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4647 21:46:58.297 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4648 21:46:58.297 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4649 21:46:58.297 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4650 21:46:58.297 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4652 21:46:58.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4653 21:46:58.297 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4654 21:46:58.297 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4655 21:46:58.297 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4656 21:46:58.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4657 21:46:58.297 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4658 21:46:58.297 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4659 21:46:58.297 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4660 21:46:58.297 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4661 21:46:58.297 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4662 21:46:58.297 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4663 21:46:58.297 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4664 21:46:58.297 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4665 21:46:58.297 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4666 21:46:58.297 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4667 21:46:58.297 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4668 21:46:58.297 0.02853295 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4670 21:46:58.328 0.01351783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4671 21:46:58.328 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4672 21:46:58.344 0.00034173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4673 21:46:58.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4674 21:46:58.344 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4675 21:46:58.344 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4676 21:46:58.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4677 21:46:58.344 0.00022716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4678 21:46:58.344 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 4679 21:46:58.344 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4680 21:46:58.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4681 21:46:58.344 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4682 21:46:58.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4683 21:46:58.344 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4684 21:46:58.344 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4685 21:46:58.344 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4686 21:46:58.344 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4687 21:46:58.344 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4688 21:46:58.344 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4689 21:46:58.344 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4690 21:46:58.344 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4691 21:46:58.344 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4692 21:46:58.344 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4693 21:46:58.344 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4694 21:46:58.344 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4695 21:46:58.344 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4696 21:46:58.344 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4697 21:46:58.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4698 21:46:58.344 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 4699 21:46:58.344 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4700 21:46:58.344 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4703 21:46:58.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4704 21:46:58.344 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4705 21:46:58.344 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4706 21:46:58.344 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4707 21:46:58.344 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4708 21:46:58.344 0.00032277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4709 21:46:58.344 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4710 21:46:58.344 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4711 21:46:58.344 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4712 21:46:58.344 0.00027891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4713 21:46:58.344 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4714 21:46:58.344 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4715 21:46:58.344 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4716 21:46:58.344 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4717 21:46:58.344 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4718 21:46:58.344 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4719 21:46:58.344 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4720 21:46:58.344 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4721 21:46:58.344 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4722 21:46:58.344 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4723 21:46:58.344 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4724 21:46:58.344 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4725 21:46:58.344 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4726 21:46:58.344 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4727 21:46:58.344 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4728 21:46:58.344 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4729 21:46:58.344 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4730 21:46:58.344 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4731 21:46:58.344 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4732 21:46:58.344 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4733 21:46:58.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4734 21:46:58.344 0.02898609 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4735 21:46:58.375 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4736 21:46:58.375 0.01173847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4737 21:46:58.375 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4738 21:46:58.391 0.00033343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4739 21:46:58.391 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4740 21:46:58.391 0.00040770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4741 21:46:58.391 0.00035911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4742 21:46:58.391 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4743 21:46:58.391 0.00033106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4744 21:46:58.391 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 4745 21:46:58.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4746 21:46:58.391 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4747 21:46:58.391 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 4748 21:46:58.391 0.00024849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4749 21:46:58.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4750 21:46:58.391 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4751 21:46:58.391 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4752 21:46:58.391 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4753 21:46:58.391 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4754 21:46:58.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4755 21:46:58.391 0.00026588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4756 21:46:58.391 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4758 21:46:58.391 0.00034765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4759 21:46:58.391 0.00039704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 4760 21:46:58.391 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4761 21:46:58.391 0.00031131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4762 21:46:58.391 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4763 21:46:58.391 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4764 21:46:58.391 0.00028444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4765 21:46:58.391 0.00033896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4766 21:46:58.391 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4767 21:46:58.391 0.00036306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4768 21:46:58.391 0.00037491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4769 21:46:58.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4770 21:46:58.391 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4771 21:46:58.391 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 4772 21:46:58.391 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4773 21:46:58.391 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4774 21:46:58.391 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4775 21:46:58.391 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4776 21:46:58.391 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4777 21:46:58.391 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4778 21:46:58.391 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4779 21:46:58.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4780 21:46:58.391 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4781 21:46:58.391 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4782 21:46:58.391 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4783 21:46:58.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4784 21:46:58.391 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4785 21:46:58.391 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4786 21:46:58.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4787 21:46:58.391 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4788 21:46:58.391 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4789 21:46:58.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4790 21:46:58.391 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4791 21:46:58.391 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4792 21:46:58.391 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4793 21:46:58.391 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4794 21:46:58.391 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4795 21:46:58.391 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4796 21:46:58.391 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4797 21:46:58.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4798 21:46:58.391 0.02498727 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4799 21:46:58.422 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4800 21:46:58.422 0.01465008 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4801 21:46:58.422 0.00007032 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4802 21:46:58.438 0.00039901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4803 21:46:58.438 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4804 21:46:58.438 0.00032672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4805 21:46:58.438 0.00030815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4806 21:46:58.438 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4807 21:46:58.438 0.00030775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4808 21:46:58.438 0.00025521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 4809 21:46:58.438 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 4810 21:46:58.438 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4811 21:46:58.438 0.00028049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4812 21:46:58.438 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4813 21:46:58.438 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4814 21:46:58.438 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4815 21:46:58.438 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4816 21:46:58.438 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4817 21:46:58.438 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4818 21:46:58.438 0.00034884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4819 21:46:58.438 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4820 21:46:58.438 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4821 21:46:58.438 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4822 21:46:58.438 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4823 21:46:58.438 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4824 21:46:58.438 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4825 21:46:58.438 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4826 21:46:58.438 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4827 21:46:58.438 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 4828 21:46:58.438 0.00028168 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4829 21:46:58.438 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4830 21:46:58.438 0.00039190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 4831 21:46:58.438 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4832 21:46:58.438 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4833 21:46:58.438 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4834 21:46:58.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4835 21:46:58.438 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4836 21:46:58.438 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4837 21:46:58.438 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4838 21:46:58.438 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4839 21:46:58.438 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4840 21:46:58.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4841 21:46:58.438 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4842 21:46:58.438 0.00009560 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4843 21:46:58.438 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4844 21:46:58.438 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4845 21:46:58.438 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4846 21:46:58.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4847 21:46:58.438 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4848 21:46:58.438 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4849 21:46:58.438 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4850 21:46:58.438 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4851 21:46:58.438 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4852 21:46:58.438 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4853 21:46:58.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4854 21:46:58.438 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4855 21:46:58.438 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4856 21:46:58.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4857 21:46:58.438 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4858 21:46:58.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4859 21:46:58.438 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4860 21:46:58.438 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4861 21:46:58.438 0.00008375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4862 21:46:58.438 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4863 21:46:58.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4864 21:46:58.438 0.02665008 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4865 21:46:58.469 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4866 21:46:58.469 0.01356998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4867 21:46:58.469 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4868 21:46:58.485 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4869 21:46:58.485 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4870 21:46:58.485 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4871 21:46:58.485 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4872 21:46:58.485 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 4873 21:46:58.485 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4874 21:46:58.485 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4875 21:46:58.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4876 21:46:58.485 0.00034686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4877 21:46:58.485 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 4878 21:46:58.485 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4879 21:46:58.485 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4880 21:46:58.485 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4881 21:46:58.485 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4882 21:46:58.485 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4883 21:46:58.485 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4884 21:46:58.485 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 4885 21:46:58.485 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4886 21:46:58.485 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4887 21:46:58.485 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 4888 21:46:58.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4889 21:46:58.485 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4890 21:46:58.485 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4891 21:46:58.485 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4892 21:46:58.485 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4893 21:46:58.485 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4894 21:46:58.485 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4895 21:46:58.485 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4896 21:46:58.485 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 4897 21:46:58.485 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4898 21:46:58.485 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4899 21:46:58.485 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 4900 21:46:58.485 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4901 21:46:58.485 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4902 21:46:58.485 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 4903 21:46:58.485 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4904 21:46:58.485 0.00034252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4905 21:46:58.485 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4906 21:46:58.485 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4907 21:46:58.485 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4908 21:46:58.485 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4909 21:46:58.485 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 4910 21:46:58.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4911 21:46:58.485 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4915 21:46:58.485 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4916 21:46:58.485 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4917 21:46:58.485 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4918 21:46:58.485 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4919 21:46:58.485 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 4920 21:46:58.485 0.00020583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4921 21:46:58.485 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4922 21:46:58.485 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4923 21:46:58.485 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 4924 21:46:58.485 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4925 21:46:58.485 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4926 21:46:58.485 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4927 21:46:58.485 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4928 21:46:58.485 0.02826431 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4929 21:46:58.516 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4930 21:46:58.516 0.01241719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4931 21:46:58.516 0.00003200 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4932 21:46:58.532 0.00030894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4933 21:46:58.532 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4934 21:46:58.532 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4935 21:46:58.532 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 4936 21:46:58.532 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4937 21:46:58.532 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4938 21:46:58.532 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 4939 21:46:58.532 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4940 21:46:58.532 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4941 21:46:58.532 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 4942 21:46:58.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4943 21:46:58.532 0.00042509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4944 21:46:58.532 0.00032909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 4945 21:46:58.532 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4946 21:46:58.532 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 4947 21:46:58.532 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4948 21:46:58.532 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 4949 21:46:58.532 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4950 21:46:58.532 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4951 21:46:58.532 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4952 21:46:58.532 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4953 21:46:58.532 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 4954 21:46:58.532 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4955 21:46:58.532 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4956 21:46:58.532 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4957 21:46:58.532 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4958 21:46:58.532 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4959 21:46:58.532 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 4960 21:46:58.532 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 4961 21:46:58.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4962 21:46:58.532 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4963 21:46:58.532 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4964 21:46:58.532 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 4965 21:46:58.532 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4966 21:46:58.532 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4967 21:46:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4968 21:46:58.532 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 4972 21:46:58.532 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4973 21:46:58.532 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4974 21:46:58.532 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4975 21:46:58.532 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4976 21:46:58.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4977 21:46:58.532 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4978 21:46:58.532 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4979 21:46:58.532 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4980 21:46:58.532 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4981 21:46:58.532 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4982 21:46:58.532 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4983 21:46:58.532 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4984 21:46:58.532 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4985 21:46:58.532 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4986 21:46:58.532 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4987 21:46:58.532 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4988 21:46:58.532 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4989 21:46:58.532 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4990 21:46:58.532 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4991 21:46:58.532 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 4992 21:46:58.532 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4993 21:46:58.532 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4995 21:46:58.563 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 4996 21:46:58.563 0.01307892 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 4997 21:46:58.563 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 4998 21:46:58.578 0.00034844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 4999 21:46:58.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5000 21:46:58.578 0.00033896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5001 21:46:58.578 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5002 21:46:58.578 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5003 21:46:58.578 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5004 21:46:58.578 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5005 21:46:58.578 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5006 21:46:58.578 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5007 21:46:58.578 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5008 21:46:58.578 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5009 21:46:58.578 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5010 21:46:58.578 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5011 21:46:58.578 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5012 21:46:58.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5013 21:46:58.578 0.00023032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5014 21:46:58.578 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5015 21:46:58.578 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5016 21:46:58.578 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5018 21:46:58.578 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5019 21:46:58.578 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 5020 21:46:58.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5021 21:46:58.578 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5022 21:46:58.578 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5023 21:46:58.578 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5024 21:46:58.578 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5025 21:46:58.578 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5026 21:46:58.578 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5027 21:46:58.578 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5028 21:46:58.578 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5029 21:46:58.578 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 5030 21:46:58.578 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5031 21:46:58.578 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5032 21:46:58.578 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5033 21:46:58.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5034 21:46:58.578 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5035 21:46:58.578 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5036 21:46:58.578 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5037 21:46:58.578 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5038 21:46:58.578 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5039 21:46:58.578 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5040 21:46:58.578 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5041 21:46:58.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5042 21:46:58.578 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5043 21:46:58.578 0.00027299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5044 21:46:58.578 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5045 21:46:58.578 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5046 21:46:58.578 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5047 21:46:58.578 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5048 21:46:58.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5049 21:46:58.578 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5050 21:46:58.578 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5051 21:46:58.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5052 21:46:58.578 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5053 21:46:58.578 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5054 21:46:58.578 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5055 21:46:58.578 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5056 21:46:58.578 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5057 21:46:58.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5058 21:46:58.578 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5059 21:46:58.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5060 21:46:58.578 0.02746391 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5061 21:46:58.610 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5062 21:46:58.610 0.01329936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5063 21:46:58.610 0.00002449 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5064 21:46:58.625 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5065 21:46:58.625 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5066 21:46:58.625 0.00024770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5067 21:46:58.625 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5068 21:46:58.625 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5069 21:46:58.625 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5070 21:46:58.625 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5071 21:46:58.625 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5072 21:46:58.625 0.00030064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5073 21:46:58.625 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5074 21:46:58.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5075 21:46:58.625 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5076 21:46:58.625 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5077 21:46:58.625 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 4C 5078 21:46:58.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5079 21:46:58.625 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5082 21:46:58.625 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5083 21:46:58.625 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5084 21:46:58.625 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5085 21:46:58.625 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5086 21:46:58.625 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5087 21:46:58.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5088 21:46:58.625 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5089 21:46:58.625 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 5090 21:46:58.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5091 21:46:58.625 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5092 21:46:58.625 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 5093 21:46:58.625 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5094 21:46:58.625 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5095 21:46:58.625 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5096 21:46:58.625 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5097 21:46:58.625 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5098 21:46:58.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5099 21:46:58.625 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5100 21:46:58.625 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5101 21:46:58.625 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5102 21:46:58.625 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5103 21:46:58.625 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5104 21:46:58.625 0.00009126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5105 21:46:58.625 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5106 21:46:58.625 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5107 21:46:58.625 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5108 21:46:58.625 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5109 21:46:58.625 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5110 21:46:58.625 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5111 21:46:58.625 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5112 21:46:58.625 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5113 21:46:58.625 0.00007941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5114 21:46:58.625 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5115 21:46:58.625 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5116 21:46:58.625 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 5117 21:46:58.625 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5118 21:46:58.625 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5121 21:46:58.625 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5122 21:46:58.625 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5123 21:46:58.625 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5124 21:46:58.625 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5125 21:46:58.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5126 21:46:58.625 0.02869611 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5127 21:46:58.657 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5128 21:46:58.657 0.01351862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5129 21:46:58.657 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5130 21:46:58.673 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5131 21:46:58.673 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5132 21:46:58.673 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5133 21:46:58.673 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5134 21:46:58.673 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5135 21:46:58.673 0.00024573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5136 21:46:58.673 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5137 21:46:58.673 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5138 21:46:58.673 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5139 21:46:58.673 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5140 21:46:58.673 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5141 21:46:58.673 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5142 21:46:58.673 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5143 21:46:58.673 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5144 21:46:58.673 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5145 21:46:58.673 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5146 21:46:58.673 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 5147 21:46:58.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5148 21:46:58.673 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5149 21:46:58.673 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 5150 21:46:58.673 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5151 21:46:58.673 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5152 21:46:58.673 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5153 21:46:58.673 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5154 21:46:58.673 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5155 21:46:58.673 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5156 21:46:58.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5157 21:46:58.673 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5158 21:46:58.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5159 21:46:58.673 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5160 21:46:58.673 0.00008652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 5161 21:46:58.673 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5162 21:46:58.673 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5163 21:46:58.673 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 5164 21:46:58.673 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5165 21:46:58.673 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5166 21:46:58.673 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5167 21:46:58.673 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5168 21:46:58.673 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5169 21:46:58.673 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5171 21:46:58.673 0.00029985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5172 21:46:58.673 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5173 21:46:58.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5174 21:46:58.673 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5175 21:46:58.673 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5176 21:46:58.673 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5177 21:46:58.673 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5178 21:46:58.673 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5179 21:46:58.673 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5180 21:46:58.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5181 21:46:58.673 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5182 21:46:58.673 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5183 21:46:58.673 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5184 21:46:58.673 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5185 21:46:58.673 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5186 21:46:58.673 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5187 21:46:58.673 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5188 21:46:58.673 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5189 21:46:58.673 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5190 21:46:58.673 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5191 21:46:58.673 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5192 21:46:58.673 0.02735606 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5193 21:46:58.704 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5194 21:46:58.704 0.01319388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5195 21:46:58.704 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5196 21:46:58.719 0.00031763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5197 21:46:58.719 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5198 21:46:58.719 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5199 21:46:58.719 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5200 21:46:58.719 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5201 21:46:58.719 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5202 21:46:58.719 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5203 21:46:58.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5204 21:46:58.719 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5205 21:46:58.719 0.00030341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5206 21:46:58.719 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5207 21:46:58.719 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5208 21:46:58.719 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5209 21:46:58.719 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5210 21:46:58.719 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5211 21:46:58.719 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 5212 21:46:58.719 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5213 21:46:58.719 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5214 21:46:58.719 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5215 21:46:58.719 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5216 21:46:58.719 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5217 21:46:58.719 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5218 21:46:58.719 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5219 21:46:58.719 0.00029195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5220 21:46:58.719 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5221 21:46:58.719 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 5222 21:46:58.719 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5223 21:46:58.719 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5224 21:46:58.719 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 5225 21:46:58.719 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5226 21:46:58.719 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5227 21:46:58.719 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5228 21:46:58.719 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5230 21:46:58.719 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5231 21:46:58.719 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5232 21:46:58.719 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5233 21:46:58.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5234 21:46:58.719 0.00020425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5235 21:46:58.719 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5236 21:46:58.719 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5237 21:46:58.719 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5238 21:46:58.719 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5239 21:46:58.719 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5240 21:46:58.719 0.00031802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5241 21:46:58.719 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5242 21:46:58.719 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5243 21:46:58.719 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5244 21:46:58.719 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5245 21:46:58.719 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5246 21:46:58.719 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5247 21:46:58.719 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5248 21:46:58.719 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5249 21:46:58.719 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5250 21:46:58.719 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5251 21:46:58.719 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5252 21:46:58.719 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5253 21:46:58.719 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5254 21:46:58.719 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5255 21:46:58.719 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5256 21:46:58.719 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5257 21:46:58.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5258 21:46:58.719 0.02694283 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5259 21:46:58.751 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5260 21:46:58.751 0.01432455 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5261 21:46:58.751 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5262 21:46:58.766 0.00029906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5263 21:46:58.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5264 21:46:58.766 0.00032000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5265 21:46:58.766 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5266 21:46:58.766 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5267 21:46:58.766 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5268 21:46:58.766 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5269 21:46:58.766 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5270 21:46:58.766 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 5271 21:46:58.766 0.00024257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5272 21:46:58.766 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5273 21:46:58.766 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5274 21:46:58.766 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5275 21:46:58.766 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5276 21:46:58.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5277 21:46:58.766 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5278 21:46:58.766 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5279 21:46:58.766 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5280 21:46:58.766 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5281 21:46:58.766 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5282 21:46:58.766 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5283 21:46:58.766 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5284 21:46:58.766 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5285 21:46:58.766 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5286 21:46:58.766 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5287 21:46:58.766 0.00031684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5288 21:46:58.766 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5289 21:46:58.766 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5290 21:46:58.766 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5291 21:46:58.766 0.00039269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5292 21:46:58.766 0.00032869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5293 21:46:58.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5294 21:46:58.766 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5295 21:46:58.766 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5296 21:46:58.766 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5297 21:46:58.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5298 21:46:58.766 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5299 21:46:58.766 0.00030736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5300 21:46:58.766 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5301 21:46:58.766 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5302 21:46:58.766 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5303 21:46:58.766 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5304 21:46:58.766 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5305 21:46:58.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5306 21:46:58.766 0.00028247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5307 21:46:58.766 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5308 21:46:58.766 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5309 21:46:58.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5310 21:46:58.766 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5311 21:46:58.766 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5312 21:46:58.766 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5313 21:46:58.766 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5314 21:46:58.766 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5315 21:46:58.766 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5316 21:46:58.766 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5317 21:46:58.766 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5318 21:46:58.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5319 21:46:58.766 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5322 21:46:58.766 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5323 21:46:58.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5324 21:46:58.766 0.02558460 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5325 21:46:58.797 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5326 21:46:58.797 0.01271665 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5327 21:46:58.797 0.00001778 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5328 21:46:58.812 0.00030420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5329 21:46:58.812 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5330 21:46:58.812 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5331 21:46:58.812 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5332 21:46:58.812 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5333 21:46:58.812 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5334 21:46:58.812 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5335 21:46:58.812 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 5336 21:46:58.812 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5337 21:46:58.812 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5338 21:46:58.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5339 21:46:58.812 0.00034528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5340 21:46:58.812 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5341 21:46:58.812 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 5342 21:46:58.812 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5343 21:46:58.812 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5344 21:46:58.812 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5345 21:46:58.812 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5346 21:46:58.812 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5347 21:46:58.812 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5348 21:46:58.812 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5349 21:46:58.812 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5350 21:46:58.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5351 21:46:58.812 0.00026667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5352 21:46:58.812 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5353 21:46:58.812 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 5354 21:46:58.812 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5355 21:46:58.812 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5356 21:46:58.812 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 5357 21:46:58.812 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5358 21:46:58.812 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5359 21:46:58.812 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5360 21:46:58.812 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5361 21:46:58.812 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5362 21:46:58.812 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5363 21:46:58.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5364 21:46:58.812 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5365 21:46:58.812 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5366 21:46:58.812 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5367 21:46:58.812 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5368 21:46:58.812 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5369 21:46:58.812 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5370 21:46:58.812 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5371 21:46:58.812 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5372 21:46:58.812 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5373 21:46:58.812 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5374 21:46:58.812 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5375 21:46:58.812 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5376 21:46:58.812 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5377 21:46:58.812 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5378 21:46:58.812 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5379 21:46:58.812 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5380 21:46:58.812 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5381 21:46:58.812 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5382 21:46:58.812 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5383 21:46:58.812 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5384 21:46:58.812 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5385 21:46:58.812 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5386 21:46:58.812 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5387 21:46:58.812 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5388 21:46:58.812 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5389 21:46:58.812 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5390 21:46:58.812 0.02661255 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5391 21:46:58.844 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5392 21:46:58.844 0.01474608 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5393 21:46:58.844 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5394 21:46:58.859 0.00038953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5395 21:46:58.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5396 21:46:58.859 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5397 21:46:58.859 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5398 21:46:58.859 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5399 21:46:58.859 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5400 21:46:58.859 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5401 21:46:58.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5402 21:46:58.859 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5403 21:46:58.859 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 5404 21:46:58.859 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5405 21:46:58.859 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5406 21:46:58.859 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5407 21:46:58.859 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5408 21:46:58.859 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5409 21:46:58.859 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5410 21:46:58.859 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 5411 21:46:58.859 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5412 21:46:58.859 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5413 21:46:58.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5414 21:46:58.859 0.00032672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5415 21:46:58.859 0.00029314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5416 21:46:58.859 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5417 21:46:58.859 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5418 21:46:58.859 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5419 21:46:58.859 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5420 21:46:58.859 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5421 21:46:58.859 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5422 21:46:58.859 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 5423 21:46:58.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5424 21:46:58.859 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5425 21:46:58.859 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5426 21:46:58.859 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5427 21:46:58.859 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5428 21:46:58.859 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5429 21:46:58.859 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5430 21:46:58.859 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5431 21:46:58.859 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5432 21:46:58.859 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5433 21:46:58.859 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5434 21:46:58.859 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5435 21:46:58.859 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5436 21:46:58.859 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5437 21:46:58.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5438 21:46:58.859 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5440 21:46:58.859 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5441 21:46:58.859 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5442 21:46:58.859 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5446 21:46:58.859 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5447 21:46:58.859 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5448 21:46:58.859 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5449 21:46:58.859 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5450 21:46:58.859 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5451 21:46:58.859 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5452 21:46:58.859 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5453 21:46:58.859 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5454 21:46:58.859 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5455 21:46:58.859 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5456 21:46:58.859 0.02681285 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5457 21:46:58.891 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5458 21:46:58.891 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5459 21:46:58.891 0.01420919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5460 21:46:58.906 0.00031210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5461 21:46:58.906 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5462 21:46:58.906 0.00037333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5463 21:46:58.906 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5464 21:46:58.906 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5465 21:46:58.906 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5466 21:46:58.906 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5467 21:46:58.906 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5468 21:46:58.906 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5469 21:46:58.906 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 5470 21:46:58.906 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5471 21:46:58.906 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5472 21:46:58.906 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5473 21:46:58.906 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 5474 21:46:58.906 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5475 21:46:58.906 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5476 21:46:58.906 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5477 21:46:58.906 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5478 21:46:58.906 0.00028840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5479 21:46:58.906 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5480 21:46:58.906 0.00028049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5481 21:46:58.906 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5482 21:46:58.906 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5483 21:46:58.906 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 5484 21:46:58.906 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5485 21:46:58.906 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5486 21:46:58.906 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 5487 21:46:58.906 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5488 21:46:58.906 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5489 21:46:58.906 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5490 21:46:58.906 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5491 21:46:58.906 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5492 21:46:58.906 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5493 21:46:58.906 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5494 21:46:58.906 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5495 21:46:58.906 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5496 21:46:58.906 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5497 21:46:58.906 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5498 21:46:58.906 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5499 21:46:58.906 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5500 21:46:58.906 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5501 21:46:58.906 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5502 21:46:58.906 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5503 21:46:58.906 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5504 21:46:58.906 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5505 21:46:58.906 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5506 21:46:58.906 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5507 21:46:58.906 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5508 21:46:58.906 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5509 21:46:58.906 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5510 21:46:58.906 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5511 21:46:58.906 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5512 21:46:58.906 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5513 21:46:58.906 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5514 21:46:58.906 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5515 21:46:58.906 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5516 21:46:58.906 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5517 21:46:58.906 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5518 21:46:58.906 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5519 21:46:58.906 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5520 21:46:58.906 0.02765315 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5521 21:46:58.938 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5522 21:46:58.938 0.01319665 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5523 21:46:58.938 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5524 21:46:58.953 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5525 21:46:58.953 0.00040533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5526 21:46:58.953 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5527 21:46:58.953 0.00030341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5528 21:46:58.953 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 02 5529 21:46:58.953 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5530 21:46:58.953 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5534 21:46:58.953 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5535 21:46:58.953 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5536 21:46:58.953 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5537 21:46:58.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5538 21:46:58.953 0.00041640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5539 21:46:58.953 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5540 21:46:58.953 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5541 21:46:58.953 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5542 21:46:58.953 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5543 21:46:58.953 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5544 21:46:58.953 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5545 21:46:58.953 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5546 21:46:58.953 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5547 21:46:58.953 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5548 21:46:58.953 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5549 21:46:58.953 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5550 21:46:58.953 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5551 21:46:58.953 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5552 21:46:58.953 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5553 21:46:58.953 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5554 21:46:58.953 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5555 21:46:58.953 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5556 21:46:58.953 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5557 21:46:58.953 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5558 21:46:58.953 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5559 21:46:58.953 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5560 21:46:58.953 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5561 21:46:58.953 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5562 21:46:58.953 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5563 21:46:58.953 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5564 21:46:58.953 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5565 21:46:58.953 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5566 21:46:58.953 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5567 21:46:58.953 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5568 21:46:58.953 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5569 21:46:58.953 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5570 21:46:58.953 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5571 21:46:58.953 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5572 21:46:58.953 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5573 21:46:58.953 0.00008652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5574 21:46:58.953 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5575 21:46:58.953 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5576 21:46:58.953 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5577 21:46:58.953 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5578 21:46:58.953 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5579 21:46:58.953 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5580 21:46:58.953 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5581 21:46:58.953 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5582 21:46:58.953 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5583 21:46:58.953 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5584 21:46:58.953 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5585 21:46:58.953 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5586 21:46:58.953 0.02821176 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5587 21:46:58.985 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5588 21:46:58.985 0.01207349 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5589 21:46:58.985 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5590 21:46:59.001 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5591 21:46:59.001 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5592 21:46:59.001 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5593 21:46:59.001 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5594 21:46:59.001 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5595 21:46:59.001 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5596 21:46:59.001 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5597 21:46:59.001 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5598 21:46:59.001 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5599 21:46:59.001 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 5600 21:46:59.001 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5601 21:46:59.001 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5602 21:46:59.001 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5603 21:46:59.001 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5604 21:46:59.001 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 5605 21:46:59.001 0.00024889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5606 21:46:59.001 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5607 21:46:59.001 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5608 21:46:59.001 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5609 21:46:59.001 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5610 21:46:59.001 0.00026351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5611 21:46:59.001 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5612 21:46:59.001 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5613 21:46:59.001 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5614 21:46:59.001 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5615 21:46:59.001 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 5616 21:46:59.001 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5617 21:46:59.001 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5618 21:46:59.001 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 30 5619 21:46:59.001 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5620 21:46:59.001 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5623 21:46:59.001 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5624 21:46:59.001 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5625 21:46:59.001 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5626 21:46:59.001 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5627 21:46:59.001 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 5628 21:46:59.001 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5629 21:46:59.001 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5631 21:46:59.001 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5632 21:46:59.001 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5633 21:46:59.001 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5634 21:46:59.001 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5635 21:46:59.001 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5636 21:46:59.001 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5637 21:46:59.001 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5638 21:46:59.001 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5639 21:46:59.001 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5640 21:46:59.001 0.00025561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5641 21:46:59.001 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5642 21:46:59.001 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5643 21:46:59.001 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5644 21:46:59.001 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5645 21:46:59.001 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5646 21:46:59.001 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5647 21:46:59.001 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5648 21:46:59.001 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5649 21:46:59.001 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5650 21:46:59.001 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5651 21:46:59.001 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5652 21:46:59.001 0.02683458 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5653 21:46:59.032 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5654 21:46:59.032 0.01474727 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5655 21:46:59.032 0.00004820 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5656 21:46:59.047 0.00034923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5657 21:46:59.047 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5658 21:46:59.047 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5659 21:46:59.047 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5660 21:46:59.047 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5661 21:46:59.047 0.00044523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5662 21:46:59.047 0.00035753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5663 21:46:59.047 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 5664 21:46:59.047 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5665 21:46:59.047 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5666 21:46:59.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5667 21:46:59.047 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5668 21:46:59.047 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5669 21:46:59.047 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5670 21:46:59.047 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5671 21:46:59.047 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5672 21:46:59.047 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5673 21:46:59.047 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5674 21:46:59.047 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 5675 21:46:59.047 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 40 5678 21:46:59.047 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5679 21:46:59.047 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5680 21:46:59.047 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 43 5682 21:46:59.047 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5683 21:46:59.047 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5684 21:46:59.047 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5685 21:46:59.047 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 5686 21:46:59.047 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5687 21:46:59.047 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5688 21:46:59.047 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5689 21:46:59.047 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5690 21:46:59.047 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5693 21:46:59.047 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5694 21:46:59.047 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5695 21:46:59.047 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5696 21:46:59.047 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5697 21:46:59.047 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5698 21:46:59.047 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5701 21:46:59.047 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5702 21:46:59.047 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5703 21:46:59.047 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5704 21:46:59.047 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5705 21:46:59.047 0.00026272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5706 21:46:59.047 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5707 21:46:59.047 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5708 21:46:59.047 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5709 21:46:59.047 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5710 21:46:59.047 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5711 21:46:59.047 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5712 21:46:59.047 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5713 21:46:59.047 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5714 21:46:59.047 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5715 21:46:59.047 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5716 21:46:59.047 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5717 21:46:59.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5718 21:46:59.047 0.02609779 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5719 21:46:59.079 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5720 21:46:59.079 0.01317650 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5721 21:46:59.079 0.00000356 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5722 21:46:59.094 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5723 21:46:59.094 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5724 21:46:59.094 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5725 21:46:59.094 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5726 21:46:59.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5727 21:46:59.094 0.00038044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5728 21:46:59.094 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5729 21:46:59.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5730 21:46:59.094 0.00034963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5731 21:46:59.094 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 5732 21:46:59.094 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5733 21:46:59.094 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5734 21:46:59.094 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5735 21:46:59.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5736 21:46:59.094 0.00033817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5737 21:46:59.094 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 5738 21:46:59.094 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5739 21:46:59.094 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5740 21:46:59.094 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5741 21:46:59.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5742 21:46:59.094 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 5743 21:46:59.094 0.00029551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5744 21:46:59.094 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5745 21:46:59.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5746 21:46:59.094 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5747 21:46:59.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5748 21:46:59.094 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5749 21:46:59.094 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 5750 21:46:59.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5751 21:46:59.094 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5752 21:46:59.094 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 5753 21:46:59.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5754 21:46:59.094 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5755 21:46:59.094 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5756 21:46:59.094 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5757 21:46:59.094 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5758 21:46:59.094 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5759 21:46:59.094 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5760 21:46:59.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5761 21:46:59.094 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5762 21:46:59.094 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5763 21:46:59.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5764 21:46:59.094 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5765 21:46:59.094 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5766 21:46:59.094 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5767 21:46:59.094 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5768 21:46:59.094 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5769 21:46:59.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5770 21:46:59.094 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5771 21:46:59.094 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5772 21:46:59.094 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5773 21:46:59.094 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5774 21:46:59.094 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5775 21:46:59.094 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5776 21:46:59.094 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5777 21:46:59.094 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5778 21:46:59.094 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5779 21:46:59.094 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5780 21:46:59.094 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5781 21:46:59.094 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5782 21:46:59.094 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5783 21:46:59.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5784 21:46:59.094 0.02881779 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5785 21:46:59.125 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5786 21:46:59.125 0.01221136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5787 21:46:59.125 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5788 21:46:59.141 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5789 21:46:59.141 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5790 21:46:59.141 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5791 21:46:59.141 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5792 21:46:59.141 0.00110933 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5793 21:46:59.141 0.00125274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5794 21:46:59.141 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5795 21:46:59.141 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5796 21:46:59.141 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 5797 21:46:59.141 0.00028681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5798 21:46:59.141 0.00035121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5799 21:46:59.141 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5800 21:46:59.141 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5801 21:46:59.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5802 21:46:59.141 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5803 21:46:59.141 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5804 21:46:59.141 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5805 21:46:59.141 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5806 21:46:59.141 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5807 21:46:59.141 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 5808 21:46:59.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5809 21:46:59.141 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5810 21:46:59.141 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5811 21:46:59.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5812 21:46:59.141 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5813 21:46:59.141 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5814 21:46:59.141 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5815 21:46:59.141 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5816 21:46:59.141 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5817 21:46:59.141 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5818 21:46:59.141 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5819 21:46:59.141 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5820 21:46:59.141 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 5821 21:46:59.141 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5822 21:46:59.141 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5823 21:46:59.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5824 21:46:59.141 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5825 21:46:59.141 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5826 21:46:59.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5827 21:46:59.141 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5828 21:46:59.141 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5830 21:46:59.141 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5831 21:46:59.141 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5832 21:46:59.141 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5833 21:46:59.141 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5834 21:46:59.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5835 21:46:59.141 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5836 21:46:59.141 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5837 21:46:59.141 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5838 21:46:59.141 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5839 21:46:59.141 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5840 21:46:59.141 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5841 21:46:59.141 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5842 21:46:59.141 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5843 21:46:59.141 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5844 21:46:59.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5845 21:46:59.141 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5846 21:46:59.141 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5847 21:46:59.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5848 21:46:59.141 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5849 21:46:59.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5850 21:46:59.141 0.02582678 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5851 21:46:59.172 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5852 21:46:59.172 0.01433601 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5853 21:46:59.172 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5854 21:46:59.188 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5855 21:46:59.188 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5856 21:46:59.188 0.00042509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5857 21:46:59.188 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5858 21:46:59.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5859 21:46:59.188 0.00032514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5860 21:46:59.188 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5861 21:46:59.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5862 21:46:59.188 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5863 21:46:59.188 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 5864 21:46:59.188 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5865 21:46:59.188 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5866 21:46:59.188 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5867 21:46:59.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5868 21:46:59.188 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 5869 21:46:59.188 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5870 21:46:59.188 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5871 21:46:59.188 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 5872 21:46:59.188 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5873 21:46:59.188 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 44 5874 21:46:59.188 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5875 21:46:59.188 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 5879 21:46:59.188 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5880 21:46:59.188 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5881 21:46:59.188 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 5882 21:46:59.188 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 5883 21:46:59.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5884 21:46:59.188 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5885 21:46:59.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5886 21:46:59.188 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5887 21:46:59.188 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5888 21:46:59.188 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5889 21:46:59.188 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5890 21:46:59.188 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5891 21:46:59.188 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5892 21:46:59.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5893 21:46:59.188 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5894 21:46:59.188 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5895 21:46:59.188 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5896 21:46:59.188 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5897 21:46:59.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5898 21:46:59.188 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5899 21:46:59.188 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5900 21:46:59.188 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5902 21:46:59.188 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5903 21:46:59.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5904 21:46:59.188 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5905 21:46:59.188 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5906 21:46:59.188 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5907 21:46:59.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5908 21:46:59.188 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5909 21:46:59.188 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5910 21:46:59.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5911 21:46:59.188 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5912 21:46:59.188 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 5913 21:46:59.188 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5914 21:46:59.188 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5915 21:46:59.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5916 21:46:59.188 0.02840455 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5917 21:46:59.219 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5918 21:46:59.219 0.02881581 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5919 21:46:59.219 0.00003081 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5920 21:46:59.250 0.00040178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5921 21:46:59.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5922 21:46:59.250 0.00129343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5923 21:46:59.250 0.00115161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5924 21:46:59.250 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5925 21:46:59.250 0.00041047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5926 21:46:59.250 0.00037175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 5927 21:46:59.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5928 21:46:59.250 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5929 21:46:59.250 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 5930 21:46:59.250 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5931 21:46:59.250 0.00038874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5932 21:46:59.250 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5933 21:46:59.250 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5934 21:46:59.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5935 21:46:59.250 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5936 21:46:59.250 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 5937 21:46:59.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5938 21:46:59.250 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5939 21:46:59.250 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5940 21:46:59.250 0.00033225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5941 21:46:59.250 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 5942 21:46:59.250 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5943 21:46:59.250 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5944 21:46:59.250 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5945 21:46:59.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5946 21:46:59.250 0.00035358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5947 21:46:59.250 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5948 21:46:59.250 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5949 21:46:59.250 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 5950 21:46:59.250 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5951 21:46:59.250 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5952 21:46:59.250 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5953 21:46:59.250 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 5954 21:46:59.250 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 5955 21:46:59.250 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5956 21:46:59.250 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5957 21:46:59.250 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5958 21:46:59.250 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5959 21:46:59.250 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5960 21:46:59.250 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5961 21:46:59.250 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5962 21:46:59.250 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5963 21:46:59.250 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5964 21:46:59.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5965 21:46:59.250 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5966 21:46:59.250 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5967 21:46:59.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5968 21:46:59.250 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5969 21:46:59.250 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5970 21:46:59.250 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5971 21:46:59.250 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5972 21:46:59.250 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 5973 21:46:59.250 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5974 21:46:59.250 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5975 21:46:59.250 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5976 21:46:59.250 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5977 21:46:59.250 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 5978 21:46:59.250 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 5979 21:46:59.250 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5980 21:46:59.250 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5981 21:46:59.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5982 21:46:59.250 0.02590539 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5983 21:46:59.281 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5984 21:46:59.281 0.01320652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5985 21:46:59.281 0.00004148 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 5986 21:46:59.297 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 5987 21:46:59.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5988 21:46:59.297 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5989 21:46:59.297 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 5990 21:46:59.297 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 5991 21:46:59.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5992 21:46:59.297 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5993 21:46:59.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5994 21:46:59.297 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 5995 21:46:59.297 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5996 21:46:59.297 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 5997 21:46:59.297 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 5998 21:46:59.297 0.00029432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 5999 21:46:59.297 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6000 21:46:59.297 0.00035121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6001 21:46:59.297 0.00036701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6002 21:46:59.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6003 21:46:59.297 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6004 21:46:59.297 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6005 21:46:59.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6006 21:46:59.297 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 6007 21:46:59.297 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6008 21:46:59.297 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6009 21:46:59.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6010 21:46:59.297 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6011 21:46:59.297 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6012 21:46:59.297 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6013 21:46:59.297 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6014 21:46:59.297 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6015 21:46:59.297 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6016 21:46:59.297 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 6017 21:46:59.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6018 21:46:59.297 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6019 21:46:59.297 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6020 21:46:59.297 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6021 21:46:59.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6022 21:46:59.297 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6023 21:46:59.297 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6024 21:46:59.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6025 21:46:59.297 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6026 21:46:59.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6027 21:46:59.297 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6028 21:46:59.297 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6029 21:46:59.297 0.00034331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6030 21:46:59.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6031 21:46:59.297 0.00034054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6032 21:46:59.297 0.00033501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6033 21:46:59.297 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6034 21:46:59.297 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6035 21:46:59.297 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6036 21:46:59.297 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6037 21:46:59.297 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6038 21:46:59.297 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6039 21:46:59.297 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6040 21:46:59.297 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6041 21:46:59.297 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6042 21:46:59.297 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6043 21:46:59.297 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6044 21:46:59.297 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6045 21:46:59.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6046 21:46:59.297 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6047 21:46:59.297 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6048 21:46:59.297 0.02702776 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6049 21:46:59.328 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6050 21:46:59.328 0.01360633 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6051 21:46:59.328 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6052 21:46:59.344 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6053 21:46:59.344 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6054 21:46:59.344 0.00039941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6055 21:46:59.344 0.00035951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6056 21:46:59.344 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6057 21:46:59.344 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 6058 21:46:59.344 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6059 21:46:59.344 0.00028286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 6060 21:46:59.344 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6061 21:46:59.344 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6062 21:46:59.344 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6063 21:46:59.344 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6064 21:46:59.344 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6065 21:46:59.344 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6066 21:46:59.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6067 21:46:59.344 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6068 21:46:59.344 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6069 21:46:59.344 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6070 21:46:59.344 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6071 21:46:59.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6072 21:46:59.344 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 6073 21:46:59.344 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6074 21:46:59.344 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6075 21:46:59.344 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6076 21:46:59.344 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6077 21:46:59.344 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6078 21:46:59.344 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6079 21:46:59.344 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6080 21:46:59.344 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6081 21:46:59.344 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6082 21:46:59.344 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6083 21:46:59.344 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 6084 21:46:59.344 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6085 21:46:59.344 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6086 21:46:59.344 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6087 21:46:59.344 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 43 6088 21:46:59.344 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6092 21:46:59.344 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6093 21:46:59.344 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6094 21:46:59.344 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6095 21:46:59.344 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6096 21:46:59.344 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6097 21:46:59.344 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6098 21:46:59.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6099 21:46:59.344 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6100 21:46:59.344 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6101 21:46:59.344 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6102 21:46:59.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6103 21:46:59.344 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6104 21:46:59.344 0.00008691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6105 21:46:59.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6106 21:46:59.344 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6107 21:46:59.344 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6108 21:46:59.344 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6109 21:46:59.344 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6110 21:46:59.344 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6111 21:46:59.344 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6112 21:46:59.344 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6113 21:46:59.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6114 21:46:59.344 0.02606500 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6115 21:46:59.375 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6116 21:46:59.375 0.01475082 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6117 21:46:59.375 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6118 21:46:59.391 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6119 21:46:59.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6120 21:46:59.391 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6121 21:46:59.391 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6122 21:46:59.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6123 21:46:59.391 0.00055032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6124 21:46:59.391 0.00044444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 6125 21:46:59.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6126 21:46:59.391 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 6127 21:46:59.391 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6128 21:46:59.391 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6129 21:46:59.391 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6130 21:46:59.391 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6131 21:46:59.391 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6132 21:46:59.391 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6133 21:46:59.391 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6134 21:46:59.391 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6135 21:46:59.391 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6136 21:46:59.391 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6137 21:46:59.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6138 21:46:59.391 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 6139 21:46:59.391 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6140 21:46:59.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6141 21:46:59.391 0.00029077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6142 21:46:59.391 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6143 21:46:59.391 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6144 21:46:59.391 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6146 21:46:59.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6147 21:46:59.391 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6148 21:46:59.391 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6149 21:46:59.391 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6150 21:46:59.391 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6151 21:46:59.391 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6152 21:46:59.391 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6153 21:46:59.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6154 21:46:59.391 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6155 21:46:59.391 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6156 21:46:59.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6157 21:46:59.391 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6158 21:46:59.391 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6159 21:46:59.391 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6160 21:46:59.391 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6161 21:46:59.391 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6162 21:46:59.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6163 21:46:59.391 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6164 21:46:59.391 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6165 21:46:59.391 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6166 21:46:59.391 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6167 21:46:59.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6168 21:46:59.391 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6169 21:46:59.391 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6170 21:46:59.391 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6171 21:46:59.391 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6172 21:46:59.391 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6173 21:46:59.391 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6174 21:46:59.391 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6175 21:46:59.391 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6176 21:46:59.391 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6177 21:46:59.391 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6178 21:46:59.391 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6179 21:46:59.391 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6180 21:46:59.391 0.02710322 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6181 21:46:59.422 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6182 21:46:59.422 0.01406815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6183 21:46:59.422 0.00003279 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6184 21:46:59.438 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6185 21:46:59.438 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6186 21:46:59.438 0.00030183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6187 21:46:59.438 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6188 21:46:59.438 0.00084899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6189 21:46:59.438 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6190 21:46:59.438 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 6191 21:46:59.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6192 21:46:59.438 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 6193 21:46:59.438 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6194 21:46:59.438 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6195 21:46:59.438 0.00032830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6196 21:46:59.438 0.00027891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6197 21:46:59.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6198 21:46:59.438 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6199 21:46:59.438 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6200 21:46:59.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6201 21:46:59.438 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 6202 21:46:59.438 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6203 21:46:59.438 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 6204 21:46:59.438 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6205 21:46:59.438 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6206 21:46:59.438 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6207 21:46:59.438 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6208 21:46:59.438 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6209 21:46:59.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6210 21:46:59.438 0.00023111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6211 21:46:59.438 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6212 21:46:59.438 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 6213 21:46:59.438 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6214 21:46:59.438 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6215 21:46:59.438 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6216 21:46:59.438 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 6217 21:46:59.438 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6218 21:46:59.438 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6219 21:46:59.438 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6220 21:46:59.438 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6221 21:46:59.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6222 21:46:59.438 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6224 21:46:59.438 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6225 21:46:59.438 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6226 21:46:59.438 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6227 21:46:59.438 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6228 21:46:59.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6229 21:46:59.438 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6230 21:46:59.438 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6231 21:46:59.438 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6232 21:46:59.438 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6233 21:46:59.438 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6234 21:46:59.438 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6235 21:46:59.438 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6236 21:46:59.438 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6237 21:46:59.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6238 21:46:59.438 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6239 21:46:59.438 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6240 21:46:59.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6241 21:46:59.438 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6242 21:46:59.438 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6243 21:46:59.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6244 21:46:59.438 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6245 21:46:59.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6246 21:46:59.438 0.02750263 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6247 21:46:59.469 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6248 21:46:59.469 0.01364307 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6250 21:46:59.485 0.00054874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6251 21:46:59.485 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6252 21:46:59.485 0.00059062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6253 21:46:59.485 0.00033304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6254 21:46:59.485 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6255 21:46:59.485 0.00032909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6256 21:46:59.485 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 6257 21:46:59.485 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 6258 21:46:59.485 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6259 21:46:59.485 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6260 21:46:59.485 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6261 21:46:59.485 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6262 21:46:59.485 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6263 21:46:59.485 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6264 21:46:59.485 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6265 21:46:59.485 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6266 21:46:59.485 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6267 21:46:59.485 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6268 21:46:59.485 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6269 21:46:59.485 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 6270 21:46:59.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6271 21:46:59.485 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6272 21:46:59.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6273 21:46:59.485 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6274 21:46:59.485 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6275 21:46:59.485 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6276 21:46:59.485 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6277 21:46:59.485 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6278 21:46:59.485 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6279 21:46:59.485 0.00026785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6280 21:46:59.485 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 6281 21:46:59.485 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6282 21:46:59.485 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6283 21:46:59.485 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6284 21:46:59.485 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6285 21:46:59.485 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6286 21:46:59.485 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6287 21:46:59.485 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6288 21:46:59.485 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6289 21:46:59.485 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6290 21:46:59.485 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6291 21:46:59.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6292 21:46:59.485 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6293 21:46:59.485 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6294 21:46:59.485 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6296 21:46:59.485 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6297 21:46:59.485 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6298 21:46:59.485 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6299 21:46:59.485 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6300 21:46:59.485 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6301 21:46:59.485 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6302 21:46:59.485 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6303 21:46:59.485 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6304 21:46:59.485 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6305 21:46:59.485 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6306 21:46:59.485 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6307 21:46:59.485 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6308 21:46:59.485 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6309 21:46:59.485 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6310 21:46:59.485 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6311 21:46:59.485 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6312 21:46:59.485 0.02859932 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6313 21:46:59.516 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6314 21:46:59.516 0.01094993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6315 21:46:59.516 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6316 21:46:59.531 0.00030222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6317 21:46:59.531 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6318 21:46:59.531 0.00117689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6319 21:46:59.531 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6320 21:46:59.531 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6321 21:46:59.531 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6322 21:46:59.531 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 6323 21:46:59.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6324 21:46:59.531 0.00049501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6325 21:46:59.531 0.00042114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 6326 21:46:59.531 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6327 21:46:59.531 0.00048316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6328 21:46:59.531 0.00041205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6329 21:46:59.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6330 21:46:59.531 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6331 21:46:59.531 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6332 21:46:59.531 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6333 21:46:59.531 0.00025995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6334 21:46:59.531 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6335 21:46:59.531 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6336 21:46:59.531 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6337 21:46:59.531 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6338 21:46:59.531 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6339 21:46:59.531 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6340 21:46:59.531 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6341 21:46:59.531 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6342 21:46:59.531 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6343 21:46:59.531 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6344 21:46:59.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6345 21:46:59.531 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6346 21:46:59.531 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6347 21:46:59.531 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6348 21:46:59.531 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6349 21:46:59.531 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6350 21:46:59.531 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6351 21:46:59.531 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6352 21:46:59.531 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6353 21:46:59.531 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6354 21:46:59.531 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6355 21:46:59.531 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6356 21:46:59.531 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6357 21:46:59.531 0.00030815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6358 21:46:59.531 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6359 21:46:59.531 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6360 21:46:59.531 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6361 21:46:59.531 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6362 21:46:59.531 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6363 21:46:59.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6364 21:46:59.531 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6365 21:46:59.531 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6366 21:46:59.531 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6367 21:46:59.531 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6368 21:46:59.531 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6369 21:46:59.531 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6370 21:46:59.531 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6371 21:46:59.531 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6372 21:46:59.531 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6373 21:46:59.531 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6374 21:46:59.531 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6375 21:46:59.531 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6376 21:46:59.531 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6377 21:46:59.531 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6378 21:46:59.531 0.02617522 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6379 21:46:59.563 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6380 21:46:59.563 0.01336020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6381 21:46:59.563 0.00005373 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6382 21:46:59.578 0.00026983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6383 21:46:59.578 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6384 21:46:59.578 0.00033541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6385 21:46:59.578 0.00028049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6386 21:46:59.578 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 6387 21:46:59.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6388 21:46:59.578 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6389 21:46:59.578 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6390 21:46:59.578 0.00031210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6391 21:46:59.578 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 6392 21:46:59.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6393 21:46:59.578 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6394 21:46:59.578 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6395 21:46:59.578 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6396 21:46:59.578 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6397 21:46:59.578 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6398 21:46:59.578 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6399 21:46:59.578 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6400 21:46:59.578 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6401 21:46:59.578 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6402 21:46:59.578 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6403 21:46:59.578 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 44 6406 21:46:59.578 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6407 21:46:59.578 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6408 21:46:59.578 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6409 21:46:59.578 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 34 6416 21:46:59.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6417 21:46:59.578 0.00030025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6418 21:46:59.578 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6419 21:46:59.578 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6420 21:46:59.578 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6421 21:46:59.578 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6422 21:46:59.578 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6423 21:46:59.578 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6424 21:46:59.578 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6425 21:46:59.578 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6426 21:46:59.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6427 21:46:59.578 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6428 21:46:59.578 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6429 21:46:59.578 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6430 21:46:59.578 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6431 21:46:59.578 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6432 21:46:59.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6433 21:46:59.578 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6434 21:46:59.578 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6435 21:46:59.578 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6436 21:46:59.578 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6437 21:46:59.578 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6438 21:46:59.578 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6439 21:46:59.578 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6440 21:46:59.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6441 21:46:59.578 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6442 21:46:59.578 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6443 21:46:59.578 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6444 21:46:59.578 0.02576317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6445 21:46:59.610 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6446 21:46:59.610 0.01471052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6447 21:46:59.610 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6448 21:46:59.625 0.00030736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6449 21:46:59.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6450 21:46:59.625 0.00025047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6451 21:46:59.625 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6452 21:46:59.625 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 6453 21:46:59.625 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6454 21:46:59.625 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6455 21:46:59.625 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6456 21:46:59.625 0.00027496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6457 21:46:59.625 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 6458 21:46:59.625 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6459 21:46:59.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6460 21:46:59.625 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6461 21:46:59.625 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6462 21:46:59.625 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6463 21:46:59.625 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6464 21:46:59.625 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 6465 21:46:59.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6466 21:46:59.625 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6467 21:46:59.625 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6468 21:46:59.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6469 21:46:59.625 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6470 21:46:59.625 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6471 21:46:59.625 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6472 21:46:59.625 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6473 21:46:59.625 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6474 21:46:59.625 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6475 21:46:59.625 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6476 21:46:59.625 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 6477 21:46:59.625 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6478 21:46:59.625 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6479 21:46:59.625 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6480 21:46:59.625 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6481 21:46:59.625 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6482 21:46:59.625 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6483 21:46:59.625 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6484 21:46:59.625 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6485 21:46:59.625 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6486 21:46:59.625 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6487 21:46:59.625 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6488 21:46:59.625 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6489 21:46:59.625 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6490 21:46:59.625 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6491 21:46:59.625 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6492 21:46:59.625 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6493 21:46:59.625 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6494 21:46:59.625 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6495 21:46:59.625 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6496 21:46:59.625 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6497 21:46:59.625 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6498 21:46:59.625 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6499 21:46:59.625 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6500 21:46:59.625 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6501 21:46:59.625 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6502 21:46:59.625 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6503 21:46:59.625 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6504 21:46:59.625 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6505 21:46:59.625 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6506 21:46:59.625 0.00032000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6507 21:46:59.625 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6508 21:46:59.625 0.00026114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6509 21:46:59.625 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6510 21:46:59.625 0.02812209 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6511 21:46:59.657 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6512 21:46:59.657 0.01202687 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6513 21:46:59.657 0.00004346 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6514 21:46:59.672 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6515 21:46:59.672 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6516 21:46:59.672 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6518 21:46:59.672 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6519 21:46:59.672 0.00034291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6520 21:46:59.672 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 6521 21:46:59.672 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 6522 21:46:59.672 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6523 21:46:59.672 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6524 21:46:59.672 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6525 21:46:59.672 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6526 21:46:59.672 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6527 21:46:59.672 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6528 21:46:59.672 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6529 21:46:59.672 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6530 21:46:59.672 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6531 21:46:59.672 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6532 21:46:59.672 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6533 21:46:59.672 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6534 21:46:59.672 0.00022519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6535 21:46:59.672 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 6536 21:46:59.672 0.00035753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6537 21:46:59.672 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6538 21:46:59.672 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6539 21:46:59.672 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6540 21:46:59.672 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6541 21:46:59.672 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6542 21:46:59.672 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 6543 21:46:59.672 0.00027457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6544 21:46:59.672 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6545 21:46:59.672 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6546 21:46:59.672 0.00024731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6547 21:46:59.672 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6548 21:46:59.672 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6549 21:46:59.672 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6550 21:46:59.672 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6551 21:46:59.672 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6552 21:46:59.672 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6553 21:46:59.672 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6554 21:46:59.672 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6555 21:46:59.672 0.00037333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6556 21:46:59.672 0.00034449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6557 21:46:59.672 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 6558 21:46:59.672 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6559 21:46:59.672 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6562 21:46:59.672 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6563 21:46:59.672 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6564 21:46:59.672 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6565 21:46:59.672 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6566 21:46:59.672 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6567 21:46:59.672 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6568 21:46:59.672 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6569 21:46:59.672 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6570 21:46:59.672 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6571 21:46:59.672 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6572 21:46:59.672 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6573 21:46:59.672 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6574 21:46:59.672 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6575 21:46:59.672 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6576 21:46:59.672 0.02591329 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6577 21:46:59.703 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6578 21:46:59.703 0.01493373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6579 21:46:59.703 0.00001620 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6580 21:46:59.719 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6581 21:46:59.719 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6582 21:46:59.719 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6583 21:46:59.719 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6584 21:46:59.719 0.00085728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6585 21:46:59.719 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6586 21:46:59.719 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 03 6589 21:46:59.719 0.00024652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6590 21:46:59.719 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6591 21:46:59.719 0.00036306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6592 21:46:59.719 0.00037373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6593 21:46:59.719 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6594 21:46:59.719 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6595 21:46:59.719 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6596 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6597 21:46:59.719 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6598 21:46:59.719 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6599 21:46:59.719 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6600 21:46:59.719 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6601 21:46:59.719 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6602 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6603 21:46:59.719 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6604 21:46:59.719 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6605 21:46:59.719 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6606 21:46:59.719 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6607 21:46:59.719 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6608 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6609 21:46:59.719 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6610 21:46:59.719 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6611 21:46:59.719 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6612 21:46:59.719 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6613 21:46:59.719 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6614 21:46:59.719 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6615 21:46:59.719 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6616 21:46:59.719 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6617 21:46:59.719 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6618 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6619 21:46:59.719 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6620 21:46:59.719 0.00007783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6621 21:46:59.719 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6622 21:46:59.719 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6623 21:46:59.719 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6624 21:46:59.719 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6625 21:46:59.719 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6626 21:46:59.719 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6627 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6628 21:46:59.719 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6629 21:46:59.719 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6630 21:46:59.719 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6631 21:46:59.719 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6632 21:46:59.719 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6633 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6634 21:46:59.719 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6635 21:46:59.719 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6636 21:46:59.719 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6637 21:46:59.719 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6638 21:46:59.719 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6639 21:46:59.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6640 21:46:59.719 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6641 21:46:59.719 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6642 21:46:59.719 0.02758559 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6643 21:46:59.750 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6644 21:46:59.750 0.01307813 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6645 21:46:59.750 0.00003793 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6646 21:46:59.766 0.00033699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6647 21:46:59.766 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6648 21:46:59.766 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6649 21:46:59.766 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6650 21:46:59.766 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6651 21:46:59.766 0.00043812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6652 21:46:59.766 0.00037847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 6653 21:46:59.766 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6654 21:46:59.766 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6655 21:46:59.766 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6656 21:46:59.766 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6657 21:46:59.766 0.00060800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6658 21:46:59.766 0.00048869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6659 21:46:59.766 0.00030459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6660 21:46:59.766 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6661 21:46:59.766 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6662 21:46:59.766 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6663 21:46:59.766 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6664 21:46:59.766 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6665 21:46:59.766 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6666 21:46:59.766 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 6667 21:46:59.766 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6668 21:46:59.766 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6669 21:46:59.766 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6670 21:46:59.766 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6671 21:46:59.766 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6672 21:46:59.766 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6673 21:46:59.766 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6674 21:46:59.766 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 6675 21:46:59.766 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6676 21:46:59.766 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6677 21:46:59.766 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6678 21:46:59.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6679 21:46:59.766 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6680 21:46:59.766 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6681 21:46:59.766 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6682 21:46:59.766 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6683 21:46:59.766 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6684 21:46:59.766 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6685 21:46:59.766 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6686 21:46:59.766 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6687 21:46:59.766 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6688 21:46:59.766 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6689 21:46:59.766 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 6690 21:46:59.766 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6691 21:46:59.766 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6695 21:46:59.766 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6696 21:46:59.766 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6697 21:46:59.766 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6698 21:46:59.766 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6699 21:46:59.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6700 21:46:59.766 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6701 21:46:59.766 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6702 21:46:59.766 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6703 21:46:59.766 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6704 21:46:59.766 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6705 21:46:59.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6706 21:46:59.766 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6707 21:46:59.766 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6708 21:46:59.766 0.02843537 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6709 21:46:59.797 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6710 21:46:59.797 0.01200277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6711 21:46:59.797 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6712 21:46:59.813 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6713 21:46:59.813 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6714 21:46:59.813 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6715 21:46:59.813 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6716 21:46:59.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6717 21:46:59.813 0.00034015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6718 21:46:59.813 0.00031921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 6719 21:46:59.813 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6720 21:46:59.813 0.00038321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6721 21:46:59.813 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6722 21:46:59.813 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6723 21:46:59.813 0.00028761 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6724 21:46:59.813 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6725 21:46:59.813 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6726 21:46:59.813 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6727 21:46:59.813 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6728 21:46:59.813 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6729 21:46:59.813 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 6730 21:46:59.813 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6731 21:46:59.813 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6732 21:46:59.813 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6733 21:46:59.813 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6734 21:46:59.813 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6735 21:46:59.813 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6736 21:46:59.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6737 21:46:59.813 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6738 21:46:59.813 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 6739 21:46:59.813 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6740 21:46:59.813 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6741 21:46:59.813 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6742 21:46:59.813 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6743 21:46:59.813 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 42 6744 21:46:59.813 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6745 21:46:59.813 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6746 21:46:59.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6747 21:46:59.813 0.00022756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6748 21:46:59.813 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6749 21:46:59.813 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6750 21:46:59.813 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6751 21:46:59.813 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6752 21:46:59.813 0.00066212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6753 21:46:59.813 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6754 21:46:59.813 0.00066449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6755 21:46:59.813 0.00044247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6756 21:46:59.813 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6757 21:46:59.813 0.00041877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6758 21:46:59.813 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6759 21:46:59.813 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6760 21:46:59.813 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6761 21:46:59.813 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6762 21:46:59.813 0.00034252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6763 21:46:59.813 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6764 21:46:59.813 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6765 21:46:59.813 0.00049620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6766 21:46:59.813 0.00040020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6767 21:46:59.813 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6768 21:46:59.813 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6769 21:46:59.813 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6770 21:46:59.813 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6771 21:46:59.813 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6772 21:46:59.813 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6773 21:46:59.813 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6774 21:46:59.813 0.02563952 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6775 21:46:59.844 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6776 21:46:59.844 0.01392317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6777 21:46:59.844 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6778 21:46:59.860 0.00030499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6779 21:46:59.860 0.00050291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6780 21:46:59.860 0.00033896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6781 21:46:59.860 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6782 21:46:59.860 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6783 21:46:59.860 0.00033264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6784 21:46:59.860 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 6785 21:46:59.860 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6786 21:46:59.860 0.00024415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6787 21:46:59.860 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6788 21:46:59.860 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6789 21:46:59.860 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6790 21:46:59.860 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6791 21:46:59.860 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6792 21:46:59.860 0.00032435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6793 21:46:59.860 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6794 21:46:59.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6795 21:46:59.860 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6796 21:46:59.860 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6797 21:46:59.860 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6798 21:46:59.860 0.00018726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6800 21:46:59.860 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6801 21:46:59.860 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6802 21:46:59.860 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6803 21:46:59.860 0.00037886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 6804 21:46:59.860 0.00034410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6805 21:46:59.860 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6806 21:46:59.860 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6807 21:46:59.860 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6808 21:46:59.860 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 6809 21:46:59.860 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6810 21:46:59.860 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6811 21:46:59.860 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6812 21:46:59.860 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6813 21:46:59.860 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6814 21:46:59.860 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6815 21:46:59.860 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 6819 21:46:59.860 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6820 21:46:59.860 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6821 21:46:59.860 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6822 21:46:59.860 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6823 21:46:59.860 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6824 21:46:59.860 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6825 21:46:59.860 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6826 21:46:59.860 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6827 21:46:59.860 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6828 21:46:59.860 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6829 21:46:59.860 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6830 21:46:59.860 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6831 21:46:59.860 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6832 21:46:59.860 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6833 21:46:59.860 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6834 21:46:59.860 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6835 21:46:59.860 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6836 21:46:59.860 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6837 21:46:59.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6838 21:46:59.860 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6839 21:46:59.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6840 21:46:59.860 0.02715458 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6841 21:46:59.891 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6842 21:46:59.891 0.01273759 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6843 21:46:59.891 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6844 21:46:59.906 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6845 21:46:59.906 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6846 21:46:59.906 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6847 21:46:59.906 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6848 21:46:59.906 0.00028761 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 6849 21:46:59.906 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6850 21:46:59.906 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6851 21:46:59.906 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6852 21:46:59.906 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6853 21:46:59.906 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 6854 21:46:59.906 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6855 21:46:59.906 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6856 21:46:59.906 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6857 21:46:59.906 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6858 21:46:59.906 0.00033541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6859 21:46:59.906 0.00035951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6860 21:46:59.906 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6861 21:46:59.906 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6862 21:46:59.906 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6863 21:46:59.906 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6864 21:46:59.906 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6865 21:46:59.906 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6866 21:46:59.906 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6867 21:46:59.906 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6868 21:46:59.906 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6869 21:46:59.906 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6870 21:46:59.906 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6871 21:46:59.906 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6872 21:46:59.906 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6873 21:46:59.906 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6874 21:46:59.906 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6875 21:46:59.906 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6876 21:46:59.906 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6877 21:46:59.906 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6878 21:46:59.906 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6879 21:46:59.906 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6880 21:46:59.906 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6881 21:46:59.906 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6882 21:46:59.906 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6883 21:46:59.906 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6884 21:46:59.906 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6885 21:46:59.906 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6886 21:46:59.906 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6887 21:46:59.906 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6888 21:46:59.906 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6889 21:46:59.906 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6890 21:46:59.906 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6891 21:46:59.906 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6892 21:46:59.906 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6893 21:46:59.906 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6894 21:46:59.906 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6895 21:46:59.906 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6896 21:46:59.906 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6897 21:46:59.906 0.00008691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 6898 21:46:59.906 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6899 21:46:59.906 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6900 21:46:59.906 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 6901 21:46:59.906 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6902 21:46:59.906 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6903 21:46:59.906 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6904 21:46:59.906 0.02811063 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6905 21:46:59.938 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6906 21:46:59.938 0.01380149 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6907 21:46:59.938 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6908 21:46:59.953 0.00038400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6909 21:46:59.953 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6910 21:46:59.953 0.00047210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6911 21:46:59.953 0.00033699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6912 21:46:59.953 0.00026667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 6913 21:46:59.953 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6914 21:46:59.953 0.00021057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6915 21:46:59.953 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 6916 21:46:59.953 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6917 21:46:59.953 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6918 21:46:59.953 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6919 21:46:59.953 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 6920 21:46:59.953 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6921 21:46:59.953 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6922 21:46:59.953 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6923 21:46:59.953 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6924 21:46:59.953 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 6925 21:46:59.953 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6926 21:46:59.953 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6927 21:46:59.953 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 6928 21:46:59.953 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6929 21:46:59.953 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6930 21:46:59.953 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6931 21:46:59.953 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6932 21:46:59.953 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6933 21:46:59.953 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6934 21:46:59.953 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6935 21:46:59.953 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 6936 21:46:59.953 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 30 6937 21:46:59.953 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6938 21:46:59.953 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6940 21:46:59.953 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6941 21:46:59.953 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6942 21:46:59.953 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6943 21:46:59.953 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6944 21:46:59.953 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6945 21:46:59.953 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6946 21:46:59.953 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6947 21:46:59.953 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6948 21:46:59.953 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6949 21:46:59.953 0.00033659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6950 21:46:59.953 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6951 21:46:59.953 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6952 21:46:59.953 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6953 21:46:59.953 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6954 21:46:59.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6955 21:46:59.953 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6956 21:46:59.953 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6957 21:46:59.953 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6958 21:46:59.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6959 21:46:59.953 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6960 21:46:59.953 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6961 21:46:59.953 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6962 21:46:59.953 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6963 21:46:59.953 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6964 21:46:59.953 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6965 21:46:59.953 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6966 21:46:59.953 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 6967 21:46:59.953 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6968 21:46:59.953 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6969 21:46:59.953 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6970 21:46:59.953 0.02673976 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6971 21:46:59.985 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6972 21:46:59.985 0.01385047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6973 21:46:59.985 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 6974 21:47:00.000 0.00029827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 6975 21:47:00.000 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6976 21:47:00.000 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 6977 21:47:00.000 0.00028879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6978 21:47:00.000 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6979 21:47:00.000 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 03 6980 21:47:00.000 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 6983 21:47:00.000 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6984 21:47:00.000 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 6985 21:47:00.000 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6986 21:47:00.000 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6987 21:47:00.000 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6988 21:47:00.000 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6989 21:47:00.000 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 6990 21:47:00.000 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6991 21:47:00.000 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6992 21:47:00.000 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 6993 21:47:00.000 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6994 21:47:00.000 0.00030815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6995 21:47:00.000 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6996 21:47:00.000 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 6997 21:47:00.000 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 6998 21:47:00.000 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 6999 21:47:00.000 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7000 21:47:00.000 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7001 21:47:00.000 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7002 21:47:00.000 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7003 21:47:00.000 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7004 21:47:00.000 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 7005 21:47:00.000 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7006 21:47:00.000 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7007 21:47:00.000 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7008 21:47:00.000 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7009 21:47:00.000 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7010 21:47:00.000 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7011 21:47:00.000 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7012 21:47:00.000 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7013 21:47:00.000 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7014 21:47:00.000 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7015 21:47:00.000 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7016 21:47:00.000 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7017 21:47:00.000 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7018 21:47:00.000 0.00030499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7019 21:47:00.000 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7020 21:47:00.000 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7021 21:47:00.000 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7022 21:47:00.000 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7023 21:47:00.000 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7024 21:47:00.000 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7025 21:47:00.000 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7026 21:47:00.000 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7027 21:47:00.000 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7028 21:47:00.000 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7029 21:47:00.000 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7030 21:47:00.000 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7031 21:47:00.000 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7032 21:47:00.000 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7033 21:47:00.000 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7034 21:47:00.000 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7035 21:47:00.000 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7036 21:47:00.000 0.02746786 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7037 21:47:00.031 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7038 21:47:00.031 0.01288178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7039 21:47:00.031 0.00000593 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7040 21:47:00.047 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7041 21:47:00.047 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7042 21:47:00.047 0.00036662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7043 21:47:00.047 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7044 21:47:00.047 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7045 21:47:00.047 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7046 21:47:00.047 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7047 21:47:00.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7048 21:47:00.047 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7049 21:47:00.047 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 7050 21:47:00.047 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7051 21:47:00.047 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7052 21:47:00.047 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7053 21:47:00.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7054 21:47:00.047 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7055 21:47:00.047 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7056 21:47:00.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7057 21:47:00.047 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7058 21:47:00.047 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7059 21:47:00.047 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7060 21:47:00.047 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7061 21:47:00.047 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7062 21:47:00.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7063 21:47:00.047 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7064 21:47:00.047 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7065 21:47:00.047 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7066 21:47:00.047 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7067 21:47:00.047 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7068 21:47:00.047 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 7069 21:47:00.047 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7070 21:47:00.047 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7071 21:47:00.047 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7072 21:47:00.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7073 21:47:00.047 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7074 21:47:00.047 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7075 21:47:00.047 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7076 21:47:00.047 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7077 21:47:00.047 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7078 21:47:00.047 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7079 21:47:00.047 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7080 21:47:00.047 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7081 21:47:00.047 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7082 21:47:00.047 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7083 21:47:00.047 0.00008178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7084 21:47:00.047 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7085 21:47:00.047 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7086 21:47:00.047 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7087 21:47:00.047 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7088 21:47:00.047 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7089 21:47:00.047 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7090 21:47:00.047 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7091 21:47:00.047 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7092 21:47:00.047 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7093 21:47:00.047 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7094 21:47:00.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7095 21:47:00.047 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7096 21:47:00.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7097 21:47:00.047 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7098 21:47:00.047 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7099 21:47:00.047 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7100 21:47:00.047 0.02795774 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7101 21:47:00.078 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7102 21:47:00.078 0.01401561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7103 21:47:00.078 0.00002252 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7104 21:47:00.094 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7105 21:47:00.094 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7106 21:47:00.094 0.00036109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7107 21:47:00.094 0.00031328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7108 21:47:00.094 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7109 21:47:00.094 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7110 21:47:00.094 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7111 21:47:00.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7112 21:47:00.094 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7113 21:47:00.094 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7114 21:47:00.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7115 21:47:00.094 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7116 21:47:00.094 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7117 21:47:00.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7118 21:47:00.094 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7119 21:47:00.094 0.00025363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7120 21:47:00.094 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7121 21:47:00.094 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7122 21:47:00.094 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7123 21:47:00.094 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7124 21:47:00.094 0.00029472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7125 21:47:00.094 0.00026272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7126 21:47:00.094 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7127 21:47:00.094 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7128 21:47:00.094 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7129 21:47:00.094 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7130 21:47:00.094 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7131 21:47:00.094 0.00045748 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7132 21:47:00.094 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7133 21:47:00.094 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7134 21:47:00.094 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7135 21:47:00.094 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 43 7136 21:47:00.094 0.00032909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7137 21:47:00.094 0.00054598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7138 21:47:00.094 0.00021412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7139 21:47:00.094 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7140 21:47:00.094 0.00028168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7141 21:47:00.094 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7142 21:47:00.094 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7143 21:47:00.094 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7144 21:47:00.094 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7145 21:47:00.094 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7146 21:47:00.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7147 21:47:00.094 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7148 21:47:00.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7149 21:47:00.094 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7150 21:47:00.094 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7151 21:47:00.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7152 21:47:00.094 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7153 21:47:00.094 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7154 21:47:00.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7155 21:47:00.094 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7156 21:47:00.094 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7157 21:47:00.094 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7158 21:47:00.094 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7159 21:47:00.094 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7160 21:47:00.094 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7161 21:47:00.094 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7162 21:47:00.094 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7163 21:47:00.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7164 21:47:00.094 0.02523537 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7165 21:47:00.125 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7166 21:47:00.125 0.01428662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7167 21:47:00.125 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7168 21:47:00.141 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7169 21:47:00.141 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7170 21:47:00.141 0.00038440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7171 21:47:00.141 0.00027812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7172 21:47:00.141 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7173 21:47:00.141 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7174 21:47:00.141 0.00038756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7178 21:47:00.141 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7179 21:47:00.141 0.00029235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7180 21:47:00.141 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7181 21:47:00.141 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7182 21:47:00.141 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7183 21:47:00.141 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7184 21:47:00.141 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7185 21:47:00.141 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7186 21:47:00.141 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7187 21:47:00.141 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7188 21:47:00.141 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7189 21:47:00.141 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7190 21:47:00.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7191 21:47:00.141 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7192 21:47:00.141 0.00026311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7193 21:47:00.141 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7194 21:47:00.141 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7195 21:47:00.141 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7196 21:47:00.141 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 7197 21:47:00.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7198 21:47:00.141 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7199 21:47:00.141 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7200 21:47:00.141 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7201 21:47:00.141 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7202 21:47:00.141 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7203 21:47:00.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7204 21:47:00.141 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7205 21:47:00.141 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7206 21:47:00.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7207 21:47:00.141 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7208 21:47:00.141 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7209 21:47:00.141 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7210 21:47:00.141 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7211 21:47:00.141 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7212 21:47:00.141 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7213 21:47:00.141 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7214 21:47:00.141 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7215 21:47:00.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7216 21:47:00.141 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7217 21:47:00.141 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7218 21:47:00.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7219 21:47:00.141 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7220 21:47:00.141 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7221 21:47:00.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7222 21:47:00.141 0.00021057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7223 21:47:00.141 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7224 21:47:00.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7225 21:47:00.141 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7226 21:47:00.141 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7227 21:47:00.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7228 21:47:00.141 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7229 21:47:00.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7230 21:47:00.141 0.02722095 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7231 21:47:00.172 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7232 21:47:00.172 0.01357393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7233 21:47:00.172 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7234 21:47:00.188 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7235 21:47:00.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7236 21:47:00.188 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7237 21:47:00.188 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7238 21:47:00.188 0.00044168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7239 21:47:00.188 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7240 21:47:00.188 0.00046696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7241 21:47:00.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7242 21:47:00.188 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7243 21:47:00.188 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7244 21:47:00.188 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7245 21:47:00.188 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7246 21:47:00.188 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7247 21:47:00.188 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7248 21:47:00.188 0.00026785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7249 21:47:00.188 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7250 21:47:00.188 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7251 21:47:00.188 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 7252 21:47:00.188 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7253 21:47:00.188 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7254 21:47:00.188 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7255 21:47:00.188 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7256 21:47:00.188 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7257 21:47:00.188 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7258 21:47:00.188 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7259 21:47:00.188 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7260 21:47:00.188 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7261 21:47:00.188 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7262 21:47:00.188 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 7263 21:47:00.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7264 21:47:00.188 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7265 21:47:00.188 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7266 21:47:00.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7267 21:47:00.188 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7268 21:47:00.188 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7269 21:47:00.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7270 21:47:00.188 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7271 21:47:00.188 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7272 21:47:00.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7273 21:47:00.188 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7274 21:47:00.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7275 21:47:00.188 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7276 21:47:00.188 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7277 21:47:00.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7278 21:47:00.188 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7279 21:47:00.188 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7280 21:47:00.188 0.00008533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7281 21:47:00.188 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7282 21:47:00.188 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7283 21:47:00.188 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7284 21:47:00.188 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7285 21:47:00.188 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7286 21:47:00.188 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7287 21:47:00.188 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7288 21:47:00.188 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7289 21:47:00.188 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7290 21:47:00.188 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7291 21:47:00.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7292 21:47:00.188 0.02617601 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7293 21:47:00.219 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7294 21:47:00.219 0.01455922 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7295 21:47:00.219 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7296 21:47:00.235 0.00060049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7297 21:47:00.235 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7298 21:47:00.235 0.00048948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7299 21:47:00.235 0.00031565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7300 21:47:00.235 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7301 21:47:00.235 0.00041284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7302 21:47:00.235 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7303 21:47:00.235 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7304 21:47:00.235 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7305 21:47:00.235 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7306 21:47:00.235 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7307 21:47:00.235 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7308 21:47:00.235 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7309 21:47:00.235 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7310 21:47:00.235 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7311 21:47:00.235 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7312 21:47:00.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7313 21:47:00.235 0.00037136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7314 21:47:00.235 0.00027852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7315 21:47:00.235 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7316 21:47:00.235 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7317 21:47:00.235 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7318 21:47:00.235 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7319 21:47:00.235 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7320 21:47:00.235 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7321 21:47:00.235 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7322 21:47:00.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7323 21:47:00.235 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7324 21:47:00.235 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7325 21:47:00.235 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 7326 21:47:00.235 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7327 21:47:00.235 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7328 21:47:00.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7329 21:47:00.235 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7330 21:47:00.235 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7331 21:47:00.235 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7332 21:47:00.235 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7333 21:47:00.235 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7334 21:47:00.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7335 21:47:00.235 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7336 21:47:00.235 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7337 21:47:00.235 0.00034765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7338 21:47:00.235 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7339 21:47:00.235 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7340 21:47:00.235 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7341 21:47:00.235 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7342 21:47:00.235 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7343 21:47:00.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7344 21:47:00.235 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7345 21:47:00.235 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7346 21:47:00.235 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7347 21:47:00.235 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7348 21:47:00.235 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7349 21:47:00.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7350 21:47:00.235 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7351 21:47:00.235 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7352 21:47:00.235 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7353 21:47:00.235 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7354 21:47:00.235 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7355 21:47:00.235 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7356 21:47:00.235 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7357 21:47:00.235 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7358 21:47:00.235 0.02791112 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7359 21:47:00.266 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7360 21:47:00.266 0.01140188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7361 21:47:00.266 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7362 21:47:00.282 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7363 21:47:00.282 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7364 21:47:00.282 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7365 21:47:00.282 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7366 21:47:00.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7367 21:47:00.282 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7368 21:47:00.282 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7369 21:47:00.282 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7370 21:47:00.282 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7371 21:47:00.282 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 7372 21:47:00.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7373 21:47:00.282 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7374 21:47:00.282 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7375 21:47:00.282 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7376 21:47:00.282 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7377 21:47:00.282 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7378 21:47:00.282 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7379 21:47:00.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7380 21:47:00.282 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7381 21:47:00.282 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7382 21:47:00.282 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7383 21:47:00.282 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7384 21:47:00.282 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7385 21:47:00.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7386 21:47:00.282 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7387 21:47:00.282 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7388 21:47:00.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7389 21:47:00.282 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7390 21:47:00.282 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7391 21:47:00.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7392 21:47:00.282 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7393 21:47:00.282 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7394 21:47:00.282 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7395 21:47:00.282 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7396 21:47:00.282 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7397 21:47:00.282 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7398 21:47:00.282 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7399 21:47:00.282 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7400 21:47:00.282 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7401 21:47:00.282 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7402 21:47:00.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7403 21:47:00.282 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7404 21:47:00.282 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7405 21:47:00.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7406 21:47:00.282 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7407 21:47:00.282 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7408 21:47:00.282 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7409 21:47:00.282 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 7410 21:47:00.282 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7414 21:47:00.282 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7415 21:47:00.282 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7416 21:47:00.282 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7417 21:47:00.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7418 21:47:00.282 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7419 21:47:00.282 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7420 21:47:00.282 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7421 21:47:00.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7422 21:47:00.282 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7423 21:47:00.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7424 21:47:00.282 0.02781947 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7425 21:47:00.313 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7426 21:47:00.313 0.01327052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7427 21:47:00.313 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7428 21:47:00.329 0.00038558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7429 21:47:00.329 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7430 21:47:00.329 0.00034607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7431 21:47:00.329 0.00032632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7432 21:47:00.329 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7433 21:47:00.329 0.00039151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7434 21:47:00.329 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7435 21:47:00.329 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 7436 21:47:00.329 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7437 21:47:00.329 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7438 21:47:00.329 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7439 21:47:00.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7440 21:47:00.329 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7441 21:47:00.329 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7442 21:47:00.329 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7443 21:47:00.329 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7444 21:47:00.329 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7445 21:47:00.329 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7446 21:47:00.329 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7447 21:47:00.329 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7448 21:47:00.329 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7449 21:47:00.329 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7450 21:47:00.329 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7451 21:47:00.329 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7452 21:47:00.329 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7453 21:47:00.329 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7454 21:47:00.329 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7455 21:47:00.329 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7456 21:47:00.329 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7457 21:47:00.329 0.00029867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7458 21:47:00.329 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 7459 21:47:00.329 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7460 21:47:00.329 0.00034370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7461 21:47:00.329 0.00026311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7462 21:47:00.329 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7463 21:47:00.329 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7464 21:47:00.329 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7465 21:47:00.329 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7466 21:47:00.329 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7467 21:47:00.329 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7468 21:47:00.329 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7469 21:47:00.329 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7470 21:47:00.329 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7471 21:47:00.329 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7472 21:47:00.329 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7473 21:47:00.329 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7474 21:47:00.329 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7475 21:47:00.329 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7476 21:47:00.329 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7477 21:47:00.329 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7478 21:47:00.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7479 21:47:00.329 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7480 21:47:00.329 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7481 21:47:00.329 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7482 21:47:00.329 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7483 21:47:00.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7484 21:47:00.329 0.00029116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7485 21:47:00.329 0.00027180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7486 21:47:00.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7487 21:47:00.329 0.00029590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7488 21:47:00.329 0.00028247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7489 21:47:00.329 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7490 21:47:00.329 0.02640317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7491 21:47:00.360 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7492 21:47:00.360 0.01345107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7493 21:47:00.360 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7494 21:47:00.376 0.00038716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7495 21:47:00.376 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7496 21:47:00.376 0.00044049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7497 21:47:00.376 0.00039862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7498 21:47:00.376 0.00080988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7499 21:47:00.376 0.00033383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7500 21:47:00.376 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7501 21:47:00.376 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7502 21:47:00.376 0.00031802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 7503 21:47:00.376 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7504 21:47:00.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7505 21:47:00.376 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7506 21:47:00.376 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7507 21:47:00.376 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7508 21:47:00.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7509 21:47:00.376 0.00024138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7510 21:47:00.376 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 7511 21:47:00.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7512 21:47:00.376 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7513 21:47:00.376 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7514 21:47:00.376 0.00041640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7515 21:47:00.376 0.00035753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7516 21:47:00.376 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7517 21:47:00.376 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7518 21:47:00.376 0.00023348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7519 21:47:00.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7520 21:47:00.376 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7521 21:47:00.376 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 7528 21:47:00.376 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7529 21:47:00.376 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7530 21:47:00.376 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7531 21:47:00.376 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7532 21:47:00.376 0.00033501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7533 21:47:00.376 0.00032158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7534 21:47:00.376 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7535 21:47:00.376 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7536 21:47:00.376 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7537 21:47:00.376 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7538 21:47:00.376 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7539 21:47:00.376 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7540 21:47:00.376 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7541 21:47:00.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7542 21:47:00.376 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7543 21:47:00.376 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 7544 21:47:00.376 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7545 21:47:00.376 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7549 21:47:00.376 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7550 21:47:00.376 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7551 21:47:00.376 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7552 21:47:00.376 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7553 21:47:00.376 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7554 21:47:00.376 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7555 21:47:00.376 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7556 21:47:00.376 0.02444801 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7557 21:47:00.406 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7558 21:47:00.406 0.01428386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7559 21:47:00.406 0.00003793 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7560 21:47:00.422 0.00043931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7561 21:47:00.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7562 21:47:00.422 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7563 21:47:00.422 0.00028286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7564 21:47:00.422 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7565 21:47:00.422 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7566 21:47:00.422 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7567 21:47:00.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7568 21:47:00.422 0.00034726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7569 21:47:00.422 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 7570 21:47:00.422 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7571 21:47:00.422 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7572 21:47:00.422 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7573 21:47:00.422 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7574 21:47:00.422 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7575 21:47:00.422 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7576 21:47:00.422 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7577 21:47:00.422 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7578 21:47:00.422 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7579 21:47:00.422 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7580 21:47:00.422 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7581 21:47:00.422 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7582 21:47:00.422 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7583 21:47:00.422 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7584 21:47:00.422 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7585 21:47:00.422 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7586 21:47:00.422 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7587 21:47:00.422 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7588 21:47:00.422 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 35 7589 21:47:00.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7590 21:47:00.422 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7592 21:47:00.422 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7593 21:47:00.422 0.00016869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7594 21:47:00.422 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7595 21:47:00.422 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7596 21:47:00.422 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7597 21:47:00.422 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7598 21:47:00.422 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7599 21:47:00.422 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7600 21:47:00.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7601 21:47:00.422 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7602 21:47:00.422 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7603 21:47:00.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7604 21:47:00.422 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7605 21:47:00.422 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7606 21:47:00.422 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7607 21:47:00.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7608 21:47:00.422 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7609 21:47:00.422 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7610 21:47:00.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7611 21:47:00.422 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7612 21:47:00.422 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7613 21:47:00.422 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7614 21:47:00.422 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7615 21:47:00.422 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7616 21:47:00.422 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7617 21:47:00.422 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7618 21:47:00.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7619 21:47:00.422 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7620 21:47:00.422 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7621 21:47:00.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7622 21:47:00.422 0.02743231 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7623 21:47:00.453 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7624 21:47:00.453 0.01287388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7625 21:47:00.453 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7626 21:47:00.469 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7627 21:47:00.469 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7628 21:47:00.469 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7629 21:47:00.469 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7630 21:47:00.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7631 21:47:00.469 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7632 21:47:00.469 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7633 21:47:00.469 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 7634 21:47:00.469 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7635 21:47:00.469 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7636 21:47:00.469 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7637 21:47:00.469 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7638 21:47:00.469 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7639 21:47:00.469 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7640 21:47:00.469 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7641 21:47:00.469 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7642 21:47:00.469 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7643 21:47:00.469 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7644 21:47:00.469 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7645 21:47:00.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7646 21:47:00.469 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7647 21:47:00.469 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7648 21:47:00.469 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7649 21:47:00.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7650 21:47:00.469 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7651 21:47:00.469 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7652 21:47:00.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7653 21:47:00.469 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7654 21:47:00.469 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7655 21:47:00.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7656 21:47:00.469 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7657 21:47:00.469 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7658 21:47:00.469 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7659 21:47:00.469 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7660 21:47:00.469 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7661 21:47:00.469 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7662 21:47:00.469 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7663 21:47:00.469 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7664 21:47:00.469 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7665 21:47:00.469 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7666 21:47:00.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7667 21:47:00.469 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7668 21:47:00.469 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7671 21:47:00.469 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7672 21:47:00.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7673 21:47:00.469 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7674 21:47:00.469 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7675 21:47:00.469 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7676 21:47:00.469 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7677 21:47:00.469 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7678 21:47:00.469 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7679 21:47:00.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7680 21:47:00.469 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7681 21:47:00.469 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7682 21:47:00.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7683 21:47:00.469 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7684 21:47:00.469 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7685 21:47:00.469 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7686 21:47:00.469 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7687 21:47:00.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7688 21:47:00.469 0.02694717 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7689 21:47:00.500 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7690 21:47:00.500 0.01424909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7691 21:47:00.500 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7692 21:47:00.516 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7693 21:47:00.516 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7694 21:47:00.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7695 21:47:00.516 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7696 21:47:00.516 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7697 21:47:00.516 0.00051516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7698 21:47:00.516 0.00043022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7699 21:47:00.516 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7700 21:47:00.516 0.00035121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7701 21:47:00.516 0.00029235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 7702 21:47:00.516 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7703 21:47:00.516 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7704 21:47:00.516 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7705 21:47:00.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7706 21:47:00.516 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7707 21:47:00.516 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7708 21:47:00.516 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7709 21:47:00.516 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7710 21:47:00.516 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7711 21:47:00.516 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7712 21:47:00.516 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7713 21:47:00.516 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7714 21:47:00.516 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7715 21:47:00.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7716 21:47:00.516 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7717 21:47:00.516 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7718 21:47:00.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7719 21:47:00.516 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7720 21:47:00.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7721 21:47:00.516 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7722 21:47:00.516 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 7723 21:47:00.516 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7724 21:47:00.516 0.00032988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7725 21:47:00.516 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7726 21:47:00.516 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7727 21:47:00.516 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7728 21:47:00.516 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7729 21:47:00.516 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7730 21:47:00.516 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7731 21:47:00.516 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7732 21:47:00.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7733 21:47:00.516 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7734 21:47:00.516 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7735 21:47:00.516 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7736 21:47:00.516 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7737 21:47:00.516 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7738 21:47:00.516 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7739 21:47:00.516 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7740 21:47:00.516 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7741 21:47:00.516 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7742 21:47:00.516 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7743 21:47:00.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7744 21:47:00.516 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7745 21:47:00.516 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 7746 21:47:00.516 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7747 21:47:00.516 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7751 21:47:00.516 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7752 21:47:00.516 0.02677532 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7753 21:47:00.547 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7754 21:47:00.547 0.01466035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7756 21:47:00.563 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7757 21:47:00.563 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7758 21:47:00.563 0.00027891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7759 21:47:00.563 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7760 21:47:00.563 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7761 21:47:00.563 0.00036978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7762 21:47:00.563 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7763 21:47:00.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7764 21:47:00.563 0.00036425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7765 21:47:00.563 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 7766 21:47:00.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7767 21:47:00.563 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7768 21:47:00.563 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7769 21:47:00.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7772 21:47:00.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7773 21:47:00.563 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7774 21:47:00.563 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 7775 21:47:00.563 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7776 21:47:00.563 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7777 21:47:00.563 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7778 21:47:00.563 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7779 21:47:00.563 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7780 21:47:00.563 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7781 21:47:00.563 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7782 21:47:00.563 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7783 21:47:00.563 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7784 21:47:00.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7785 21:47:00.563 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7786 21:47:00.563 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 7787 21:47:00.563 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7788 21:47:00.563 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7789 21:47:00.563 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7790 21:47:00.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7791 21:47:00.563 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7792 21:47:00.563 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7793 21:47:00.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7794 21:47:00.563 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7796 21:47:00.563 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7797 21:47:00.563 0.00064830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7798 21:47:00.563 0.00047486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7799 21:47:00.563 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7800 21:47:00.563 0.00035872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7801 21:47:00.563 0.00046143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7802 21:47:00.563 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7803 21:47:00.563 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7805 21:47:00.563 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7806 21:47:00.563 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7807 21:47:00.563 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7808 21:47:00.563 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7809 21:47:00.563 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7810 21:47:00.563 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7811 21:47:00.563 0.00007704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 7812 21:47:00.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7813 21:47:00.563 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7814 21:47:00.563 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7815 21:47:00.563 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7816 21:47:00.563 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7817 21:47:00.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7818 21:47:00.563 0.02544989 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7819 21:47:00.594 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7820 21:47:00.594 0.01328317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7821 21:47:00.594 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7822 21:47:00.610 0.00030933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7823 21:47:00.610 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7824 21:47:00.610 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7825 21:47:00.610 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7826 21:47:00.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7827 21:47:00.610 0.00042469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7828 21:47:00.610 0.00038677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7829 21:47:00.610 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 7830 21:47:00.610 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7831 21:47:00.610 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7832 21:47:00.610 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7833 21:47:00.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7834 21:47:00.610 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7835 21:47:00.610 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7836 21:47:00.610 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7837 21:47:00.610 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7838 21:47:00.610 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7839 21:47:00.610 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7840 21:47:00.610 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 7841 21:47:00.610 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 7842 21:47:00.610 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7843 21:47:00.610 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7844 21:47:00.610 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7845 21:47:00.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7846 21:47:00.610 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7847 21:47:00.610 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7848 21:47:00.610 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7849 21:47:00.610 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7850 21:47:00.610 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 7851 21:47:00.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7852 21:47:00.610 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7853 21:47:00.610 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7854 21:47:00.610 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7855 21:47:00.610 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7856 21:47:00.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7857 21:47:00.610 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7858 21:47:00.610 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7859 21:47:00.610 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7860 21:47:00.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7861 21:47:00.610 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7862 21:47:00.610 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7863 21:47:00.610 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7864 21:47:00.610 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7865 21:47:00.610 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7866 21:47:00.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7867 21:47:00.610 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7868 21:47:00.610 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7869 21:47:00.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7870 21:47:00.610 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7871 21:47:00.610 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 7872 21:47:00.610 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7873 21:47:00.610 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7877 21:47:00.610 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7878 21:47:00.610 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7879 21:47:00.610 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7880 21:47:00.610 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7881 21:47:00.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7882 21:47:00.610 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7883 21:47:00.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7884 21:47:00.610 0.02784712 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7885 21:47:00.641 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7886 21:47:00.641 0.01352810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7887 21:47:00.641 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7888 21:47:00.657 0.00025521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7889 21:47:00.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7890 21:47:00.657 0.00025284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7891 21:47:00.657 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7892 21:47:00.657 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 7893 21:47:00.657 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7894 21:47:00.657 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7895 21:47:00.657 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 7896 21:47:00.657 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7897 21:47:00.657 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7898 21:47:00.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7899 21:47:00.657 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7900 21:47:00.657 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7901 21:47:00.657 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7902 21:47:00.657 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7903 21:47:00.657 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7904 21:47:00.657 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7905 21:47:00.657 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7906 21:47:00.657 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7907 21:47:00.657 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 7908 21:47:00.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7909 21:47:00.657 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7910 21:47:00.657 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7911 21:47:00.657 0.00026785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7912 21:47:00.657 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7913 21:47:00.657 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7914 21:47:00.657 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7915 21:47:00.657 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7916 21:47:00.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7917 21:47:00.657 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7918 21:47:00.657 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7919 21:47:00.657 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7920 21:47:00.657 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7921 21:47:00.657 0.00023546 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 7922 21:47:00.657 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7923 21:47:00.657 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7924 21:47:00.657 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 7925 21:47:00.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7926 21:47:00.657 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7927 21:47:00.657 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7928 21:47:00.657 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7929 21:47:00.657 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7930 21:47:00.657 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7931 21:47:00.657 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7932 21:47:00.657 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7933 21:47:00.657 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7934 21:47:00.657 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7935 21:47:00.657 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7936 21:47:00.657 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7937 21:47:00.657 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 7938 21:47:00.657 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7939 21:47:00.657 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7940 21:47:00.657 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7941 21:47:00.657 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7942 21:47:00.657 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 7946 21:47:00.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7947 21:47:00.657 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7948 21:47:00.657 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 7949 21:47:00.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7950 21:47:00.657 0.02507458 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7951 21:47:00.688 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7952 21:47:00.688 0.01503131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7953 21:47:00.688 0.00000514 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 7954 21:47:00.704 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 7955 21:47:00.704 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7956 21:47:00.704 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7957 21:47:00.704 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 7958 21:47:00.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7959 21:47:00.704 0.00036306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7960 21:47:00.704 0.00030854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 7961 21:47:00.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7962 21:47:00.704 0.00031447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7963 21:47:00.704 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 7964 21:47:00.704 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 7965 21:47:00.704 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7966 21:47:00.704 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7967 21:47:00.704 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 7968 21:47:00.704 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7969 21:47:00.704 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7973 21:47:00.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7974 21:47:00.704 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 44 7975 21:47:00.704 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 7977 21:47:00.704 0.00035951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7978 21:47:00.704 0.00033541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7979 21:47:00.704 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7980 21:47:00.704 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 7981 21:47:00.704 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7982 21:47:00.704 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 7983 21:47:00.704 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7984 21:47:00.704 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7985 21:47:00.704 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7986 21:47:00.704 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7988 21:47:00.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7989 21:47:00.704 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7990 21:47:00.704 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7991 21:47:00.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7992 21:47:00.704 0.00461195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7993 21:47:00.704 0.00461235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7994 21:47:00.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7995 21:47:00.704 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 7996 21:47:00.704 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7997 21:47:00.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 7998 21:47:00.704 0.00029590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 7999 21:47:00.704 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8000 21:47:00.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8001 21:47:00.704 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8002 21:47:00.704 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8003 21:47:00.704 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8004 21:47:00.704 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8005 21:47:00.704 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8006 21:47:00.704 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8007 21:47:00.704 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8008 21:47:00.704 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8009 21:47:00.704 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8010 21:47:00.704 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8011 21:47:00.704 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8012 21:47:00.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8013 21:47:00.704 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8014 21:47:00.704 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8015 21:47:00.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8016 21:47:00.704 0.02168100 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8017 21:47:00.735 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8018 21:47:00.735 0.01383388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8019 21:47:00.735 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8020 21:47:00.751 0.00032474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8021 21:47:00.751 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8022 21:47:00.751 0.00032237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8023 21:47:00.751 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8024 21:47:00.751 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8025 21:47:00.751 0.00035516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8026 21:47:00.751 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 8027 21:47:00.751 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8028 21:47:00.751 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8029 21:47:00.751 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 8030 21:47:00.751 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8031 21:47:00.751 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8032 21:47:00.751 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8033 21:47:00.751 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8034 21:47:00.751 0.00029946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8035 21:47:00.751 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8036 21:47:00.751 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8037 21:47:00.751 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 8038 21:47:00.751 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8039 21:47:00.751 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8040 21:47:00.751 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8041 21:47:00.751 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 8042 21:47:00.751 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8043 21:47:00.751 0.00028879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8044 21:47:00.751 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8045 21:47:00.751 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8046 21:47:00.751 0.00032198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8047 21:47:00.751 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8048 21:47:00.751 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8049 21:47:00.751 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8050 21:47:00.751 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 8051 21:47:00.751 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 8052 21:47:00.751 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8053 21:47:00.751 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8054 21:47:00.751 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8055 21:47:00.751 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8056 21:47:00.751 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8057 21:47:00.751 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8058 21:47:00.751 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8059 21:47:00.751 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8060 21:47:00.751 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8061 21:47:00.751 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8062 21:47:00.751 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8063 21:47:00.751 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8064 21:47:00.751 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8065 21:47:00.751 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8066 21:47:00.751 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8067 21:47:00.751 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8068 21:47:00.751 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8069 21:47:00.751 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8072 21:47:00.751 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8073 21:47:00.751 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8074 21:47:00.751 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8075 21:47:00.751 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8076 21:47:00.751 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8077 21:47:00.751 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8078 21:47:00.751 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8079 21:47:00.751 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8080 21:47:00.751 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8081 21:47:00.751 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8082 21:47:00.751 0.02701275 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8083 21:47:00.782 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8084 21:47:00.782 0.01317729 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8085 21:47:00.782 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8086 21:47:00.797 0.00033896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8087 21:47:00.797 0.00037333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8088 21:47:00.797 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8089 21:47:00.797 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 8090 21:47:00.797 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8091 21:47:00.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8092 21:47:00.797 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8093 21:47:00.797 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 8094 21:47:00.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8095 21:47:00.797 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8096 21:47:00.797 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8097 21:47:00.797 0.00024099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8098 21:47:00.797 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8099 21:47:00.797 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8100 21:47:00.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8101 21:47:00.797 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8102 21:47:00.797 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8103 21:47:00.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8104 21:47:00.797 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8105 21:47:00.797 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8106 21:47:00.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8107 21:47:00.797 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8108 21:47:00.797 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8109 21:47:00.797 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8110 21:47:00.797 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8111 21:47:00.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8112 21:47:00.797 0.00024138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8113 21:47:00.797 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 8114 21:47:00.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8115 21:47:00.797 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8116 21:47:00.797 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 8117 21:47:00.797 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8118 21:47:00.797 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8119 21:47:00.797 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8120 21:47:00.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8121 21:47:00.797 0.00040217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8122 21:47:00.797 0.00031407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8123 21:47:00.797 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8124 21:47:00.797 0.00051793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8125 21:47:00.797 0.00041402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8126 21:47:00.797 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8127 21:47:00.797 0.00026193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8128 21:47:00.797 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8129 21:47:00.797 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8130 21:47:00.797 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8131 21:47:00.797 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8132 21:47:00.797 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8133 21:47:00.797 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8134 21:47:00.797 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8135 21:47:00.797 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8136 21:47:00.797 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8137 21:47:00.797 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8138 21:47:00.797 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8139 21:47:00.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8140 21:47:00.797 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8141 21:47:00.797 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8142 21:47:00.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8143 21:47:00.797 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8144 21:47:00.797 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8145 21:47:00.797 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8146 21:47:00.797 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8147 21:47:00.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8148 21:47:00.797 0.02785147 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8149 21:47:00.828 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8150 21:47:00.828 0.01136870 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8151 21:47:00.828 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8152 21:47:00.844 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8153 21:47:00.844 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8154 21:47:00.844 0.00035635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8155 21:47:00.844 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8156 21:47:00.844 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 8157 21:47:00.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8158 21:47:00.844 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8159 21:47:00.844 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8160 21:47:00.844 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8161 21:47:00.844 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 8165 21:47:00.844 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8166 21:47:00.844 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8167 21:47:00.844 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8168 21:47:00.844 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8169 21:47:00.844 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8170 21:47:00.844 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8171 21:47:00.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8172 21:47:00.844 0.00026430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8173 21:47:00.844 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 8174 21:47:00.844 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8175 21:47:00.844 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8176 21:47:00.844 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8177 21:47:00.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8178 21:47:00.844 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8179 21:47:00.844 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8180 21:47:00.844 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8181 21:47:00.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8182 21:47:00.844 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8183 21:47:00.844 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 8184 21:47:00.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8185 21:47:00.844 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8186 21:47:00.844 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8187 21:47:00.844 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8188 21:47:00.844 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8189 21:47:00.844 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8190 21:47:00.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8191 21:47:00.844 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8192 21:47:00.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8193 21:47:00.844 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8194 21:47:00.844 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8195 21:47:00.844 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8196 21:47:00.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8197 21:47:00.844 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8198 21:47:00.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8199 21:47:00.844 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8200 21:47:00.844 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8201 21:47:00.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8202 21:47:00.844 0.00034528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8203 21:47:00.844 0.00031249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8204 21:47:00.844 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8205 21:47:00.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8206 21:47:00.844 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8207 21:47:00.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8208 21:47:00.844 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8209 21:47:00.844 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8210 21:47:00.844 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8211 21:47:00.844 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8212 21:47:00.844 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8213 21:47:00.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8214 21:47:00.844 0.02577897 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8215 21:47:00.875 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8216 21:47:00.875 0.01389591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8217 21:47:00.875 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8218 21:47:00.891 0.00034133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8219 21:47:00.891 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8220 21:47:00.891 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8221 21:47:00.891 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8222 21:47:00.891 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 8223 21:47:00.891 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8224 21:47:00.891 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8225 21:47:00.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8226 21:47:00.891 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8227 21:47:00.891 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 8228 21:47:00.891 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8229 21:47:00.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8230 21:47:00.891 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8231 21:47:00.891 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8232 21:47:00.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8233 21:47:00.891 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8234 21:47:00.891 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8235 21:47:00.891 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8237 21:47:00.891 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8238 21:47:00.891 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8239 21:47:00.891 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8240 21:47:00.891 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8241 21:47:00.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8242 21:47:00.891 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8243 21:47:00.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8244 21:47:00.891 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 8245 21:47:00.891 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8246 21:47:00.891 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 8247 21:47:00.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8248 21:47:00.891 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8249 21:47:00.891 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8250 21:47:00.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8251 21:47:00.891 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8252 21:47:00.891 0.00008099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8253 21:47:00.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8254 21:47:00.891 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8255 21:47:00.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8256 21:47:00.891 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8257 21:47:00.891 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8258 21:47:00.891 0.00008217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8259 21:47:00.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8260 21:47:00.891 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8261 21:47:00.891 0.00008020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8262 21:47:00.891 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8263 21:47:00.891 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8264 21:47:00.891 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8265 21:47:00.891 0.00007704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8266 21:47:00.891 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 8267 21:47:00.891 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8268 21:47:00.891 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8269 21:47:00.891 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8270 21:47:00.891 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8271 21:47:00.891 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8272 21:47:00.891 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8273 21:47:00.891 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8274 21:47:00.891 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8275 21:47:00.891 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8276 21:47:00.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8277 21:47:00.891 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8278 21:47:00.891 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8279 21:47:00.891 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8280 21:47:00.891 0.02887705 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8281 21:47:00.922 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8282 21:47:00.922 0.01286993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8283 21:47:00.922 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8284 21:47:00.938 0.00035832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8285 21:47:00.938 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8286 21:47:00.938 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8287 21:47:00.938 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8288 21:47:00.938 0.00031644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 8289 21:47:00.938 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8290 21:47:00.938 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8291 21:47:00.938 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8292 21:47:00.938 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 8293 21:47:00.938 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8294 21:47:00.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8295 21:47:00.938 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8296 21:47:00.938 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8297 21:47:00.938 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8298 21:47:00.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8299 21:47:00.938 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8300 21:47:00.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 75 8301 21:47:00.938 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8302 21:47:00.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 8305 21:47:00.938 0.00035753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 8306 21:47:00.938 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8307 21:47:00.938 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8308 21:47:00.938 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8309 21:47:00.938 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8310 21:47:00.938 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8311 21:47:00.938 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8312 21:47:00.938 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 8313 21:47:00.938 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8314 21:47:00.938 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8315 21:47:00.938 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 8316 21:47:00.938 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8317 21:47:00.938 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8318 21:47:00.938 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8319 21:47:00.938 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8320 21:47:00.938 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8321 21:47:00.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8322 21:47:00.938 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8323 21:47:00.938 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8324 21:47:00.938 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8325 21:47:00.938 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8326 21:47:00.938 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8327 21:47:00.938 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8328 21:47:00.938 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8329 21:47:00.938 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8330 21:47:00.938 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8331 21:47:00.938 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8332 21:47:00.938 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8333 21:47:00.938 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8334 21:47:00.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8335 21:47:00.938 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8336 21:47:00.938 0.00033896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8337 21:47:00.938 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8338 21:47:00.938 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8339 21:47:00.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8340 21:47:00.938 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8341 21:47:00.938 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8342 21:47:00.938 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8343 21:47:00.938 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8344 21:47:00.938 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8345 21:47:00.938 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8346 21:47:00.938 0.02668999 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8347 21:47:00.969 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8348 21:47:00.969 0.01314529 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8349 21:47:00.969 0.00001106 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8350 21:47:00.984 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8351 21:47:00.984 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8352 21:47:00.984 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8353 21:47:00.984 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8354 21:47:00.984 0.00030064 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8355 21:47:00.984 0.00041600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 8356 21:47:00.984 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8357 21:47:00.984 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 8358 21:47:00.984 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8359 21:47:00.984 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8360 21:47:00.984 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8361 21:47:00.984 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8362 21:47:00.984 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8363 21:47:00.984 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8364 21:47:00.984 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8365 21:47:00.984 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8366 21:47:00.984 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8367 21:47:00.984 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8368 21:47:00.984 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8369 21:47:00.984 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8370 21:47:00.984 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8371 21:47:00.984 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8372 21:47:00.984 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8373 21:47:00.984 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8374 21:47:00.984 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8375 21:47:00.984 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 36 8376 21:47:00.984 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8377 21:47:00.984 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 8381 21:47:00.984 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8382 21:47:00.984 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8383 21:47:00.984 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8384 21:47:00.984 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8385 21:47:00.984 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8386 21:47:00.984 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8387 21:47:00.984 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8388 21:47:00.984 0.00021412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8389 21:47:00.984 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8390 21:47:00.984 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8391 21:47:00.984 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8392 21:47:00.984 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8393 21:47:00.984 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8394 21:47:00.984 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8395 21:47:00.984 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8396 21:47:00.984 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8397 21:47:00.984 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8398 21:47:00.984 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8399 21:47:00.984 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8400 21:47:00.984 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8401 21:47:00.984 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8402 21:47:00.984 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8403 21:47:00.984 0.00029827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8404 21:47:00.984 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8405 21:47:00.984 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8406 21:47:00.984 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8407 21:47:00.984 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8408 21:47:00.984 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8409 21:47:00.984 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8410 21:47:00.984 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8411 21:47:00.984 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8412 21:47:00.984 0.02611754 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8413 21:47:01.016 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8414 21:47:01.016 0.01486618 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8415 21:47:01.016 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8416 21:47:01.031 0.00037491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8417 21:47:01.031 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8418 21:47:01.031 0.00027417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8419 21:47:01.031 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8420 21:47:01.031 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8421 21:47:01.031 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8422 21:47:01.031 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 8423 21:47:01.031 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8424 21:47:01.031 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 8425 21:47:01.031 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8426 21:47:01.031 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8427 21:47:01.031 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8428 21:47:01.031 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8429 21:47:01.031 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8430 21:47:01.031 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8431 21:47:01.031 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8432 21:47:01.031 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8433 21:47:01.031 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8434 21:47:01.031 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8435 21:47:01.031 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8436 21:47:01.031 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8437 21:47:01.031 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8438 21:47:01.031 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8439 21:47:01.031 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8440 21:47:01.031 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8441 21:47:01.031 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8442 21:47:01.031 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8443 21:47:01.031 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8444 21:47:01.031 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8445 21:47:01.031 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8446 21:47:01.031 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8447 21:47:01.031 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8448 21:47:01.031 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8449 21:47:01.031 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8450 21:47:01.031 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8451 21:47:01.031 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8452 21:47:01.031 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8453 21:47:01.031 0.00027773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8454 21:47:01.031 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8455 21:47:01.031 0.00026311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8456 21:47:01.031 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8457 21:47:01.031 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8458 21:47:01.031 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8459 21:47:01.031 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8460 21:47:01.031 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8461 21:47:01.031 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8462 21:47:01.031 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8463 21:47:01.031 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8464 21:47:01.031 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8465 21:47:01.031 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8466 21:47:01.031 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8467 21:47:01.031 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8468 21:47:01.031 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8469 21:47:01.031 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8470 21:47:01.031 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8471 21:47:01.031 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8472 21:47:01.031 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8473 21:47:01.031 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8474 21:47:01.031 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8475 21:47:01.031 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8476 21:47:01.031 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8477 21:47:01.031 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8478 21:47:01.031 0.02666115 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8479 21:47:01.063 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8480 21:47:01.063 0.01300425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8481 21:47:01.063 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8482 21:47:01.078 0.00033580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8483 21:47:01.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8484 21:47:01.078 0.00030933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8485 21:47:01.078 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8486 21:47:01.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8487 21:47:01.078 0.00028879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8488 21:47:01.078 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 8489 21:47:01.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8490 21:47:01.078 0.00039862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8491 21:47:01.078 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 8492 21:47:01.078 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8493 21:47:01.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8494 21:47:01.078 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8495 21:47:01.078 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8496 21:47:01.078 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8497 21:47:01.078 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8498 21:47:01.078 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8499 21:47:01.078 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8500 21:47:01.078 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8501 21:47:01.078 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8502 21:47:01.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8503 21:47:01.078 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8504 21:47:01.078 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8505 21:47:01.078 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8506 21:47:01.078 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8507 21:47:01.078 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8508 21:47:01.078 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 8509 21:47:01.078 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8510 21:47:01.078 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 8511 21:47:01.078 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8512 21:47:01.078 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8513 21:47:01.078 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8514 21:47:01.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8515 21:47:01.078 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8516 21:47:01.078 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8517 21:47:01.078 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8518 21:47:01.078 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8519 21:47:01.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8520 21:47:01.078 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8522 21:47:01.078 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8523 21:47:01.078 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8524 21:47:01.078 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8525 21:47:01.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8526 21:47:01.078 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8527 21:47:01.078 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8528 21:47:01.078 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8529 21:47:01.078 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8530 21:47:01.078 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8531 21:47:01.078 0.00033383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8532 21:47:01.078 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8533 21:47:01.078 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8534 21:47:01.078 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8535 21:47:01.078 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8536 21:47:01.078 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8537 21:47:01.078 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8538 21:47:01.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8539 21:47:01.078 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8540 21:47:01.078 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8541 21:47:01.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8542 21:47:01.078 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8543 21:47:01.078 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8544 21:47:01.078 0.02759310 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8545 21:47:01.109 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8546 21:47:01.109 0.01341235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8547 21:47:01.109 0.00001422 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8548 21:47:01.125 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8549 21:47:01.125 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8550 21:47:01.125 0.00033541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8551 21:47:01.125 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8552 21:47:01.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8553 21:47:01.125 0.00029037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8554 21:47:01.125 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 8555 21:47:01.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8556 21:47:01.125 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8557 21:47:01.125 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 8558 21:47:01.125 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8559 21:47:01.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8560 21:47:01.125 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8561 21:47:01.125 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8562 21:47:01.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8563 21:47:01.125 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8564 21:47:01.125 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 8565 21:47:01.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8566 21:47:01.125 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8567 21:47:01.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8568 21:47:01.125 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8569 21:47:01.125 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8570 21:47:01.125 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8571 21:47:01.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8572 21:47:01.125 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8573 21:47:01.125 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8574 21:47:01.125 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8575 21:47:01.125 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8576 21:47:01.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8577 21:47:01.125 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8578 21:47:01.125 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 8579 21:47:01.125 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8580 21:47:01.125 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8581 21:47:01.125 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8582 21:47:01.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8583 21:47:01.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 43 8584 21:47:01.125 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8585 21:47:01.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8588 21:47:01.125 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8589 21:47:01.125 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8590 21:47:01.125 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8591 21:47:01.125 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8592 21:47:01.125 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8593 21:47:01.125 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8594 21:47:01.125 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8595 21:47:01.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8596 21:47:01.125 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8597 21:47:01.125 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8598 21:47:01.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8599 21:47:01.125 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8600 21:47:01.125 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8601 21:47:01.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8602 21:47:01.125 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8603 21:47:01.125 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8604 21:47:01.125 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8605 21:47:01.125 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8606 21:47:01.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8607 21:47:01.125 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8608 21:47:01.125 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8609 21:47:01.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8610 21:47:01.125 0.02746273 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8611 21:47:01.156 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8612 21:47:01.156 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8613 21:47:01.156 0.01391329 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8614 21:47:01.172 0.00040296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8615 21:47:01.172 0.00029630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8616 21:47:01.172 0.00024415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8617 21:47:01.172 0.00028958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 8618 21:47:01.172 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8619 21:47:01.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8620 21:47:01.172 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8621 21:47:01.172 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 8622 21:47:01.172 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8623 21:47:01.172 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8624 21:47:01.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8625 21:47:01.172 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8626 21:47:01.172 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8627 21:47:01.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8628 21:47:01.172 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8629 21:47:01.172 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8630 21:47:01.172 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8631 21:47:01.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8632 21:47:01.172 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8633 21:47:01.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8634 21:47:01.172 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8635 21:47:01.172 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8636 21:47:01.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8637 21:47:01.172 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8638 21:47:01.172 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8639 21:47:01.172 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 8640 21:47:01.172 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8641 21:47:01.172 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8642 21:47:01.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8643 21:47:01.172 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 8644 21:47:01.172 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8645 21:47:01.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8646 21:47:01.172 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8647 21:47:01.172 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8648 21:47:01.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8649 21:47:01.172 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8650 21:47:01.172 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8651 21:47:01.172 0.00094736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8652 21:47:01.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8653 21:47:01.172 0.00076563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8654 21:47:01.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8655 21:47:01.172 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8656 21:47:01.172 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8657 21:47:01.172 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8658 21:47:01.172 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8659 21:47:01.172 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8660 21:47:01.172 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8661 21:47:01.172 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8662 21:47:01.172 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8663 21:47:01.172 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8664 21:47:01.172 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8665 21:47:01.172 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8666 21:47:01.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8667 21:47:01.172 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8668 21:47:01.172 0.00022519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8669 21:47:01.172 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8670 21:47:01.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8671 21:47:01.172 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8672 21:47:01.172 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8673 21:47:01.172 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8674 21:47:01.172 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8675 21:47:01.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8676 21:47:01.172 0.02609147 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8677 21:47:01.203 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8678 21:47:01.203 0.01318124 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8679 21:47:01.203 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8680 21:47:01.219 0.00027299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8681 21:47:01.219 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8682 21:47:01.219 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8683 21:47:01.219 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8684 21:47:01.219 0.00027970 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8685 21:47:01.219 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 8686 21:47:01.219 0.00031289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8687 21:47:01.219 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8688 21:47:01.219 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8689 21:47:01.219 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8690 21:47:01.219 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8691 21:47:01.219 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8692 21:47:01.219 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8693 21:47:01.219 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8694 21:47:01.219 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8695 21:47:01.219 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8696 21:47:01.219 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8697 21:47:01.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8698 21:47:01.219 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8699 21:47:01.219 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8700 21:47:01.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8701 21:47:01.219 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8702 21:47:01.219 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8703 21:47:01.219 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8704 21:47:01.219 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8705 21:47:01.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8706 21:47:01.219 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8707 21:47:01.219 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 8709 21:47:01.219 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8710 21:47:01.219 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8711 21:47:01.219 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8712 21:47:01.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8713 21:47:01.219 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8714 21:47:01.219 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8715 21:47:01.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8716 21:47:01.219 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8717 21:47:01.219 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8718 21:47:01.219 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8719 21:47:01.219 0.00015605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8720 21:47:01.219 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8721 21:47:01.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8722 21:47:01.219 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8723 21:47:01.219 0.00031684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8724 21:47:01.219 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8725 21:47:01.219 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8726 21:47:01.219 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8727 21:47:01.219 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8728 21:47:01.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8729 21:47:01.219 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8730 21:47:01.219 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8731 21:47:01.219 0.00026430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8732 21:47:01.219 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8733 21:47:01.219 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8734 21:47:01.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8735 21:47:01.219 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8736 21:47:01.219 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8737 21:47:01.219 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8738 21:47:01.219 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8739 21:47:01.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8740 21:47:01.219 0.02634273 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8741 21:47:01.250 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8742 21:47:01.250 0.01387931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8743 21:47:01.250 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8744 21:47:01.266 0.00034963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8745 21:47:01.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8746 21:47:01.266 0.00045353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8747 21:47:01.266 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8748 21:47:01.266 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 8749 21:47:01.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8750 21:47:01.266 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8751 21:47:01.266 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8752 21:47:01.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8753 21:47:01.266 0.00020583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8756 21:47:01.266 0.00026825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8757 21:47:01.266 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8758 21:47:01.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8759 21:47:01.266 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8760 21:47:01.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8761 21:47:01.266 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8762 21:47:01.266 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8763 21:47:01.266 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8764 21:47:01.266 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8765 21:47:01.266 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8766 21:47:01.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8767 21:47:01.266 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8768 21:47:01.266 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8769 21:47:01.266 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 8770 21:47:01.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8771 21:47:01.266 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8772 21:47:01.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8773 21:47:01.266 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 8774 21:47:01.266 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8775 21:47:01.266 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8776 21:47:01.266 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8777 21:47:01.266 0.00038835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8778 21:47:01.266 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8779 21:47:01.266 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8780 21:47:01.266 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8781 21:47:01.266 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8782 21:47:01.266 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8783 21:47:01.266 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8784 21:47:01.266 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8785 21:47:01.266 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8786 21:47:01.266 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8788 21:47:01.266 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8789 21:47:01.266 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8790 21:47:01.266 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8791 21:47:01.266 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8792 21:47:01.266 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8793 21:47:01.266 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8794 21:47:01.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8795 21:47:01.266 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8796 21:47:01.266 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8797 21:47:01.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8798 21:47:01.266 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8799 21:47:01.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8800 21:47:01.266 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8801 21:47:01.266 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8802 21:47:01.266 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8803 21:47:01.266 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8804 21:47:01.266 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8805 21:47:01.266 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8806 21:47:01.266 0.02590500 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8807 21:47:01.297 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8808 21:47:01.297 0.01442450 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8809 21:47:01.297 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8810 21:47:01.313 0.00036188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8811 21:47:01.313 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8812 21:47:01.313 0.00027654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8813 21:47:01.313 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8814 21:47:01.313 0.00033264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 8815 21:47:01.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8816 21:47:01.313 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8817 21:47:01.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8818 21:47:01.313 0.00037570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8819 21:47:01.313 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8820 21:47:01.313 0.00032277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8821 21:47:01.313 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8822 21:47:01.313 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8823 21:47:01.313 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8824 21:47:01.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8825 21:47:01.313 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8826 21:47:01.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8827 21:47:01.313 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8828 21:47:01.313 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 8829 21:47:01.313 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8830 21:47:01.313 0.00027694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8831 21:47:01.313 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8832 21:47:01.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8833 21:47:01.313 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8835 21:47:01.313 0.00035437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8836 21:47:01.313 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8837 21:47:01.313 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8838 21:47:01.313 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 8839 21:47:01.313 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8840 21:47:01.313 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8841 21:47:01.313 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 46 8842 21:47:01.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8843 21:47:01.313 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8844 21:47:01.313 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8845 21:47:01.313 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8846 21:47:01.313 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8847 21:47:01.313 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8848 21:47:01.313 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8849 21:47:01.313 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8850 21:47:01.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8851 21:47:01.313 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8852 21:47:01.313 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8853 21:47:01.313 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8854 21:47:01.313 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8855 21:47:01.313 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8856 21:47:01.313 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8857 21:47:01.313 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8858 21:47:01.313 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8859 21:47:01.313 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8860 21:47:01.313 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8861 21:47:01.313 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8862 21:47:01.313 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8863 21:47:01.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8864 21:47:01.313 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8865 21:47:01.313 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8866 21:47:01.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8867 21:47:01.313 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8868 21:47:01.313 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 8869 21:47:01.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8870 21:47:01.313 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8871 21:47:01.313 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8872 21:47:01.313 0.02658727 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8873 21:47:01.344 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8874 21:47:01.344 0.01343013 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8875 21:47:01.344 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8876 21:47:01.360 0.00028168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8877 21:47:01.360 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8878 21:47:01.360 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8879 21:47:01.360 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8880 21:47:01.360 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8881 21:47:01.360 0.00038163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 8882 21:47:01.360 0.00039348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8883 21:47:01.360 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8884 21:47:01.360 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8885 21:47:01.360 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8886 21:47:01.360 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8887 21:47:01.360 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8888 21:47:01.360 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8889 21:47:01.360 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 8890 21:47:01.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8891 21:47:01.360 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8892 21:47:01.360 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8893 21:47:01.360 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8894 21:47:01.360 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 8895 21:47:01.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8896 21:47:01.360 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 8897 21:47:01.360 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8898 21:47:01.360 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8899 21:47:01.360 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8900 21:47:01.360 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8901 21:47:01.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8902 21:47:01.360 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8903 21:47:01.360 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 8904 21:47:01.360 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8905 21:47:01.360 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 8906 21:47:01.360 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8907 21:47:01.360 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8908 21:47:01.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8909 21:47:01.360 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8910 21:47:01.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8911 21:47:01.360 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8912 21:47:01.360 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8913 21:47:01.360 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8914 21:47:01.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8915 21:47:01.360 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8916 21:47:01.360 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8917 21:47:01.360 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8918 21:47:01.360 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8919 21:47:01.360 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8920 21:47:01.360 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8921 21:47:01.360 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8922 21:47:01.360 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8923 21:47:01.360 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8924 21:47:01.360 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8925 21:47:01.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8926 21:47:01.360 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8927 21:47:01.360 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8928 21:47:01.360 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8929 21:47:01.360 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8930 21:47:01.360 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8931 21:47:01.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8932 21:47:01.360 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8933 21:47:01.360 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8934 21:47:01.360 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8935 21:47:01.360 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 8936 21:47:01.360 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8937 21:47:01.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8938 21:47:01.360 0.02781552 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8939 21:47:01.391 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8940 21:47:01.391 0.01302875 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8941 21:47:01.391 0.00000395 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 8942 21:47:01.407 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 8943 21:47:01.407 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8944 21:47:01.407 0.00036859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8945 21:47:01.407 0.00026864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 8946 21:47:01.407 0.00024849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 8947 21:47:01.407 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8948 21:47:01.407 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8949 21:47:01.407 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8950 21:47:01.407 0.00036306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8951 21:47:01.407 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 8952 21:47:01.407 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8953 21:47:01.407 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8954 21:47:01.407 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 8955 21:47:01.407 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8956 21:47:01.407 0.00029353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8957 21:47:01.407 0.00027970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8958 21:47:01.407 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8959 21:47:01.407 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8960 21:47:01.407 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8961 21:47:01.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8962 21:47:01.407 0.00029472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8963 21:47:01.407 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 8964 21:47:01.407 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8965 21:47:01.407 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8966 21:47:01.407 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8967 21:47:01.407 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8968 21:47:01.407 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8969 21:47:01.407 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8970 21:47:01.407 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8971 21:47:01.407 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8973 21:47:01.407 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8974 21:47:01.407 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8975 21:47:01.407 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 8976 21:47:01.407 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8977 21:47:01.407 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 8978 21:47:01.407 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8979 21:47:01.407 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8980 21:47:01.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8981 21:47:01.407 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8982 21:47:01.407 0.00009047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8983 21:47:01.407 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8984 21:47:01.407 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8985 21:47:01.407 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8986 21:47:01.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8987 21:47:01.407 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8988 21:47:01.407 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8989 21:47:01.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8990 21:47:01.407 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8991 21:47:01.407 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8992 21:47:01.407 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8993 21:47:01.407 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8994 21:47:01.407 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 8995 21:47:01.407 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8996 21:47:01.407 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 8997 21:47:01.407 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 8998 21:47:01.407 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8999 21:47:01.407 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9000 21:47:01.407 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 9001 21:47:01.407 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9002 21:47:01.407 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9003 21:47:01.407 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9004 21:47:01.407 0.02607290 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9005 21:47:01.438 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9006 21:47:01.438 0.01463309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9007 21:47:01.438 0.00001422 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9008 21:47:01.454 0.00034805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9009 21:47:01.454 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9010 21:47:01.454 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9011 21:47:01.454 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9012 21:47:01.454 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9013 21:47:01.454 0.00037096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9014 21:47:01.454 0.00031407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9015 21:47:01.454 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9016 21:47:01.454 0.00042351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9017 21:47:01.454 0.00031921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 9018 21:47:01.454 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9019 21:47:01.454 0.00027338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9020 21:47:01.454 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9021 21:47:01.454 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9022 21:47:01.454 0.00034173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9023 21:47:01.454 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 9024 21:47:01.454 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9025 21:47:01.454 0.00034489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9026 21:47:01.454 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9027 21:47:01.454 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9028 21:47:01.454 0.00033975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9029 21:47:01.454 0.00030499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9030 21:47:01.454 0.00030459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9031 21:47:01.454 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9032 21:47:01.454 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9033 21:47:01.454 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 9034 21:47:01.454 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9035 21:47:01.454 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9036 21:47:01.454 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9037 21:47:01.454 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9038 21:47:01.454 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 9039 21:47:01.454 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9040 21:47:01.454 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9041 21:47:01.454 0.00028681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9042 21:47:01.454 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9044 21:47:01.454 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9045 21:47:01.454 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9046 21:47:01.454 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9047 21:47:01.454 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9048 21:47:01.454 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9049 21:47:01.454 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9050 21:47:01.454 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9051 21:47:01.454 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9052 21:47:01.454 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9053 21:47:01.454 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9054 21:47:01.454 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9055 21:47:01.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9056 21:47:01.454 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9057 21:47:01.454 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9058 21:47:01.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9059 21:47:01.454 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9060 21:47:01.454 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9061 21:47:01.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9062 21:47:01.454 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9063 21:47:01.454 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9064 21:47:01.454 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9065 21:47:01.454 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9066 21:47:01.454 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9067 21:47:01.454 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9068 21:47:01.454 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9069 21:47:01.454 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9070 21:47:01.454 0.02626529 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9071 21:47:01.485 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9072 21:47:01.485 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9073 21:47:01.485 0.01392475 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9074 21:47:01.501 0.00029946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9075 21:47:01.501 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9076 21:47:01.501 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9077 21:47:01.501 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9078 21:47:01.501 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9079 21:47:01.501 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9080 21:47:01.501 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9081 21:47:01.501 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9082 21:47:01.501 0.00041877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9083 21:47:01.501 0.00030578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 9084 21:47:01.501 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9085 21:47:01.501 0.00036662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9086 21:47:01.501 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9087 21:47:01.501 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9088 21:47:01.501 0.00032711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9089 21:47:01.501 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9090 21:47:01.501 0.00033896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 9091 21:47:01.501 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9092 21:47:01.501 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9093 21:47:01.501 0.00063802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 9094 21:47:01.501 0.00038242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9095 21:47:01.501 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9096 21:47:01.501 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9097 21:47:01.501 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9098 21:47:01.501 0.00024533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 9099 21:47:01.501 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9100 21:47:01.501 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9101 21:47:01.501 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 9104 21:47:01.501 0.00039980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 9105 21:47:01.501 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 9106 21:47:01.501 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9107 21:47:01.501 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9108 21:47:01.501 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 9109 21:47:01.501 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9110 21:47:01.501 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9111 21:47:01.501 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9112 21:47:01.501 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9113 21:47:01.501 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9114 21:47:01.501 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9115 21:47:01.501 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9116 21:47:01.501 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9117 21:47:01.501 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9118 21:47:01.501 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9119 21:47:01.501 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9120 21:47:01.501 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9121 21:47:01.501 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9122 21:47:01.501 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9123 21:47:01.501 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9124 21:47:01.501 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9125 21:47:01.501 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9126 21:47:01.501 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9127 21:47:01.501 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9128 21:47:01.501 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9129 21:47:01.501 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 9130 21:47:01.501 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9131 21:47:01.501 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9132 21:47:01.501 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 9133 21:47:01.501 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9134 21:47:01.501 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9135 21:47:01.501 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9136 21:47:01.501 0.02389176 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9137 21:47:01.532 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9138 21:47:01.532 0.01491635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9139 21:47:01.532 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9140 21:47:01.547 0.00031565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9141 21:47:01.547 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9142 21:47:01.547 0.00029551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9143 21:47:01.547 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9144 21:47:01.547 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9145 21:47:01.547 0.00032079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9146 21:47:01.547 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9147 21:47:01.547 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9148 21:47:01.547 0.00035832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9149 21:47:01.547 0.00034370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 9150 21:47:01.547 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9151 21:47:01.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9152 21:47:01.547 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9153 21:47:01.547 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 9154 21:47:01.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9155 21:47:01.547 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9156 21:47:01.547 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9157 21:47:01.547 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9158 21:47:01.547 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9159 21:47:01.547 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9160 21:47:01.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9161 21:47:01.547 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9162 21:47:01.547 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9163 21:47:01.547 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9164 21:47:01.547 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9165 21:47:01.547 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 9166 21:47:01.547 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9167 21:47:01.547 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9168 21:47:01.547 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 9169 21:47:01.547 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9170 21:47:01.547 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9171 21:47:01.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9172 21:47:01.547 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9173 21:47:01.547 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9174 21:47:01.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9175 21:47:01.547 0.00023032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9176 21:47:01.547 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9177 21:47:01.547 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9178 21:47:01.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9179 21:47:01.547 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9180 21:47:01.547 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9181 21:47:01.547 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9182 21:47:01.547 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9183 21:47:01.547 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9184 21:47:01.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9185 21:47:01.547 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9186 21:47:01.547 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9187 21:47:01.547 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9188 21:47:01.547 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9189 21:47:01.547 0.00025165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9190 21:47:01.547 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9191 21:47:01.547 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9192 21:47:01.547 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9193 21:47:01.547 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9194 21:47:01.547 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9195 21:47:01.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9196 21:47:01.547 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9197 21:47:01.547 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9198 21:47:01.547 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 9199 21:47:01.547 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9201 21:47:01.547 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9202 21:47:01.547 0.02591013 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9203 21:47:01.579 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9204 21:47:01.579 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9205 21:47:01.579 0.01495862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9206 21:47:01.594 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9207 21:47:01.594 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9208 21:47:01.594 0.00035951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9209 21:47:01.594 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9210 21:47:01.594 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9211 21:47:01.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9212 21:47:01.594 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9213 21:47:01.594 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9214 21:47:01.594 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 9215 21:47:01.594 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9216 21:47:01.594 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9217 21:47:01.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9218 21:47:01.594 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9219 21:47:01.594 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9220 21:47:01.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9221 21:47:01.594 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9222 21:47:01.594 0.00009047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9223 21:47:01.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9224 21:47:01.594 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9225 21:47:01.594 0.00027654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 9226 21:47:01.594 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9227 21:47:01.594 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9228 21:47:01.594 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 9229 21:47:01.594 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9230 21:47:01.594 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9231 21:47:01.594 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9232 21:47:01.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9233 21:47:01.594 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9234 21:47:01.594 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9235 21:47:01.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9236 21:47:01.594 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9237 21:47:01.594 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 9238 21:47:01.594 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9239 21:47:01.594 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9240 21:47:01.594 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 9241 21:47:01.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9242 21:47:01.594 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9243 21:47:01.594 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9244 21:47:01.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9245 21:47:01.594 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9246 21:47:01.594 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9247 21:47:01.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9248 21:47:01.594 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9249 21:47:01.594 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 9250 21:47:01.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9251 21:47:01.594 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9255 21:47:01.594 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9256 21:47:01.594 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9257 21:47:01.594 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9258 21:47:01.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9259 21:47:01.594 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9260 21:47:01.594 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9261 21:47:01.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9262 21:47:01.594 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9263 21:47:01.594 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 9264 21:47:01.594 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 9265 21:47:01.594 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9266 21:47:01.594 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9267 21:47:01.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9268 21:47:01.594 0.02670026 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9269 21:47:01.625 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9270 21:47:01.625 0.01314213 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9271 21:47:01.625 0.00009205 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9272 21:47:01.641 0.00035319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9273 21:47:01.641 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9274 21:47:01.641 0.00043338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9275 21:47:01.641 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9276 21:47:01.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9277 21:47:01.641 0.00036859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9278 21:47:01.641 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9279 21:47:01.641 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9280 21:47:01.641 0.00030854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9281 21:47:01.641 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 9282 21:47:01.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9283 21:47:01.641 0.00050489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9284 21:47:01.641 0.00038005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9285 21:47:01.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9286 21:47:01.641 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9287 21:47:01.641 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 9288 21:47:01.641 0.00036583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9289 21:47:01.641 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9290 21:47:01.641 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9291 21:47:01.641 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9292 21:47:01.641 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9293 21:47:01.641 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9294 21:47:01.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9295 21:47:01.641 0.00022400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9296 21:47:01.641 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9297 21:47:01.641 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 9298 21:47:01.641 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9299 21:47:01.641 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9300 21:47:01.641 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 9301 21:47:01.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9302 21:47:01.641 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9303 21:47:01.641 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9304 21:47:01.641 0.00025284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9305 21:47:01.641 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9306 21:47:01.641 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9307 21:47:01.641 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9308 21:47:01.641 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9309 21:47:01.641 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9310 21:47:01.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9311 21:47:01.641 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9312 21:47:01.641 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9313 21:47:01.641 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9314 21:47:01.641 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9315 21:47:01.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9316 21:47:01.641 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9317 21:47:01.641 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9318 21:47:01.641 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9319 21:47:01.641 0.00025363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9320 21:47:01.641 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9321 21:47:01.641 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9322 21:47:01.641 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9323 21:47:01.641 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9324 21:47:01.641 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9325 21:47:01.641 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9326 21:47:01.641 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9327 21:47:01.641 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9328 21:47:01.641 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9329 21:47:01.641 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9330 21:47:01.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9331 21:47:01.641 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9332 21:47:01.641 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9333 21:47:01.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9334 21:47:01.641 0.02569917 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9335 21:47:01.672 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9336 21:47:01.672 0.01468406 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9337 21:47:01.672 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9338 21:47:01.688 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9339 21:47:01.688 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9340 21:47:01.688 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9341 21:47:01.688 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9342 21:47:01.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9343 21:47:01.688 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9344 21:47:01.688 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9345 21:47:01.688 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9346 21:47:01.688 0.00026074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9347 21:47:01.688 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9348 21:47:01.688 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9349 21:47:01.688 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9350 21:47:01.688 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9351 21:47:01.688 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9352 21:47:01.688 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9353 21:47:01.688 0.00031723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9354 21:47:01.688 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 9355 21:47:01.688 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9356 21:47:01.688 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9357 21:47:01.688 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 9358 21:47:01.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9359 21:47:01.688 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9360 21:47:01.688 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9361 21:47:01.688 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9362 21:47:01.688 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 9363 21:47:01.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9364 21:47:01.688 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9365 21:47:01.688 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9366 21:47:01.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9367 21:47:01.688 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 9368 21:47:01.688 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9369 21:47:01.688 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9370 21:47:01.688 0.00031052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9371 21:47:01.688 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 47 9372 21:47:01.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9373 21:47:01.688 0.00029748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9374 21:47:01.688 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 9375 21:47:01.688 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9376 21:47:01.688 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9377 21:47:01.688 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9378 21:47:01.688 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9379 21:47:01.688 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9380 21:47:01.688 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9381 21:47:01.688 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9382 21:47:01.688 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9383 21:47:01.688 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9384 21:47:01.688 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 9385 21:47:01.688 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9388 21:47:01.688 0.00028800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9389 21:47:01.688 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9390 21:47:01.688 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9391 21:47:01.688 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9392 21:47:01.688 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9393 21:47:01.688 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 9394 21:47:01.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9395 21:47:01.688 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9396 21:47:01.688 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 9397 21:47:01.688 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9398 21:47:01.688 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9399 21:47:01.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9400 21:47:01.688 0.02844643 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9401 21:47:01.719 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9402 21:47:01.719 0.01259181 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9403 21:47:01.719 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9404 21:47:01.735 0.00062341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9405 21:47:01.735 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9406 21:47:01.735 0.00035753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9407 21:47:01.735 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9408 21:47:01.735 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9409 21:47:01.735 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9410 21:47:01.735 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9411 21:47:01.735 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9412 21:47:01.735 0.00038874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9413 21:47:01.735 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9414 21:47:01.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9415 21:47:01.735 0.00033027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9416 21:47:01.735 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9417 21:47:01.735 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9418 21:47:01.735 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 4C 9419 21:47:01.735 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9422 21:47:01.735 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9423 21:47:01.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9424 21:47:01.735 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9425 21:47:01.735 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9426 21:47:01.735 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9427 21:47:01.735 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 9428 21:47:01.735 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9431 21:47:01.735 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9432 21:47:01.735 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 9433 21:47:01.735 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9434 21:47:01.735 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9435 21:47:01.735 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9436 21:47:01.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9437 21:47:01.735 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9438 21:47:01.735 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9439 21:47:01.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9440 21:47:01.735 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9441 21:47:01.735 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9442 21:47:01.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9443 21:47:01.735 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9444 21:47:01.735 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9445 21:47:01.735 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9446 21:47:01.735 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9447 21:47:01.735 0.00007901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9448 21:47:01.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9449 21:47:01.735 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9450 21:47:01.735 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9451 21:47:01.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9452 21:47:01.735 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9453 21:47:01.735 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9454 21:47:01.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9455 21:47:01.735 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9456 21:47:01.735 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9457 21:47:01.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9458 21:47:01.735 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9459 21:47:01.735 0.00032711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9460 21:47:01.735 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9461 21:47:01.735 0.00026114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9462 21:47:01.735 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9463 21:47:01.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9464 21:47:01.735 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9465 21:47:01.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9466 21:47:01.735 0.02597413 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9467 21:47:01.766 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9468 21:47:01.766 0.01421591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9469 21:47:01.766 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9470 21:47:01.782 0.00063605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9471 21:47:01.782 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9472 21:47:01.782 0.00034489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9473 21:47:01.782 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9474 21:47:01.782 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9475 21:47:01.782 0.00036899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9476 21:47:01.782 0.00030380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9477 21:47:01.782 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9478 21:47:01.782 0.00036504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9479 21:47:01.782 0.00036701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9480 21:47:01.782 0.00031644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9481 21:47:01.782 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9482 21:47:01.782 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9483 21:47:01.782 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9484 21:47:01.782 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9485 21:47:01.782 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9486 21:47:01.782 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9487 21:47:01.782 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9488 21:47:01.782 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9489 21:47:01.782 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9490 21:47:01.782 0.00034410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9491 21:47:01.782 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9492 21:47:01.782 0.00029669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9493 21:47:01.782 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9494 21:47:01.782 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9495 21:47:01.782 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9496 21:47:01.782 0.00042232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9497 21:47:01.782 0.00033778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9498 21:47:01.782 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9499 21:47:01.782 0.00034291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9500 21:47:01.782 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9501 21:47:01.782 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9502 21:47:01.782 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9503 21:47:01.782 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9504 21:47:01.782 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9505 21:47:01.782 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9506 21:47:01.782 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9507 21:47:01.782 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9508 21:47:01.782 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9509 21:47:01.782 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9510 21:47:01.782 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9511 21:47:01.782 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9512 21:47:01.782 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9513 21:47:01.782 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9514 21:47:01.782 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9515 21:47:01.782 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9516 21:47:01.782 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9517 21:47:01.782 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9518 21:47:01.782 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9519 21:47:01.782 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9520 21:47:01.782 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9521 21:47:01.782 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9522 21:47:01.782 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9523 21:47:01.782 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9524 21:47:01.782 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9525 21:47:01.782 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 9526 21:47:01.782 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9527 21:47:01.782 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9529 21:47:01.782 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9530 21:47:01.782 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9531 21:47:01.782 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9532 21:47:01.782 0.02638263 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9533 21:47:01.812 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9534 21:47:01.812 0.01252307 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9535 21:47:01.812 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9536 21:47:01.828 0.00030301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9537 21:47:01.828 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9538 21:47:01.828 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9539 21:47:01.828 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9543 21:47:01.828 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9544 21:47:01.828 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9545 21:47:01.828 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9546 21:47:01.828 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9547 21:47:01.828 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9548 21:47:01.828 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9549 21:47:01.828 0.00037649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9550 21:47:01.828 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9551 21:47:01.828 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9552 21:47:01.828 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9553 21:47:01.828 0.00031881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9554 21:47:01.828 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9555 21:47:01.828 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9556 21:47:01.828 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9557 21:47:01.828 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9558 21:47:01.828 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9559 21:47:01.828 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9560 21:47:01.828 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9561 21:47:01.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9562 21:47:01.828 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9563 21:47:01.828 0.00027022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9564 21:47:01.828 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9565 21:47:01.828 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9566 21:47:01.828 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9567 21:47:01.828 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9568 21:47:01.828 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9569 21:47:01.828 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9570 21:47:01.828 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9571 21:47:01.828 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9572 21:47:01.828 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9573 21:47:01.828 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9574 21:47:01.828 0.00038440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9575 21:47:01.828 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9576 21:47:01.828 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9577 21:47:01.828 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9578 21:47:01.828 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9579 21:47:01.828 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9580 21:47:01.828 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9581 21:47:01.828 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9582 21:47:01.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9583 21:47:01.828 0.00023348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9584 21:47:01.828 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9585 21:47:01.828 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9586 21:47:01.828 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9587 21:47:01.828 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9588 21:47:01.828 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9589 21:47:01.828 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9590 21:47:01.828 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9591 21:47:01.828 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9592 21:47:01.828 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9593 21:47:01.828 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9594 21:47:01.828 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9595 21:47:01.828 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9596 21:47:01.828 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9597 21:47:01.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9598 21:47:01.828 0.02549532 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9599 21:47:01.859 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9600 21:47:01.859 0.01434983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9601 21:47:01.859 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9602 21:47:01.875 0.00027931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9603 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9604 21:47:01.875 0.00028840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9605 21:47:01.875 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9606 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9607 21:47:01.875 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9608 21:47:01.875 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9609 21:47:01.875 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9610 21:47:01.875 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9611 21:47:01.875 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 9612 21:47:01.875 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9613 21:47:01.875 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9614 21:47:01.875 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9615 21:47:01.875 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9616 21:47:01.875 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9617 21:47:01.875 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 9618 21:47:01.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9619 21:47:01.875 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9620 21:47:01.875 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9621 21:47:01.875 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9622 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9623 21:47:01.875 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9624 21:47:01.875 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9625 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9626 21:47:01.875 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 9627 21:47:01.875 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9628 21:47:01.875 0.00008178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9629 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9630 21:47:01.875 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9631 21:47:01.875 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9632 21:47:01.875 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9633 21:47:01.875 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9634 21:47:01.875 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9635 21:47:01.875 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9636 21:47:01.875 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9637 21:47:01.875 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9638 21:47:01.875 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9639 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9640 21:47:01.875 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9641 21:47:01.875 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9642 21:47:01.875 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9643 21:47:01.875 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9644 21:47:01.875 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9645 21:47:01.875 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9646 21:47:01.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9647 21:47:01.875 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9648 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9649 21:47:01.875 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9650 21:47:01.875 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9651 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9652 21:47:01.875 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9653 21:47:01.875 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9654 21:47:01.875 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9655 21:47:01.875 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9656 21:47:01.875 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9657 21:47:01.875 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 9658 21:47:01.875 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9659 21:47:01.875 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9660 21:47:01.875 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9661 21:47:01.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9662 21:47:01.875 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9663 21:47:01.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9664 21:47:01.875 0.02712653 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9665 21:47:01.906 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9666 21:47:01.906 0.01353087 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9667 21:47:01.906 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9668 21:47:01.922 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9669 21:47:01.922 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9670 21:47:01.922 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9671 21:47:01.922 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9672 21:47:01.922 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9673 21:47:01.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9674 21:47:01.922 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9675 21:47:01.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9676 21:47:01.922 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9677 21:47:01.922 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 9678 21:47:01.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9679 21:47:01.922 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9680 21:47:01.922 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9681 21:47:01.922 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9682 21:47:01.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9683 21:47:01.922 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9684 21:47:01.922 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 9685 21:47:01.922 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9686 21:47:01.922 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 9687 21:47:01.922 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9688 21:47:01.922 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9689 21:47:01.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9690 21:47:01.922 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9691 21:47:01.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9692 21:47:01.922 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9693 21:47:01.922 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 9694 21:47:01.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9695 21:47:01.922 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9696 21:47:01.922 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9697 21:47:01.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9698 21:47:01.922 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9699 21:47:01.922 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9700 21:47:01.922 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9701 21:47:01.922 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9702 21:47:01.922 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 9703 21:47:01.922 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9704 21:47:01.922 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9706 21:47:01.922 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9707 21:47:01.922 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9708 21:47:01.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9709 21:47:01.922 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9710 21:47:01.922 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9711 21:47:01.922 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9712 21:47:01.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9713 21:47:01.922 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9714 21:47:01.922 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9715 21:47:01.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9716 21:47:01.922 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9717 21:47:01.922 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9718 21:47:01.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9719 21:47:01.922 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9720 21:47:01.922 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9721 21:47:01.922 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9722 21:47:01.922 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9723 21:47:01.922 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9724 21:47:01.922 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9725 21:47:01.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9726 21:47:01.922 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9727 21:47:01.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9728 21:47:01.922 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9731 21:47:01.953 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9732 21:47:01.953 0.01462401 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9733 21:47:01.953 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9734 21:47:01.969 0.00034173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9735 21:47:01.969 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9736 21:47:01.969 0.00033146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9737 21:47:01.969 0.00027931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9738 21:47:01.969 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9739 21:47:01.969 0.00034765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9740 21:47:01.969 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9741 21:47:01.969 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 9742 21:47:01.969 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9743 21:47:01.969 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9744 21:47:01.969 0.00025165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9745 21:47:01.969 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9746 21:47:01.969 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9747 21:47:01.969 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9748 21:47:01.969 0.00043891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 9749 21:47:01.969 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9750 21:47:01.969 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 9751 21:47:01.969 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9752 21:47:01.969 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9753 21:47:01.969 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9754 21:47:01.969 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9755 21:47:01.969 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9756 21:47:01.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9757 21:47:01.969 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9758 21:47:01.969 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9759 21:47:01.969 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 9760 21:47:01.969 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9761 21:47:01.969 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9762 21:47:01.969 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 9763 21:47:01.969 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9764 21:47:01.969 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9765 21:47:01.969 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9766 21:47:01.969 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9767 21:47:01.969 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9768 21:47:01.969 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9769 21:47:01.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9770 21:47:01.969 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9771 21:47:01.969 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9772 21:47:01.969 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9773 21:47:01.969 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9774 21:47:01.969 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9775 21:47:01.969 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9776 21:47:01.969 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9777 21:47:01.969 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 9778 21:47:01.969 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9779 21:47:01.969 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9782 21:47:01.969 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9783 21:47:01.969 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9784 21:47:01.969 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9785 21:47:01.969 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9786 21:47:01.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9787 21:47:01.969 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9788 21:47:01.969 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9789 21:47:01.969 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9790 21:47:01.969 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 9791 21:47:01.969 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9792 21:47:01.969 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9793 21:47:01.969 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9794 21:47:01.969 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9795 21:47:01.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9796 21:47:01.969 0.02658648 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9797 21:47:02.000 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9798 21:47:02.000 0.01359526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9799 21:47:02.000 0.00001817 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9800 21:47:02.016 0.00041758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9801 21:47:02.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9802 21:47:02.016 0.00043457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9803 21:47:02.016 0.00029748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9804 21:47:02.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9805 21:47:02.016 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9806 21:47:02.016 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9807 21:47:02.016 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 9808 21:47:02.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9809 21:47:02.016 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9810 21:47:02.016 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9811 21:47:02.016 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9812 21:47:02.016 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9813 21:47:02.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9814 21:47:02.016 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9815 21:47:02.016 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9816 21:47:02.016 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 9817 21:47:02.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9818 21:47:02.016 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9819 21:47:02.016 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9820 21:47:02.016 0.00031447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9821 21:47:02.016 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 9822 21:47:02.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9823 21:47:02.016 0.00028919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9824 21:47:02.016 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9825 21:47:02.016 0.00027536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 9826 21:47:02.016 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9827 21:47:02.016 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9829 21:47:02.016 0.00045314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9830 21:47:02.016 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9831 21:47:02.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9832 21:47:02.016 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9833 21:47:02.016 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9834 21:47:02.016 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9835 21:47:02.016 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9836 21:47:02.016 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9837 21:47:02.016 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9838 21:47:02.016 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9839 21:47:02.016 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9840 21:47:02.016 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9841 21:47:02.016 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9842 21:47:02.016 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9843 21:47:02.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9844 21:47:02.016 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9845 21:47:02.016 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9846 21:47:02.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9847 21:47:02.016 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9848 21:47:02.016 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9849 21:47:02.016 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9850 21:47:02.016 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9851 21:47:02.016 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9852 21:47:02.016 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9853 21:47:02.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9854 21:47:02.016 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9855 21:47:02.016 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9856 21:47:02.016 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9857 21:47:02.016 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9858 21:47:02.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9859 21:47:02.016 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9860 21:47:02.016 0.00024770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9861 21:47:02.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9862 21:47:02.016 0.02585048 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9863 21:47:02.047 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9864 21:47:02.047 0.01424238 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9865 21:47:02.047 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9866 21:47:02.063 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9867 21:47:02.063 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9868 21:47:02.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9869 21:47:02.063 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9870 21:47:02.063 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 9871 21:47:02.063 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9872 21:47:02.063 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9873 21:47:02.063 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 9874 21:47:02.063 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9875 21:47:02.063 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9876 21:47:02.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9877 21:47:02.063 0.00029985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9878 21:47:02.063 0.00040257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9879 21:47:02.063 0.00032632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 9880 21:47:02.063 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9881 21:47:02.063 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9882 21:47:02.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9883 21:47:02.063 0.00031842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9885 21:47:02.063 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9886 21:47:02.063 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9887 21:47:02.063 0.00033422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9888 21:47:02.063 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9889 21:47:02.063 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9890 21:47:02.063 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9891 21:47:02.063 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 9892 21:47:02.063 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9893 21:47:02.063 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9894 21:47:02.063 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9895 21:47:02.063 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9896 21:47:02.063 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 9897 21:47:02.063 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 9898 21:47:02.063 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9899 21:47:02.063 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9900 21:47:02.063 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9901 21:47:02.063 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9902 21:47:02.063 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9903 21:47:02.063 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9904 21:47:02.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9905 21:47:02.063 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9906 21:47:02.063 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9907 21:47:02.063 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9908 21:47:02.063 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9909 21:47:02.063 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9910 21:47:02.063 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9911 21:47:02.063 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9912 21:47:02.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9913 21:47:02.063 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9914 21:47:02.063 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9915 21:47:02.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9916 21:47:02.063 0.00024889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9917 21:47:02.063 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9918 21:47:02.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9919 21:47:02.063 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 9920 21:47:02.063 0.00025086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9921 21:47:02.063 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 9922 21:47:02.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9923 21:47:02.063 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9924 21:47:02.063 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 9925 21:47:02.063 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9926 21:47:02.063 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9927 21:47:02.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9928 21:47:02.063 0.02647073 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9929 21:47:02.094 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9930 21:47:02.094 0.01344988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9931 21:47:02.094 0.00001462 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9932 21:47:02.110 0.00028563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9933 21:47:02.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9934 21:47:02.110 0.00029827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9935 21:47:02.110 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 9936 21:47:02.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9937 21:47:02.110 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9938 21:47:02.110 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 9939 21:47:02.110 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9940 21:47:02.110 0.00027773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9941 21:47:02.110 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 9942 21:47:02.110 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9943 21:47:02.110 0.00037412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9944 21:47:02.110 0.00031644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 9945 21:47:02.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9946 21:47:02.110 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9947 21:47:02.110 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 9948 21:47:02.110 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9949 21:47:02.110 0.00036662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 9950 21:47:02.110 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9951 21:47:02.110 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 9952 21:47:02.110 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9953 21:47:02.110 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9954 21:47:02.110 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9955 21:47:02.110 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9956 21:47:02.110 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9957 21:47:02.110 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9958 21:47:02.110 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9959 21:47:02.110 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 9960 21:47:02.110 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9961 21:47:02.110 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9962 21:47:02.110 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 9963 21:47:02.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9964 21:47:02.110 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9965 21:47:02.110 0.00020622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9966 21:47:02.110 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9967 21:47:02.110 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9968 21:47:02.110 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9969 21:47:02.110 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9970 21:47:02.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9971 21:47:02.110 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9972 21:47:02.110 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9973 21:47:02.110 0.00024731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9974 21:47:02.110 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9975 21:47:02.110 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9976 21:47:02.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9977 21:47:02.110 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9978 21:47:02.110 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9979 21:47:02.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9980 21:47:02.110 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9982 21:47:02.110 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9983 21:47:02.110 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9984 21:47:02.110 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9985 21:47:02.110 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9986 21:47:02.110 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9987 21:47:02.110 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9988 21:47:02.110 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9989 21:47:02.110 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9990 21:47:02.110 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 9991 21:47:02.110 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9992 21:47:02.110 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9993 21:47:02.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9994 21:47:02.110 0.02636366 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9995 21:47:02.141 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 9996 21:47:02.141 0.01694420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 9997 21:47:02.141 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 9998 21:47:02.160 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 9999 21:47:02.160 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10000 21:47:02.160 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10001 21:47:02.160 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10002 21:47:02.160 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10003 21:47:02.160 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 10004 21:47:02.160 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10005 21:47:02.160 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10006 21:47:02.160 0.00024138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10007 21:47:02.160 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 10008 21:47:02.160 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10009 21:47:02.160 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10010 21:47:02.160 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10011 21:47:02.160 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 10012 21:47:02.160 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10013 21:47:02.160 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10014 21:47:02.160 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10015 21:47:02.160 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10016 21:47:02.160 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 10017 21:47:02.160 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10018 21:47:02.160 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 60 10019 21:47:02.160 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10023 21:47:02.160 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10024 21:47:02.160 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 10025 21:47:02.160 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10026 21:47:02.160 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10027 21:47:02.160 0.00023506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10028 21:47:02.160 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 10029 21:47:02.160 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10030 21:47:02.160 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10031 21:47:02.160 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10032 21:47:02.160 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10033 21:47:02.160 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10034 21:47:02.160 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10035 21:47:02.160 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10036 21:47:02.160 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10037 21:47:02.160 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10038 21:47:02.160 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10039 21:47:02.160 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10040 21:47:02.160 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10041 21:47:02.160 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10042 21:47:02.160 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10043 21:47:02.160 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10044 21:47:02.160 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 10045 21:47:02.160 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10046 21:47:02.160 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10048 21:47:02.160 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10049 21:47:02.160 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10050 21:47:02.160 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10051 21:47:02.160 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10052 21:47:02.160 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10053 21:47:02.160 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10054 21:47:02.160 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10055 21:47:02.160 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 10056 21:47:02.160 0.00007941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10057 21:47:02.160 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10058 21:47:02.160 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10059 21:47:02.160 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10060 21:47:02.160 0.02646204 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10061 21:47:02.188 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10062 21:47:02.188 0.01088791 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10063 21:47:02.188 0.00000395 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10064 21:47:02.203 0.00036701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10065 21:47:02.203 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10066 21:47:02.203 0.00042627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10067 21:47:02.203 0.00031170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10068 21:47:02.203 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10069 21:47:02.203 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10070 21:47:02.203 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 10071 21:47:02.203 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10072 21:47:02.203 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 10073 21:47:02.203 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10074 21:47:02.203 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10075 21:47:02.203 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 10076 21:47:02.203 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10079 21:47:02.203 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 10080 21:47:02.203 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 10081 21:47:02.203 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10082 21:47:02.203 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10083 21:47:02.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10084 21:47:02.203 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10085 21:47:02.203 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 10086 21:47:02.203 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10087 21:47:02.203 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10088 21:47:02.203 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10089 21:47:02.203 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 34 10090 21:47:02.203 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10091 21:47:02.203 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10092 21:47:02.203 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10093 21:47:02.203 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10094 21:47:02.203 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10095 21:47:02.203 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10096 21:47:02.203 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10097 21:47:02.203 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10098 21:47:02.203 0.00009086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10099 21:47:02.203 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10100 21:47:02.203 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10101 21:47:02.203 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10102 21:47:02.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10103 21:47:02.203 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10104 21:47:02.203 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10105 21:47:02.203 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10106 21:47:02.203 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10107 21:47:02.203 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10108 21:47:02.203 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10109 21:47:02.203 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10110 21:47:02.203 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10111 21:47:02.203 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 10112 21:47:02.203 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10115 21:47:02.203 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10116 21:47:02.203 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10117 21:47:02.203 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10118 21:47:02.203 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10119 21:47:02.203 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10120 21:47:02.203 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10121 21:47:02.203 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10122 21:47:02.203 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10123 21:47:02.203 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10124 21:47:02.203 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10125 21:47:02.203 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10126 21:47:02.203 0.02854717 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10127 21:47:02.235 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10128 21:47:02.235 0.01409620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10129 21:47:02.235 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10130 21:47:02.250 0.00108405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10131 21:47:02.250 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10132 21:47:02.250 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10133 21:47:02.250 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10134 21:47:02.250 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 10135 21:47:02.250 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10136 21:47:02.250 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10137 21:47:02.250 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 10138 21:47:02.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10139 21:47:02.250 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10140 21:47:02.250 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10141 21:47:02.250 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10142 21:47:02.250 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10143 21:47:02.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10144 21:47:02.250 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 10145 21:47:02.250 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10146 21:47:02.250 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 56 10147 21:47:02.250 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10148 21:47:02.250 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10149 21:47:02.250 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10150 21:47:02.250 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10151 21:47:02.250 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10152 21:47:02.250 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10153 21:47:02.250 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10154 21:47:02.250 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10155 21:47:02.250 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 10156 21:47:02.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10157 21:47:02.250 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10158 21:47:02.250 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 56 10159 21:47:02.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10160 21:47:02.250 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10161 21:47:02.250 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10162 21:47:02.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10163 21:47:02.250 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10164 21:47:02.250 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10165 21:47:02.250 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10166 21:47:02.250 0.00021412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10167 21:47:02.250 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10168 21:47:02.250 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10169 21:47:02.250 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10170 21:47:02.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10171 21:47:02.250 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10172 21:47:02.250 0.00008257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10173 21:47:02.250 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10174 21:47:02.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10175 21:47:02.250 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10176 21:47:02.250 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10177 21:47:02.250 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10178 21:47:02.250 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10179 21:47:02.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10180 21:47:02.250 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10181 21:47:02.250 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10182 21:47:02.250 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10183 21:47:02.250 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10184 21:47:02.250 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10185 21:47:02.250 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10186 21:47:02.250 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10187 21:47:02.250 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 10188 21:47:02.250 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10191 21:47:02.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10192 21:47:02.250 0.02623883 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10193 21:47:02.282 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10194 21:47:02.282 0.01353917 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10195 21:47:02.282 0.00001541 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10196 21:47:02.297 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10197 21:47:02.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10198 21:47:02.297 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10199 21:47:02.297 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10200 21:47:02.297 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 10201 21:47:02.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10202 21:47:02.297 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10203 21:47:02.297 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 10204 21:47:02.297 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10205 21:47:02.297 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10206 21:47:02.297 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10207 21:47:02.297 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10208 21:47:02.297 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10209 21:47:02.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10210 21:47:02.297 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10211 21:47:02.297 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 10212 21:47:02.297 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 10213 21:47:02.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10214 21:47:02.297 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10215 21:47:02.297 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 10216 21:47:02.297 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10217 21:47:02.297 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10218 21:47:02.297 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10219 21:47:02.297 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10220 21:47:02.297 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10221 21:47:02.297 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 10222 21:47:02.297 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10223 21:47:02.297 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10224 21:47:02.297 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10225 21:47:02.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10226 21:47:02.297 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10227 21:47:02.297 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10228 21:47:02.297 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10229 21:47:02.297 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10230 21:47:02.297 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10231 21:47:02.297 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10232 21:47:02.297 0.00028563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10233 21:47:02.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10234 21:47:02.297 0.00032277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10235 21:47:02.297 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10236 21:47:02.297 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10237 21:47:02.297 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10238 21:47:02.297 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10239 21:47:02.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10240 21:47:02.297 0.00042311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10241 21:47:02.297 0.00028484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10242 21:47:02.297 0.00039309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10243 21:47:02.297 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10244 21:47:02.297 0.00034094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10245 21:47:02.297 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10246 21:47:02.297 0.00055388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10247 21:47:02.297 0.00040652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10248 21:47:02.297 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10249 21:47:02.297 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10250 21:47:02.297 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10251 21:47:02.297 0.00029432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10252 21:47:02.297 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10253 21:47:02.297 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10254 21:47:02.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10255 21:47:02.297 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10256 21:47:02.297 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10257 21:47:02.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10258 21:47:02.297 0.02541868 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10259 21:47:02.328 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10260 21:47:02.328 0.01444109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10261 21:47:02.328 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10262 21:47:02.344 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10263 21:47:02.344 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10264 21:47:02.344 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10265 21:47:02.344 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10266 21:47:02.344 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10267 21:47:02.344 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10268 21:47:02.344 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 10269 21:47:02.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10270 21:47:02.344 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10271 21:47:02.344 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 10272 21:47:02.344 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10273 21:47:02.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10274 21:47:02.344 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10275 21:47:02.344 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 10276 21:47:02.344 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10277 21:47:02.344 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10278 21:47:02.344 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 68 10279 21:47:02.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10280 21:47:02.344 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10281 21:47:02.344 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10282 21:47:02.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10283 21:47:02.344 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10284 21:47:02.344 0.00008217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10285 21:47:02.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10286 21:47:02.344 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10287 21:47:02.344 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 10288 21:47:02.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10289 21:47:02.344 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10290 21:47:02.344 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 68 10291 21:47:02.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10292 21:47:02.344 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10293 21:47:02.344 0.00008375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10294 21:47:02.344 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10295 21:47:02.344 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10296 21:47:02.344 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10297 21:47:02.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10298 21:47:02.344 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10299 21:47:02.344 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10300 21:47:02.344 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10301 21:47:02.344 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10302 21:47:02.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10303 21:47:02.344 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10304 21:47:02.344 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10305 21:47:02.344 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10306 21:47:02.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10307 21:47:02.344 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10308 21:47:02.344 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10309 21:47:02.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10310 21:47:02.344 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10311 21:47:02.344 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10312 21:47:02.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10313 21:47:02.344 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10314 21:47:02.344 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10315 21:47:02.344 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10316 21:47:02.344 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10317 21:47:02.344 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 10318 21:47:02.344 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10319 21:47:02.344 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10320 21:47:02.344 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10321 21:47:02.344 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 44 10322 21:47:02.344 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10325 21:47:02.375 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10326 21:47:02.375 0.01363240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10327 21:47:02.375 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10328 21:47:02.391 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10329 21:47:02.391 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10330 21:47:02.391 0.00041877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10331 21:47:02.391 0.00031684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10332 21:47:02.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10333 21:47:02.391 0.00029156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10334 21:47:02.391 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 10335 21:47:02.391 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10336 21:47:02.391 0.00033659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 10337 21:47:02.391 0.00024652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10338 21:47:02.391 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10339 21:47:02.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10340 21:47:02.391 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10341 21:47:02.391 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 10342 21:47:02.391 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10343 21:47:02.391 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10344 21:47:02.391 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 10345 21:47:02.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10346 21:47:02.391 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10347 21:47:02.391 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 10348 21:47:02.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10349 21:47:02.391 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10350 21:47:02.391 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10351 21:47:02.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10352 21:47:02.391 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10353 21:47:02.391 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 36 10354 21:47:02.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10355 21:47:02.391 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10356 21:47:02.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10357 21:47:02.391 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10358 21:47:02.391 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10359 21:47:02.391 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10360 21:47:02.391 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10361 21:47:02.391 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10362 21:47:02.391 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10363 21:47:02.391 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10364 21:47:02.391 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10365 21:47:02.391 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10366 21:47:02.391 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10367 21:47:02.391 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10368 21:47:02.391 0.00009560 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10369 21:47:02.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10370 21:47:02.391 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10371 21:47:02.391 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10372 21:47:02.391 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10373 21:47:02.391 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10374 21:47:02.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10375 21:47:02.391 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10376 21:47:02.391 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10377 21:47:02.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10378 21:47:02.391 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10379 21:47:02.391 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10380 21:47:02.391 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10381 21:47:02.391 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10382 21:47:02.391 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10383 21:47:02.391 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10384 21:47:02.391 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10385 21:47:02.391 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10386 21:47:02.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10387 21:47:02.391 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10388 21:47:02.391 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10389 21:47:02.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10390 21:47:02.391 0.02689384 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10391 21:47:02.422 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10392 21:47:02.422 0.01706825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10393 21:47:02.422 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10394 21:47:02.441 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10395 21:47:02.441 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10396 21:47:02.441 0.00029669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10397 21:47:02.441 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10398 21:47:02.441 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10399 21:47:02.441 0.00047842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10400 21:47:02.441 0.00040889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 10401 21:47:02.441 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10402 21:47:02.441 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 10403 21:47:02.441 0.00029630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10404 21:47:02.441 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10405 21:47:02.441 0.00039664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10407 21:47:02.441 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 10408 21:47:02.441 0.00023348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10409 21:47:02.441 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10413 21:47:02.441 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10414 21:47:02.441 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10415 21:47:02.441 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10416 21:47:02.441 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10417 21:47:02.441 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10418 21:47:02.441 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10419 21:47:02.441 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 10420 21:47:02.441 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10421 21:47:02.441 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10422 21:47:02.441 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10423 21:47:02.441 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10424 21:47:02.441 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 81 10425 21:47:02.441 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10426 21:47:02.441 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10427 21:47:02.441 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10428 21:47:02.441 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10429 21:47:02.441 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10430 21:47:02.441 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10431 21:47:02.441 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10432 21:47:02.441 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10433 21:47:02.441 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10434 21:47:02.441 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10435 21:47:02.441 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10436 21:47:02.441 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10437 21:47:02.441 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10438 21:47:02.441 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10439 21:47:02.441 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10440 21:47:02.441 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10441 21:47:02.441 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10442 21:47:02.441 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10443 21:47:02.441 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10444 21:47:02.441 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10445 21:47:02.441 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10446 21:47:02.441 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10447 21:47:02.441 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10448 21:47:02.441 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10449 21:47:02.441 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 10450 21:47:02.441 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10451 21:47:02.441 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10452 21:47:02.441 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10453 21:47:02.441 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10454 21:47:02.441 0.02629611 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10455 21:47:02.469 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10456 21:47:02.469 0.01095665 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10457 21:47:02.469 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10458 21:47:02.484 0.00041323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10459 21:47:02.484 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10460 21:47:02.484 0.00037017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10461 21:47:02.484 0.00029788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10462 21:47:02.484 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10463 21:47:02.484 0.00038123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10464 21:47:02.484 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 10465 21:47:02.484 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10466 21:47:02.484 0.00027694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 10467 21:47:02.484 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10468 21:47:02.484 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10470 21:47:02.484 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10471 21:47:02.484 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10472 21:47:02.484 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 50 10473 21:47:02.484 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10474 21:47:02.484 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10475 21:47:02.484 0.00028207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 10476 21:47:02.484 0.00025561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10477 21:47:02.484 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10478 21:47:02.484 0.00026074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10479 21:47:02.484 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 10480 21:47:02.484 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10481 21:47:02.484 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10482 21:47:02.484 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10483 21:47:02.484 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 10484 21:47:02.484 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10485 21:47:02.484 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10486 21:47:02.484 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10487 21:47:02.484 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10488 21:47:02.484 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10489 21:47:02.484 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10490 21:47:02.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10491 21:47:02.484 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10492 21:47:02.484 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10493 21:47:02.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10494 21:47:02.484 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10495 21:47:02.484 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10496 21:47:02.484 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10497 21:47:02.484 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10498 21:47:02.484 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10499 21:47:02.484 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10500 21:47:02.484 0.00009047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10501 21:47:02.484 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10502 21:47:02.484 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10503 21:47:02.484 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10504 21:47:02.484 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10505 21:47:02.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10506 21:47:02.484 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10507 21:47:02.484 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10508 21:47:02.484 0.00021136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10509 21:47:02.484 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10510 21:47:02.484 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10511 21:47:02.484 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10512 21:47:02.484 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10513 21:47:02.484 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10514 21:47:02.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10515 21:47:02.484 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10516 21:47:02.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10517 21:47:02.484 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10518 21:47:02.484 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10519 21:47:02.484 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10520 21:47:02.484 0.02729917 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10521 21:47:02.516 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10522 21:47:02.516 0.01321126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10523 21:47:02.516 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10524 21:47:02.531 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10525 21:47:02.531 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10526 21:47:02.531 0.00042351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10527 21:47:02.531 0.00029393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10528 21:47:02.531 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10529 21:47:02.531 0.00032079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10530 21:47:02.531 0.00026785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 10531 21:47:02.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10532 21:47:02.531 0.00030815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10533 21:47:02.531 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 10534 21:47:02.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10535 21:47:02.531 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10536 21:47:02.531 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10537 21:47:02.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10538 21:47:02.531 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10539 21:47:02.531 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 10540 21:47:02.531 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10541 21:47:02.531 0.00035516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10542 21:47:02.531 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 93 10543 21:47:02.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10544 21:47:02.531 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10545 21:47:02.531 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10546 21:47:02.531 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10547 21:47:02.531 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10548 21:47:02.531 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10549 21:47:02.531 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10550 21:47:02.531 0.00029472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 10551 21:47:02.531 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10552 21:47:02.531 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10553 21:47:02.531 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10554 21:47:02.531 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 93 10555 21:47:02.531 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 10556 21:47:02.531 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10557 21:47:02.531 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10558 21:47:02.531 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10559 21:47:02.531 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10560 21:47:02.531 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10561 21:47:02.531 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10562 21:47:02.531 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10563 21:47:02.531 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10564 21:47:02.531 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10565 21:47:02.531 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10566 21:47:02.531 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10567 21:47:02.531 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10568 21:47:02.531 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10569 21:47:02.531 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10570 21:47:02.531 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10571 21:47:02.531 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10572 21:47:02.531 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10573 21:47:02.531 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10574 21:47:02.531 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10575 21:47:02.531 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10576 21:47:02.531 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10577 21:47:02.531 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10578 21:47:02.531 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10579 21:47:02.531 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 10580 21:47:02.531 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10581 21:47:02.531 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10582 21:47:02.531 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10583 21:47:02.531 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10584 21:47:02.531 0.00008533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 10585 21:47:02.531 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10586 21:47:02.531 0.02668169 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10587 21:47:02.563 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10588 21:47:02.563 0.01361936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10589 21:47:02.563 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10590 21:47:02.578 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10591 21:47:02.578 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10592 21:47:02.578 0.00026785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10593 21:47:02.578 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10594 21:47:02.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10595 21:47:02.578 0.00052701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10596 21:47:02.578 0.00046499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 10597 21:47:02.578 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10598 21:47:02.578 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10599 21:47:02.578 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 10600 21:47:02.578 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 10601 21:47:02.578 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10602 21:47:02.578 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10606 21:47:02.578 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10607 21:47:02.578 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10608 21:47:02.578 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 10609 21:47:02.578 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 10610 21:47:02.578 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10611 21:47:02.578 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10612 21:47:02.578 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10613 21:47:02.578 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10614 21:47:02.578 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10615 21:47:02.578 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10616 21:47:02.578 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 38 10617 21:47:02.578 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10618 21:47:02.578 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10619 21:47:02.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10620 21:47:02.578 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10621 21:47:02.578 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10622 21:47:02.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10623 21:47:02.578 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10624 21:47:02.578 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10625 21:47:02.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10626 21:47:02.578 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10627 21:47:02.578 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10628 21:47:02.578 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10629 21:47:02.578 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10630 21:47:02.578 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10631 21:47:02.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10632 21:47:02.578 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10633 21:47:02.578 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10634 21:47:02.578 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10635 21:47:02.578 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10636 21:47:02.578 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10637 21:47:02.578 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10638 21:47:02.578 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10639 21:47:02.578 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10640 21:47:02.578 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10641 21:47:02.578 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10642 21:47:02.578 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10643 21:47:02.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10644 21:47:02.578 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10645 21:47:02.578 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10646 21:47:02.578 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10647 21:47:02.578 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10648 21:47:02.578 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10649 21:47:02.578 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10650 21:47:02.578 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10651 21:47:02.578 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10652 21:47:02.578 0.02665206 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10653 21:47:02.610 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10654 21:47:02.610 0.01470065 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10655 21:47:02.610 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10656 21:47:02.626 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10657 21:47:02.626 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10658 21:47:02.626 0.00043259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10659 21:47:02.626 0.00036938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10660 21:47:02.626 0.00028484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 10661 21:47:02.626 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10662 21:47:02.626 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10663 21:47:02.626 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10664 21:47:02.626 0.00042706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10665 21:47:02.626 0.00033264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 10666 21:47:02.626 0.00027773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10667 21:47:02.626 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10668 21:47:02.626 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10669 21:47:02.626 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10670 21:47:02.626 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10671 21:47:02.626 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10672 21:47:02.626 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10673 21:47:02.626 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10674 21:47:02.626 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10675 21:47:02.626 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10676 21:47:02.626 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10677 21:47:02.626 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10678 21:47:02.626 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10679 21:47:02.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10680 21:47:02.626 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10681 21:47:02.626 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10682 21:47:02.626 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10683 21:47:02.626 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10684 21:47:02.626 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10685 21:47:02.626 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10686 21:47:02.626 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10687 21:47:02.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10688 21:47:02.626 0.00035635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10689 21:47:02.626 0.00036109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10690 21:47:02.626 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10691 21:47:02.626 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10692 21:47:02.626 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10693 21:47:02.626 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10694 21:47:02.626 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10695 21:47:02.626 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10696 21:47:02.626 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10697 21:47:02.626 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10698 21:47:02.626 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10699 21:47:02.626 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10700 21:47:02.626 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10701 21:47:02.626 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10702 21:47:02.626 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10703 21:47:02.626 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10704 21:47:02.626 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10705 21:47:02.626 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10706 21:47:02.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10707 21:47:02.626 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10708 21:47:02.626 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10709 21:47:02.626 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10710 21:47:02.626 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10711 21:47:02.626 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10712 21:47:02.626 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10713 21:47:02.626 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10714 21:47:02.626 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10715 21:47:02.626 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10716 21:47:02.626 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10717 21:47:02.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10718 21:47:02.626 0.02538036 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10719 21:47:02.657 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10720 21:47:02.657 0.01393186 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10721 21:47:02.657 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10722 21:47:02.673 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10723 21:47:02.673 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10724 21:47:02.673 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10725 21:47:02.673 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10726 21:47:02.673 0.00047723 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10727 21:47:02.673 0.00046183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 10728 21:47:02.673 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10729 21:47:02.673 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 10730 21:47:02.673 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10731 21:47:02.673 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10732 21:47:02.673 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10733 21:47:02.673 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10734 21:47:02.673 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10735 21:47:02.673 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10736 21:47:02.673 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10737 21:47:02.673 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10738 21:47:02.673 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10739 21:47:02.673 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10740 21:47:02.673 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10741 21:47:02.673 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10742 21:47:02.673 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10743 21:47:02.673 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10744 21:47:02.673 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10745 21:47:02.673 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10746 21:47:02.673 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10747 21:47:02.673 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10748 21:47:02.673 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10749 21:47:02.673 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10750 21:47:02.673 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10751 21:47:02.673 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10752 21:47:02.673 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10753 21:47:02.673 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10754 21:47:02.673 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10755 21:47:02.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10756 21:47:02.673 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10757 21:47:02.673 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10758 21:47:02.673 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10759 21:47:02.673 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10760 21:47:02.673 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10761 21:47:02.673 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10762 21:47:02.673 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10763 21:47:02.673 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10764 21:47:02.673 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10765 21:47:02.673 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10766 21:47:02.673 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10767 21:47:02.673 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10768 21:47:02.673 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10769 21:47:02.673 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10770 21:47:02.673 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10771 21:47:02.673 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10772 21:47:02.673 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10773 21:47:02.673 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10774 21:47:02.673 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10775 21:47:02.673 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10776 21:47:02.673 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10777 21:47:02.673 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10778 21:47:02.673 0.00008533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10779 21:47:02.673 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10780 21:47:02.673 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10781 21:47:02.673 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10782 21:47:02.673 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10783 21:47:02.673 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10784 21:47:02.673 0.02745167 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10785 21:47:02.703 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10786 21:47:02.703 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10787 21:47:02.703 0.01426134 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10788 21:47:02.719 0.00047131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10789 21:47:02.719 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10790 21:47:02.719 0.00034686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10791 21:47:02.719 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10792 21:47:02.719 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10793 21:47:02.719 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10794 21:47:02.719 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 10795 21:47:02.719 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10796 21:47:02.719 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10797 21:47:02.719 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10798 21:47:02.719 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10799 21:47:02.719 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10800 21:47:02.719 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10801 21:47:02.719 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10802 21:47:02.719 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10803 21:47:02.719 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10804 21:47:02.719 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10805 21:47:02.719 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10806 21:47:02.719 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10807 21:47:02.719 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10808 21:47:02.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10809 21:47:02.719 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10810 21:47:02.719 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10811 21:47:02.719 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10812 21:47:02.719 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10813 21:47:02.719 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10814 21:47:02.719 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10815 21:47:02.719 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10816 21:47:02.719 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10817 21:47:02.719 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10818 21:47:02.719 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10819 21:47:02.719 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10820 21:47:02.719 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10821 21:47:02.719 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10822 21:47:02.719 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10823 21:47:02.719 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10824 21:47:02.719 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10825 21:47:02.719 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10826 21:47:02.719 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10827 21:47:02.719 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10828 21:47:02.719 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10829 21:47:02.719 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10830 21:47:02.719 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10831 21:47:02.719 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10832 21:47:02.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10833 21:47:02.719 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10834 21:47:02.719 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10835 21:47:02.719 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10836 21:47:02.719 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10837 21:47:02.719 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10840 21:47:02.719 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10841 21:47:02.719 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10842 21:47:02.719 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10843 21:47:02.719 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10844 21:47:02.719 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10845 21:47:02.719 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10846 21:47:02.719 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10847 21:47:02.719 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10848 21:47:02.719 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10849 21:47:02.719 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10850 21:47:02.719 0.02642806 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10851 21:47:02.750 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10852 21:47:02.750 0.01454657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10853 21:47:02.750 0.00000356 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10854 21:47:02.766 0.00037649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10855 21:47:02.766 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10856 21:47:02.766 0.00044958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10857 21:47:02.766 0.00038874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10858 21:47:02.766 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10859 21:47:02.766 0.00033106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10860 21:47:02.766 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 10861 21:47:02.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10862 21:47:02.766 0.00039072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10863 21:47:02.766 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 10864 21:47:02.766 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10865 21:47:02.766 0.00059378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10866 21:47:02.766 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10867 21:47:02.766 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10868 21:47:02.766 0.00040138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10869 21:47:02.766 0.00033343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10870 21:47:02.766 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10871 21:47:02.766 0.00028049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10872 21:47:02.766 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10873 21:47:02.766 0.00038005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10874 21:47:02.766 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10875 21:47:02.766 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10876 21:47:02.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10877 21:47:02.766 0.00024099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10878 21:47:02.766 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10879 21:47:02.766 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10880 21:47:02.766 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10881 21:47:02.766 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10882 21:47:02.766 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10883 21:47:02.766 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10884 21:47:02.766 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10885 21:47:02.766 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10886 21:47:02.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10887 21:47:02.766 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10888 21:47:02.766 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10889 21:47:02.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10890 21:47:02.766 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10891 21:47:02.766 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10892 21:47:02.766 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10893 21:47:02.766 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10894 21:47:02.766 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10895 21:47:02.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10896 21:47:02.766 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10897 21:47:02.766 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10898 21:47:02.766 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10899 21:47:02.766 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10900 21:47:02.766 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10901 21:47:02.766 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10902 21:47:02.766 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10903 21:47:02.766 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10904 21:47:02.766 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10905 21:47:02.766 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10906 21:47:02.766 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10907 21:47:02.766 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10908 21:47:02.766 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10909 21:47:02.766 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10910 21:47:02.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10911 21:47:02.766 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10912 21:47:02.766 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10913 21:47:02.766 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10914 21:47:02.766 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10915 21:47:02.766 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10916 21:47:02.766 0.02630520 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10917 21:47:02.797 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10918 21:47:02.797 0.01350519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10919 21:47:02.797 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10920 21:47:02.813 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10921 21:47:02.813 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10922 21:47:02.813 0.00026667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10923 21:47:02.813 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10924 21:47:02.813 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 10925 21:47:02.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10926 21:47:02.813 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10927 21:47:02.813 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10928 21:47:02.813 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10929 21:47:02.813 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10930 21:47:02.813 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10931 21:47:02.813 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10932 21:47:02.813 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10933 21:47:02.813 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10934 21:47:02.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10935 21:47:02.813 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10936 21:47:02.813 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10937 21:47:02.813 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10938 21:47:02.813 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10939 21:47:02.813 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10940 21:47:02.813 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10941 21:47:02.813 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10942 21:47:02.813 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10943 21:47:02.813 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10944 21:47:02.813 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10945 21:47:02.813 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10946 21:47:02.813 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10947 21:47:02.813 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 10948 21:47:02.813 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10949 21:47:02.813 0.00025047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10950 21:47:02.813 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10951 21:47:02.813 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10952 21:47:02.813 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10953 21:47:02.813 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10954 21:47:02.813 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10955 21:47:02.813 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10956 21:47:02.813 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10957 21:47:02.813 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10958 21:47:02.813 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10959 21:47:02.813 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10960 21:47:02.813 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10961 21:47:02.813 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10962 21:47:02.813 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10963 21:47:02.813 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10964 21:47:02.813 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10965 21:47:02.813 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10966 21:47:02.813 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10967 21:47:02.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10968 21:47:02.813 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10969 21:47:02.813 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10970 21:47:02.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10971 21:47:02.813 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10972 21:47:02.813 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10973 21:47:02.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10974 21:47:02.813 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10975 21:47:02.813 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10976 21:47:02.813 0.00042548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10977 21:47:02.813 0.00038756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10978 21:47:02.813 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10979 21:47:02.813 0.00038005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10980 21:47:02.813 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10981 21:47:02.813 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10982 21:47:02.813 0.02653591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10983 21:47:02.844 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10984 21:47:02.844 0.01414124 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10985 21:47:02.844 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 10986 21:47:02.860 0.00033857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 10987 21:47:02.860 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10988 21:47:02.860 0.00033343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10989 21:47:02.860 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 10990 21:47:02.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10991 21:47:02.860 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10992 21:47:02.860 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 10993 21:47:02.860 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10994 21:47:02.860 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 10995 21:47:02.860 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10996 21:47:02.860 0.00009086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 10997 21:47:02.860 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10998 21:47:02.860 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 10999 21:47:02.860 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11000 21:47:02.860 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11001 21:47:02.860 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11002 21:47:02.860 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11003 21:47:02.860 0.00032711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11004 21:47:02.860 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11005 21:47:02.860 0.00104810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11006 21:47:02.860 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11007 21:47:02.860 0.00106825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11008 21:47:02.860 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11009 21:47:02.860 0.00024652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11010 21:47:02.860 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11011 21:47:02.860 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11012 21:47:02.860 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11013 21:47:02.860 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11014 21:47:02.860 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11015 21:47:02.860 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11016 21:47:02.860 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11017 21:47:02.860 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11018 21:47:02.860 0.00032119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11019 21:47:02.860 0.00044365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11020 21:47:02.860 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11021 21:47:02.860 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11022 21:47:02.860 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11023 21:47:02.860 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11024 21:47:02.860 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11025 21:47:02.860 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11026 21:47:02.860 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11027 21:47:02.860 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11028 21:47:02.860 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11029 21:47:02.860 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11030 21:47:02.860 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11031 21:47:02.860 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11032 21:47:02.860 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11033 21:47:02.860 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11034 21:47:02.860 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11035 21:47:02.860 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11036 21:47:02.860 0.00028523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11037 21:47:02.860 0.00034489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11038 21:47:02.860 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11039 21:47:02.860 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11040 21:47:02.860 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11041 21:47:02.860 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11042 21:47:02.860 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11043 21:47:02.860 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11044 21:47:02.860 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11045 21:47:02.860 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11046 21:47:02.860 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11047 21:47:02.860 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11048 21:47:02.860 0.02742599 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11049 21:47:02.891 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11050 21:47:02.891 0.01174677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11051 21:47:02.891 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11052 21:47:02.907 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11053 21:47:02.907 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11054 21:47:02.907 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11055 21:47:02.907 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11056 21:47:02.907 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11057 21:47:02.907 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11058 21:47:02.907 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11059 21:47:02.907 0.00046499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 11060 21:47:02.907 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11061 21:47:02.907 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11062 21:47:02.907 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11063 21:47:02.907 0.00040375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11064 21:47:02.907 0.00029235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11065 21:47:02.907 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11066 21:47:02.907 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11067 21:47:02.907 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11068 21:47:02.907 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11069 21:47:02.907 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11070 21:47:02.907 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11071 21:47:02.907 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11072 21:47:02.907 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11073 21:47:02.907 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11074 21:47:02.907 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11075 21:47:02.907 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11076 21:47:02.907 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11077 21:47:02.907 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11078 21:47:02.907 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11079 21:47:02.907 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11080 21:47:02.907 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11081 21:47:02.907 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11082 21:47:02.907 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11083 21:47:02.907 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11084 21:47:02.907 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11085 21:47:02.907 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11086 21:47:02.907 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11087 21:47:02.907 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11088 21:47:02.907 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11089 21:47:02.907 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11090 21:47:02.907 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11091 21:47:02.907 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11092 21:47:02.907 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11093 21:47:02.907 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11094 21:47:02.907 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11095 21:47:02.907 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11096 21:47:02.907 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11097 21:47:02.907 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11098 21:47:02.907 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11099 21:47:02.907 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11100 21:47:02.907 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11101 21:47:02.907 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11102 21:47:02.907 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11103 21:47:02.907 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11104 21:47:02.907 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11105 21:47:02.907 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11106 21:47:02.907 0.00030104 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11107 21:47:02.907 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11108 21:47:02.907 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11109 21:47:02.907 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11110 21:47:02.907 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11111 21:47:02.907 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11112 21:47:02.907 0.02534006 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11113 21:47:02.938 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11114 21:47:02.938 0.01501235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11115 21:47:02.938 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11116 21:47:02.954 0.00033699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11117 21:47:02.954 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11118 21:47:02.954 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11119 21:47:02.954 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11120 21:47:02.954 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11121 21:47:02.954 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11122 21:47:02.954 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11123 21:47:02.954 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11124 21:47:02.954 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 11125 21:47:02.954 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11126 21:47:02.954 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11127 21:47:02.954 0.00041244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11128 21:47:02.954 0.00034410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11129 21:47:02.954 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11130 21:47:02.954 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11131 21:47:02.954 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11132 21:47:02.954 0.00009126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11133 21:47:02.954 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11134 21:47:02.954 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11135 21:47:02.954 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11136 21:47:02.954 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11137 21:47:02.954 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11138 21:47:02.954 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11139 21:47:02.954 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11140 21:47:02.954 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11141 21:47:02.954 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11142 21:47:02.954 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11143 21:47:02.954 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11144 21:47:02.954 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11145 21:47:02.954 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11146 21:47:02.954 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11147 21:47:02.954 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11148 21:47:02.954 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11149 21:47:02.954 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11150 21:47:02.954 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11151 21:47:02.954 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11152 21:47:02.954 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11153 21:47:02.954 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11154 21:47:02.954 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11155 21:47:02.954 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11156 21:47:02.954 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11157 21:47:02.954 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11158 21:47:02.954 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11159 21:47:02.954 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11160 21:47:02.954 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11161 21:47:02.954 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11162 21:47:02.954 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11163 21:47:02.954 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11164 21:47:02.954 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11165 21:47:02.954 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11166 21:47:02.954 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11167 21:47:02.954 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11168 21:47:02.954 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11169 21:47:02.954 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11170 21:47:02.954 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11171 21:47:02.954 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11172 21:47:02.954 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11173 21:47:02.954 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11174 21:47:02.954 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11175 21:47:02.954 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11176 21:47:02.954 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11177 21:47:02.954 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11178 21:47:02.954 0.02844880 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11179 21:47:02.984 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11180 21:47:02.984 0.01258470 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11181 21:47:02.984 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11182 21:47:03.000 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11183 21:47:03.000 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11184 21:47:03.000 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11185 21:47:03.000 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 58 11188 21:47:03.000 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11189 21:47:03.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11190 21:47:03.000 0.00042904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11191 21:47:03.000 0.00035990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 11192 21:47:03.000 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11193 21:47:03.000 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11194 21:47:03.000 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11195 21:47:03.000 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11196 21:47:03.000 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11197 21:47:03.000 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11198 21:47:03.000 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11199 21:47:03.000 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11200 21:47:03.000 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11201 21:47:03.000 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11202 21:47:03.000 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11203 21:47:03.000 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11204 21:47:03.000 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11205 21:47:03.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11206 21:47:03.000 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11207 21:47:03.000 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11208 21:47:03.000 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11209 21:47:03.000 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11210 21:47:03.000 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11211 21:47:03.000 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11212 21:47:03.000 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11213 21:47:03.000 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11214 21:47:03.000 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11215 21:47:03.000 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11216 21:47:03.000 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11218 21:47:03.000 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11219 21:47:03.000 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11220 21:47:03.000 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11221 21:47:03.000 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 11223 21:47:03.000 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11224 21:47:03.000 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11225 21:47:03.000 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11226 21:47:03.000 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11227 21:47:03.000 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11228 21:47:03.000 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11229 21:47:03.000 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11230 21:47:03.000 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11231 21:47:03.000 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11232 21:47:03.000 0.00000079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11233 21:47:03.000 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11234 21:47:03.000 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11235 21:47:03.000 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11236 21:47:03.000 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11237 21:47:03.000 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11238 21:47:03.000 0.00009126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11239 21:47:03.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11240 21:47:03.000 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11241 21:47:03.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11242 21:47:03.000 0.02556366 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11243 21:47:03.032 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11244 21:47:03.032 0.01494322 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11246 21:47:03.047 0.00034686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11247 21:47:03.047 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11248 21:47:03.047 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11249 21:47:03.047 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11250 21:47:03.047 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11251 21:47:03.047 0.00037491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11252 21:47:03.047 0.00034252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11253 21:47:03.047 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 11254 21:47:03.047 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11255 21:47:03.047 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11256 21:47:03.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11257 21:47:03.047 0.00028681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11258 21:47:03.047 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11259 21:47:03.047 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11260 21:47:03.047 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11261 21:47:03.047 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11262 21:47:03.047 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11263 21:47:03.047 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11264 21:47:03.047 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11265 21:47:03.047 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 11266 21:47:03.047 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11267 21:47:03.047 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11270 21:47:03.047 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11271 21:47:03.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11272 21:47:03.047 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11273 21:47:03.047 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11274 21:47:03.047 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11275 21:47:03.047 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11276 21:47:03.047 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11277 21:47:03.047 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11278 21:47:03.047 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11279 21:47:03.047 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11280 21:47:03.047 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11281 21:47:03.047 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11282 21:47:03.047 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11283 21:47:03.047 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11284 21:47:03.047 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11285 21:47:03.047 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11286 21:47:03.047 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11287 21:47:03.047 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11288 21:47:03.047 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11289 21:47:03.047 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11290 21:47:03.047 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11291 21:47:03.047 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11292 21:47:03.047 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11293 21:47:03.047 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11294 21:47:03.047 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11295 21:47:03.047 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11296 21:47:03.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11297 21:47:03.047 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11298 21:47:03.047 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11299 21:47:03.047 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11300 21:47:03.047 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11301 21:47:03.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11302 21:47:03.047 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 11303 21:47:03.047 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11307 21:47:03.047 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11308 21:47:03.047 0.02561700 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11309 21:47:03.078 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11310 21:47:03.078 0.01460939 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11311 21:47:03.078 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11312 21:47:03.094 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11313 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11314 21:47:03.094 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11315 21:47:03.094 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11316 21:47:03.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11317 21:47:03.094 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11318 21:47:03.094 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11319 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11320 21:47:03.094 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11321 21:47:03.094 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 11322 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11323 21:47:03.094 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11324 21:47:03.094 0.00033541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11325 21:47:03.094 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11326 21:47:03.094 0.00031407 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11327 21:47:03.094 0.00030696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11328 21:47:03.094 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11329 21:47:03.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11330 21:47:03.094 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11331 21:47:03.094 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11332 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11333 21:47:03.094 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11334 21:47:03.094 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11335 21:47:03.094 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11336 21:47:03.094 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11337 21:47:03.094 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11338 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11339 21:47:03.094 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11340 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11341 21:47:03.094 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11342 21:47:03.094 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11343 21:47:03.094 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11344 21:47:03.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11345 21:47:03.094 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11346 21:47:03.094 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11347 21:47:03.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11348 21:47:03.094 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11349 21:47:03.094 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11350 21:47:03.094 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11351 21:47:03.094 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11352 21:47:03.094 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11353 21:47:03.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11354 21:47:03.094 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11355 21:47:03.094 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11356 21:47:03.094 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11357 21:47:03.094 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11358 21:47:03.094 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11359 21:47:03.094 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11360 21:47:03.094 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11361 21:47:03.094 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11362 21:47:03.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11363 21:47:03.094 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11364 21:47:03.094 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11365 21:47:03.094 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11366 21:47:03.094 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11367 21:47:03.094 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11368 21:47:03.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11369 21:47:03.094 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11370 21:47:03.094 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11371 21:47:03.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11372 21:47:03.094 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11373 21:47:03.094 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11374 21:47:03.094 0.02796248 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11375 21:47:03.125 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11376 21:47:03.125 0.01324129 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11377 21:47:03.125 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11378 21:47:03.141 0.00033541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11379 21:47:03.141 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11380 21:47:03.141 0.00047486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11381 21:47:03.141 0.00040533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11382 21:47:03.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11383 21:47:03.141 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11384 21:47:03.141 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11385 21:47:03.141 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 11386 21:47:03.141 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11387 21:47:03.141 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11388 21:47:03.141 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11389 21:47:03.141 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11390 21:47:03.141 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11391 21:47:03.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11392 21:47:03.141 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11393 21:47:03.141 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11394 21:47:03.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11395 21:47:03.141 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11396 21:47:03.141 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11397 21:47:03.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11398 21:47:03.141 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11399 21:47:03.141 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11400 21:47:03.141 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11401 21:47:03.141 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11402 21:47:03.141 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11403 21:47:03.141 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11404 21:47:03.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11405 21:47:03.141 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11406 21:47:03.141 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11407 21:47:03.141 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11408 21:47:03.141 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11409 21:47:03.141 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11410 21:47:03.141 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11411 21:47:03.141 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11412 21:47:03.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11413 21:47:03.141 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11414 21:47:03.141 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11415 21:47:03.141 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11416 21:47:03.141 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11417 21:47:03.141 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11418 21:47:03.141 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11419 21:47:03.141 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11420 21:47:03.141 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11421 21:47:03.141 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11422 21:47:03.141 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11423 21:47:03.141 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11424 21:47:03.141 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11425 21:47:03.141 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11426 21:47:03.141 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11427 21:47:03.141 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11428 21:47:03.141 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11429 21:47:03.141 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11430 21:47:03.141 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11431 21:47:03.141 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11432 21:47:03.141 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11433 21:47:03.141 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11434 21:47:03.141 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11435 21:47:03.141 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11436 21:47:03.141 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11437 21:47:03.141 0.00022756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11438 21:47:03.141 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11439 21:47:03.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11440 21:47:03.141 0.02700446 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11441 21:47:03.172 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11442 21:47:03.172 0.01417838 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11443 21:47:03.172 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11444 21:47:03.188 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11445 21:47:03.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11446 21:47:03.188 0.00031249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11447 21:47:03.188 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11448 21:47:03.188 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11449 21:47:03.188 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11450 21:47:03.188 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11451 21:47:03.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11452 21:47:03.188 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11453 21:47:03.188 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 11454 21:47:03.188 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11455 21:47:03.188 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11456 21:47:03.188 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11457 21:47:03.188 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11458 21:47:03.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11459 21:47:03.188 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11460 21:47:03.188 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11461 21:47:03.188 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11462 21:47:03.188 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11463 21:47:03.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11464 21:47:03.188 0.00038044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11465 21:47:03.188 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11466 21:47:03.188 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11467 21:47:03.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11468 21:47:03.188 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11469 21:47:03.188 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11470 21:47:03.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11471 21:47:03.188 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11472 21:47:03.188 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11473 21:47:03.188 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11474 21:47:03.188 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11475 21:47:03.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11476 21:47:03.188 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11477 21:47:03.188 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11478 21:47:03.188 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11479 21:47:03.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11480 21:47:03.188 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11481 21:47:03.188 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11484 21:47:03.188 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11485 21:47:03.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11486 21:47:03.188 0.00026943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11487 21:47:03.188 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11488 21:47:03.188 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11489 21:47:03.188 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11490 21:47:03.188 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11491 21:47:03.188 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11492 21:47:03.188 0.00020583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11493 21:47:03.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11494 21:47:03.188 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11495 21:47:03.188 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11496 21:47:03.188 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11497 21:47:03.188 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11498 21:47:03.188 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11499 21:47:03.188 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11500 21:47:03.188 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11501 21:47:03.188 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11502 21:47:03.188 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11503 21:47:03.188 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11504 21:47:03.188 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11505 21:47:03.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11506 21:47:03.188 0.02701631 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11507 21:47:03.219 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11508 21:47:03.219 0.01363714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11509 21:47:03.219 0.00003556 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11510 21:47:03.235 0.00058351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11511 21:47:03.235 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11512 21:47:03.235 0.00034449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11513 21:47:03.235 0.00029788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11514 21:47:03.235 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11515 21:47:03.235 0.00039032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11516 21:47:03.235 0.00031210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11517 21:47:03.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11518 21:47:03.235 0.00031565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11519 21:47:03.235 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 11520 21:47:03.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11521 21:47:03.235 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11522 21:47:03.235 0.00029037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11523 21:47:03.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11524 21:47:03.235 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11525 21:47:03.235 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11526 21:47:03.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11527 21:47:03.235 0.00037531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11528 21:47:03.235 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11529 21:47:03.235 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11530 21:47:03.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11531 21:47:03.235 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11532 21:47:03.235 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11533 21:47:03.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11534 21:47:03.235 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11535 21:47:03.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11536 21:47:03.235 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11537 21:47:03.235 0.00023506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11538 21:47:03.235 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11539 21:47:03.235 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11540 21:47:03.235 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11541 21:47:03.235 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11542 21:47:03.235 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11543 21:47:03.235 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11544 21:47:03.235 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11545 21:47:03.235 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11546 21:47:03.235 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11547 21:47:03.235 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11548 21:47:03.235 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11550 21:47:03.235 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11551 21:47:03.235 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11552 21:47:03.235 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11553 21:47:03.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11554 21:47:03.235 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11555 21:47:03.235 0.00009560 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11556 21:47:03.235 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11557 21:47:03.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11558 21:47:03.235 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11559 21:47:03.235 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11560 21:47:03.235 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11561 21:47:03.235 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11562 21:47:03.235 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11563 21:47:03.235 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11564 21:47:03.235 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11565 21:47:03.235 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11566 21:47:03.235 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11567 21:47:03.235 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11568 21:47:03.235 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11569 21:47:03.235 0.00045551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11570 21:47:03.235 0.00030301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11571 21:47:03.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11572 21:47:03.235 0.02651537 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11573 21:47:03.266 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11574 21:47:03.266 0.01336652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11575 21:47:03.266 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11576 21:47:03.282 0.00032988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11577 21:47:03.282 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11578 21:47:03.282 0.00040652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11579 21:47:03.282 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11580 21:47:03.282 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11581 21:47:03.282 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11582 21:47:03.282 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11583 21:47:03.282 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 11584 21:47:03.282 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11585 21:47:03.282 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11586 21:47:03.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11587 21:47:03.282 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11588 21:47:03.282 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11589 21:47:03.282 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11590 21:47:03.282 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11591 21:47:03.282 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11592 21:47:03.282 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 11593 21:47:03.282 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11594 21:47:03.282 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11597 21:47:03.282 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11598 21:47:03.282 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11599 21:47:03.282 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11600 21:47:03.282 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11601 21:47:03.282 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11602 21:47:03.282 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11603 21:47:03.282 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11604 21:47:03.282 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11605 21:47:03.282 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11606 21:47:03.282 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11607 21:47:03.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11608 21:47:03.282 0.00020622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11609 21:47:03.282 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11610 21:47:03.282 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11611 21:47:03.282 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11612 21:47:03.282 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11613 21:47:03.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11614 21:47:03.282 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11615 21:47:03.282 0.00008296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11616 21:47:03.282 0.00007743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11617 21:47:03.282 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11618 21:47:03.282 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11619 21:47:03.282 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11620 21:47:03.282 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11621 21:47:03.282 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11622 21:47:03.282 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11623 21:47:03.282 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11624 21:47:03.282 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11625 21:47:03.282 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11626 21:47:03.282 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11627 21:47:03.282 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11628 21:47:03.282 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11629 21:47:03.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11630 21:47:03.282 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11631 21:47:03.282 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11632 21:47:03.282 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11633 21:47:03.282 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11634 21:47:03.282 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11635 21:47:03.282 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11636 21:47:03.282 0.02693887 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11637 21:47:03.312 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11638 21:47:03.312 0.01338233 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11639 21:47:03.312 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11640 21:47:03.328 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11641 21:47:03.328 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11642 21:47:03.328 0.00033185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11643 21:47:03.328 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11644 21:47:03.328 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11645 21:47:03.328 0.00030894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11646 21:47:03.328 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11647 21:47:03.328 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 11648 21:47:03.328 0.00028365 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11649 21:47:03.328 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11650 21:47:03.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11651 21:47:03.328 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11652 21:47:03.328 0.00032751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11653 21:47:03.328 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11654 21:47:03.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11655 21:47:03.328 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11656 21:47:03.328 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11657 21:47:03.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11658 21:47:03.328 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11659 21:47:03.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11660 21:47:03.328 0.00033778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11661 21:47:03.328 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11662 21:47:03.328 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11663 21:47:03.328 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11664 21:47:03.328 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11665 21:47:03.328 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11666 21:47:03.328 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11667 21:47:03.328 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11668 21:47:03.328 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11669 21:47:03.328 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11670 21:47:03.328 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11671 21:47:03.328 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11672 21:47:03.328 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11673 21:47:03.328 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11674 21:47:03.328 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11675 21:47:03.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11676 21:47:03.328 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11677 21:47:03.328 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11678 21:47:03.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11679 21:47:03.328 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11680 21:47:03.328 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11681 21:47:03.328 0.00025284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11682 21:47:03.328 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11683 21:47:03.328 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11684 21:47:03.328 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11685 21:47:03.328 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11686 21:47:03.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11687 21:47:03.328 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11688 21:47:03.328 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11689 21:47:03.328 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11690 21:47:03.328 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11691 21:47:03.328 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11692 21:47:03.328 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11693 21:47:03.328 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11694 21:47:03.328 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11695 21:47:03.328 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11696 21:47:03.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11697 21:47:03.328 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11698 21:47:03.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11699 21:47:03.328 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11700 21:47:03.328 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11701 21:47:03.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11702 21:47:03.328 0.02588129 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11703 21:47:03.359 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11704 21:47:03.359 0.01439092 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11705 21:47:03.359 0.00003081 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11706 21:47:03.375 0.00033620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11707 21:47:03.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11708 21:47:03.375 0.00041363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11709 21:47:03.375 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11710 21:47:03.375 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11711 21:47:03.375 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11712 21:47:03.375 0.00030617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11713 21:47:03.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11714 21:47:03.375 0.00036938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11715 21:47:03.375 0.00027299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 11716 21:47:03.375 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11717 21:47:03.375 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11718 21:47:03.375 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11719 21:47:03.375 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11720 21:47:03.375 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11721 21:47:03.375 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11722 21:47:03.375 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11723 21:47:03.375 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11724 21:47:03.375 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11725 21:47:03.375 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11726 21:47:03.375 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11727 21:47:03.375 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11728 21:47:03.375 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11729 21:47:03.375 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11730 21:47:03.375 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11731 21:47:03.375 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11732 21:47:03.375 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11733 21:47:03.375 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11734 21:47:03.375 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11736 21:47:03.375 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11737 21:47:03.375 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 11738 21:47:03.375 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11739 21:47:03.375 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 11740 21:47:03.375 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11741 21:47:03.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11742 21:47:03.375 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11743 21:47:03.375 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11744 21:47:03.375 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11745 21:47:03.375 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11746 21:47:03.375 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11747 21:47:03.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11748 21:47:03.375 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11749 21:47:03.375 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11750 21:47:03.375 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11751 21:47:03.375 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11752 21:47:03.375 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11753 21:47:03.375 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11754 21:47:03.375 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11755 21:47:03.375 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11756 21:47:03.375 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11757 21:47:03.375 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11758 21:47:03.375 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11759 21:47:03.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11760 21:47:03.375 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11761 21:47:03.375 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11762 21:47:03.375 0.00020622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11763 21:47:03.375 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11764 21:47:03.375 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11765 21:47:03.375 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11766 21:47:03.375 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11767 21:47:03.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11768 21:47:03.375 0.02818688 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11769 21:47:03.406 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11770 21:47:03.406 0.01312238 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11771 21:47:03.406 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11772 21:47:03.422 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11773 21:47:03.422 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11774 21:47:03.422 0.00036267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11775 21:47:03.422 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11776 21:47:03.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11777 21:47:03.422 0.00030854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11778 21:47:03.422 0.00032751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11779 21:47:03.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11780 21:47:03.422 0.00032474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11781 21:47:03.422 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 11782 21:47:03.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11783 21:47:03.422 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11784 21:47:03.422 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11785 21:47:03.422 0.00045077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11786 21:47:03.422 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11787 21:47:03.422 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11788 21:47:03.422 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11789 21:47:03.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11790 21:47:03.422 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11791 21:47:03.422 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11792 21:47:03.422 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11793 21:47:03.422 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11794 21:47:03.422 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11795 21:47:03.422 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11796 21:47:03.422 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11797 21:47:03.422 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11798 21:47:03.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11799 21:47:03.422 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11800 21:47:03.422 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11801 21:47:03.422 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11802 21:47:03.422 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11803 21:47:03.422 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11804 21:47:03.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11805 21:47:03.422 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11806 21:47:03.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11807 21:47:03.422 0.00027299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11808 21:47:03.422 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11809 21:47:03.422 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11810 21:47:03.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11811 21:47:03.422 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11812 21:47:03.422 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11813 21:47:03.422 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11814 21:47:03.422 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11815 21:47:03.422 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11816 21:47:03.422 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11817 21:47:03.422 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11818 21:47:03.422 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11819 21:47:03.422 0.00020583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11820 21:47:03.422 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11821 21:47:03.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11822 21:47:03.422 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11823 21:47:03.422 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11824 21:47:03.422 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11825 21:47:03.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11826 21:47:03.422 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11827 21:47:03.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11828 21:47:03.422 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11829 21:47:03.422 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11830 21:47:03.422 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11831 21:47:03.422 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11832 21:47:03.422 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11833 21:47:03.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11834 21:47:03.422 0.02671013 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11835 21:47:03.453 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11836 21:47:03.453 0.01393423 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11837 21:47:03.453 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11838 21:47:03.469 0.00030301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11839 21:47:03.469 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11840 21:47:03.469 0.00027259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11841 21:47:03.469 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11842 21:47:03.469 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11843 21:47:03.469 0.00042785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11844 21:47:03.469 0.00031921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11845 21:47:03.469 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 11846 21:47:03.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11847 21:47:03.469 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11848 21:47:03.469 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11849 21:47:03.469 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11850 21:47:03.469 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11851 21:47:03.469 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11852 21:47:03.469 0.00039664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11853 21:47:03.469 0.00044168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11854 21:47:03.469 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11855 21:47:03.469 0.00016435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11856 21:47:03.469 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11857 21:47:03.469 0.00036109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11858 21:47:03.469 0.00021096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11859 21:47:03.469 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11860 21:47:03.469 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11861 21:47:03.469 0.00024217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11863 21:47:03.469 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11864 21:47:03.469 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11865 21:47:03.469 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11866 21:47:03.469 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11867 21:47:03.469 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11868 21:47:03.469 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11869 21:47:03.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11870 21:47:03.469 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11871 21:47:03.469 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11872 21:47:03.469 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11873 21:47:03.469 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11874 21:47:03.469 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11875 21:47:03.469 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11876 21:47:03.469 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11877 21:47:03.469 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11878 21:47:03.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11880 21:47:03.469 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11881 21:47:03.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11882 21:47:03.469 0.00025165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11883 21:47:03.469 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11884 21:47:03.469 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11885 21:47:03.469 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11886 21:47:03.469 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11887 21:47:03.469 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11888 21:47:03.469 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11889 21:47:03.469 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11890 21:47:03.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11891 21:47:03.469 0.00021096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11892 21:47:03.469 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11893 21:47:03.469 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11894 21:47:03.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11895 21:47:03.469 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11896 21:47:03.469 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11897 21:47:03.469 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11898 21:47:03.469 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11899 21:47:03.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11900 21:47:03.469 0.02572011 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11901 21:47:03.500 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11902 21:47:03.500 0.01332307 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11903 21:47:03.500 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11904 21:47:03.516 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11905 21:47:03.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11906 21:47:03.516 0.00037491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11907 21:47:03.516 0.00032356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11908 21:47:03.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11909 21:47:03.516 0.00045590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11910 21:47:03.516 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 11911 21:47:03.516 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 11912 21:47:03.516 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11913 21:47:03.516 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11914 21:47:03.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11915 21:47:03.516 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11916 21:47:03.516 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11919 21:47:03.516 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11920 21:47:03.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11921 21:47:03.516 0.00029195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11922 21:47:03.516 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11923 21:47:03.516 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11924 21:47:03.516 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11925 21:47:03.516 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11926 21:47:03.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11927 21:47:03.516 0.00034094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11928 21:47:03.516 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11929 21:47:03.516 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11930 21:47:03.516 0.00035319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11931 21:47:03.516 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11932 21:47:03.516 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11933 21:47:03.516 0.00026114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11934 21:47:03.516 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11935 21:47:03.516 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11936 21:47:03.516 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11937 21:47:03.516 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11938 21:47:03.516 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11939 21:47:03.516 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11940 21:47:03.516 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11941 21:47:03.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11942 21:47:03.516 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11943 21:47:03.516 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11944 21:47:03.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11945 21:47:03.516 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11946 21:47:03.516 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11947 21:47:03.516 0.00008099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11948 21:47:03.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11949 21:47:03.516 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11950 21:47:03.516 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11951 21:47:03.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11952 21:47:03.516 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11953 21:47:03.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11954 21:47:03.516 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11955 21:47:03.516 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11956 21:47:03.516 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11957 21:47:03.516 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11958 21:47:03.516 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11959 21:47:03.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11960 21:47:03.516 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11961 21:47:03.516 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11962 21:47:03.516 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11963 21:47:03.516 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11964 21:47:03.516 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11965 21:47:03.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11966 21:47:03.516 0.02747971 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11967 21:47:03.547 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11968 21:47:03.547 0.01319902 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11969 21:47:03.547 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 11970 21:47:03.563 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 11971 21:47:03.563 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11972 21:47:03.563 0.00031605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11973 21:47:03.563 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 11974 21:47:03.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11975 21:47:03.563 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11976 21:47:03.563 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 11977 21:47:03.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11978 21:47:03.563 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11979 21:47:03.563 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 11980 21:47:03.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11981 21:47:03.563 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11982 21:47:03.563 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 11983 21:47:03.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11984 21:47:03.563 0.00029274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11985 21:47:03.563 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11986 21:47:03.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11987 21:47:03.563 0.00030459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11988 21:47:03.563 0.00031881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11989 21:47:03.563 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11990 21:47:03.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11991 21:47:03.563 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11992 21:47:03.563 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11993 21:47:03.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11994 21:47:03.563 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11995 21:47:03.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 11996 21:47:03.563 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11997 21:47:03.563 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11998 21:47:03.563 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 11999 21:47:03.563 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12000 21:47:03.563 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12001 21:47:03.563 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12002 21:47:03.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12003 21:47:03.563 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12004 21:47:03.563 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12005 21:47:03.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12006 21:47:03.563 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12007 21:47:03.563 0.00007506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12008 21:47:03.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12009 21:47:03.563 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12010 21:47:03.563 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12011 21:47:03.563 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12012 21:47:03.563 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12013 21:47:03.563 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12014 21:47:03.563 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12015 21:47:03.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12016 21:47:03.563 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12017 21:47:03.563 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12018 21:47:03.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12019 21:47:03.563 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12020 21:47:03.563 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12021 21:47:03.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12022 21:47:03.563 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12023 21:47:03.563 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12024 21:47:03.563 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12025 21:47:03.563 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12026 21:47:03.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12027 21:47:03.563 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12028 21:47:03.563 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12029 21:47:03.563 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12030 21:47:03.563 0.02702500 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12031 21:47:03.594 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12032 21:47:03.594 0.01402272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12033 21:47:03.594 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12034 21:47:03.610 0.00032237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12035 21:47:03.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12036 21:47:03.610 0.00035081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12037 21:47:03.610 0.00027536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12038 21:47:03.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12039 21:47:03.610 0.00033817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12040 21:47:03.610 0.00028484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 12041 21:47:03.610 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 12042 21:47:03.610 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12043 21:47:03.610 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12044 21:47:03.610 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12045 21:47:03.610 0.00032672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12046 21:47:03.610 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12047 21:47:03.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12048 21:47:03.610 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 12049 21:47:03.610 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12053 21:47:03.610 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12054 21:47:03.610 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12055 21:47:03.610 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12056 21:47:03.610 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12057 21:47:03.610 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12058 21:47:03.610 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12059 21:47:03.610 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12060 21:47:03.610 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12061 21:47:03.610 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12062 21:47:03.610 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12063 21:47:03.610 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12064 21:47:03.610 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12065 21:47:03.610 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12066 21:47:03.610 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12067 21:47:03.610 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12068 21:47:03.610 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12069 21:47:03.610 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12070 21:47:03.610 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12071 21:47:03.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12072 21:47:03.610 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12073 21:47:03.610 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12074 21:47:03.610 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12076 21:47:03.610 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12077 21:47:03.610 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12078 21:47:03.610 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12079 21:47:03.610 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12080 21:47:03.610 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12081 21:47:03.610 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12082 21:47:03.610 0.00044958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12083 21:47:03.610 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12084 21:47:03.610 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12085 21:47:03.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12086 21:47:03.610 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12087 21:47:03.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12088 21:47:03.610 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12089 21:47:03.610 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12090 21:47:03.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12091 21:47:03.610 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12092 21:47:03.610 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12093 21:47:03.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12094 21:47:03.610 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12095 21:47:03.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12096 21:47:03.610 0.02572090 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12097 21:47:03.641 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12098 21:47:03.641 0.01424791 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12099 21:47:03.641 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12100 21:47:03.657 0.00033027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12101 21:47:03.657 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12102 21:47:03.657 0.00039625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12103 21:47:03.657 0.00096079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12104 21:47:03.657 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12105 21:47:03.657 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12106 21:47:03.657 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 12107 21:47:03.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12108 21:47:03.657 0.00047131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12109 21:47:03.657 0.00031210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 12110 21:47:03.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12111 21:47:03.657 0.00035358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12112 21:47:03.657 0.00031012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12113 21:47:03.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12114 21:47:03.657 0.00022716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12115 21:47:03.657 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12116 21:47:03.657 0.00046578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12117 21:47:03.657 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12118 21:47:03.657 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12119 21:47:03.657 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12120 21:47:03.657 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12121 21:47:03.657 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12122 21:47:03.657 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12123 21:47:03.657 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12125 21:47:03.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12126 21:47:03.657 0.00032909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12127 21:47:03.657 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12128 21:47:03.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12129 21:47:03.657 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12130 21:47:03.657 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12131 21:47:03.657 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12132 21:47:03.657 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12133 21:47:03.657 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12134 21:47:03.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12135 21:47:03.657 0.00032909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12136 21:47:03.657 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12137 21:47:03.657 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12138 21:47:03.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12139 21:47:03.657 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12140 21:47:03.657 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12141 21:47:03.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12142 21:47:03.657 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12143 21:47:03.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12144 21:47:03.657 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12145 21:47:03.657 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12146 21:47:03.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12147 21:47:03.657 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12148 21:47:03.657 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12149 21:47:03.657 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12150 21:47:03.657 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12151 21:47:03.657 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12152 21:47:03.657 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12153 21:47:03.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12154 21:47:03.657 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12155 21:47:03.657 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12156 21:47:03.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12157 21:47:03.657 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12158 21:47:03.657 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12159 21:47:03.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12160 21:47:03.657 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12161 21:47:03.657 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12162 21:47:03.657 0.02547715 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12163 21:47:03.688 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12164 21:47:03.688 0.01369284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12165 21:47:03.688 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12166 21:47:03.704 0.00030025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12167 21:47:03.704 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12168 21:47:03.704 0.00039348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12169 21:47:03.704 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12170 21:47:03.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12171 21:47:03.704 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12172 21:47:03.704 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 12173 21:47:03.704 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 12174 21:47:03.704 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12175 21:47:03.704 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12176 21:47:03.704 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12177 21:47:03.704 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12178 21:47:03.704 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12179 21:47:03.704 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12180 21:47:03.704 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12181 21:47:03.704 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12182 21:47:03.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12183 21:47:03.704 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12184 21:47:03.704 0.00024652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12185 21:47:03.704 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12186 21:47:03.704 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12187 21:47:03.704 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12188 21:47:03.704 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12189 21:47:03.704 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12190 21:47:03.704 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12191 21:47:03.704 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12192 21:47:03.704 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12193 21:47:03.704 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12194 21:47:03.704 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12195 21:47:03.704 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12196 21:47:03.704 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12197 21:47:03.704 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12198 21:47:03.704 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12199 21:47:03.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12200 21:47:03.704 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12201 21:47:03.704 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12202 21:47:03.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12203 21:47:03.704 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 12207 21:47:03.704 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12208 21:47:03.704 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12209 21:47:03.704 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12210 21:47:03.704 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12211 21:47:03.704 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12212 21:47:03.704 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12213 21:47:03.704 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12214 21:47:03.704 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12215 21:47:03.704 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12216 21:47:03.704 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12217 21:47:03.704 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12218 21:47:03.704 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12219 21:47:03.704 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12220 21:47:03.704 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12221 21:47:03.704 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12222 21:47:03.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12223 21:47:03.704 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12224 21:47:03.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12225 21:47:03.704 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12226 21:47:03.704 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12227 21:47:03.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12228 21:47:03.704 0.02632732 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12229 21:47:03.735 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12230 21:47:03.735 0.02924564 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12231 21:47:03.735 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12232 21:47:03.766 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12233 21:47:03.766 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12234 21:47:03.766 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12235 21:47:03.766 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12236 21:47:03.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12237 21:47:03.766 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 12238 21:47:03.766 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12239 21:47:03.766 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12240 21:47:03.766 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12241 21:47:03.766 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 12242 21:47:03.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12243 21:47:03.766 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12244 21:47:03.766 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12245 21:47:03.766 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12246 21:47:03.766 0.00035753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12247 21:47:03.766 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12248 21:47:03.766 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12249 21:47:03.766 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12250 21:47:03.766 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12251 21:47:03.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12252 21:47:03.766 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12253 21:47:03.766 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12254 21:47:03.766 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12255 21:47:03.766 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12256 21:47:03.766 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12257 21:47:03.766 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12258 21:47:03.766 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12259 21:47:03.766 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12260 21:47:03.766 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12261 21:47:03.766 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12262 21:47:03.766 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12263 21:47:03.766 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12264 21:47:03.766 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12265 21:47:03.766 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12266 21:47:03.766 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12267 21:47:03.766 0.00023506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12268 21:47:03.766 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12269 21:47:03.766 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12270 21:47:03.766 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12271 21:47:03.766 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12272 21:47:03.766 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12273 21:47:03.766 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12274 21:47:03.766 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12275 21:47:03.766 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12276 21:47:03.766 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12277 21:47:03.766 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12278 21:47:03.766 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12279 21:47:03.766 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12280 21:47:03.766 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12281 21:47:03.766 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12282 21:47:03.766 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12283 21:47:03.766 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12284 21:47:03.766 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12285 21:47:03.766 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12286 21:47:03.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12287 21:47:03.766 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12288 21:47:03.766 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12289 21:47:03.766 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12290 21:47:03.766 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12291 21:47:03.766 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12292 21:47:03.766 0.02667379 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12293 21:47:03.797 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12294 21:47:03.797 0.01387457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12295 21:47:03.797 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12296 21:47:03.812 0.00027891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12297 21:47:03.812 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12298 21:47:03.812 0.00029156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12299 21:47:03.812 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12300 21:47:03.812 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12301 21:47:03.812 0.00023901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12302 21:47:03.812 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 12303 21:47:03.812 0.00029077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 12304 21:47:03.812 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12305 21:47:03.812 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12306 21:47:03.812 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12307 21:47:03.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12308 21:47:03.812 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12309 21:47:03.812 0.00026272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12310 21:47:03.812 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12311 21:47:03.812 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12312 21:47:03.812 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12313 21:47:03.812 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12314 21:47:03.812 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12315 21:47:03.812 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12316 21:47:03.812 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12317 21:47:03.812 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12318 21:47:03.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12319 21:47:03.812 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12320 21:47:03.812 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12321 21:47:03.812 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12322 21:47:03.812 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12323 21:47:03.812 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12324 21:47:03.812 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12325 21:47:03.812 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12326 21:47:03.812 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12327 21:47:03.812 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12328 21:47:03.812 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12329 21:47:03.812 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12330 21:47:03.812 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12331 21:47:03.812 0.00045432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12332 21:47:03.812 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12333 21:47:03.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12334 21:47:03.812 0.00037570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12335 21:47:03.812 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12336 21:47:03.812 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12337 21:47:03.812 0.00027654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12338 21:47:03.812 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12339 21:47:03.812 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12340 21:47:03.812 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12341 21:47:03.812 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12342 21:47:03.812 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12343 21:47:03.812 0.00028958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12344 21:47:03.812 0.00032790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12345 21:47:03.812 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12346 21:47:03.812 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12347 21:47:03.812 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12348 21:47:03.812 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12349 21:47:03.812 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12350 21:47:03.812 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12351 21:47:03.812 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12352 21:47:03.812 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12353 21:47:03.812 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12354 21:47:03.812 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12355 21:47:03.812 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12356 21:47:03.812 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12357 21:47:03.812 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12358 21:47:03.812 0.02638500 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12359 21:47:03.844 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12360 21:47:03.844 0.01299991 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12361 21:47:03.844 0.00000435 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12362 21:47:03.859 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12363 21:47:03.859 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12364 21:47:03.859 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12365 21:47:03.859 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12366 21:47:03.859 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12367 21:47:03.859 0.00026667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12368 21:47:03.859 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 12369 21:47:03.859 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12370 21:47:03.859 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12371 21:47:03.859 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 12372 21:47:03.859 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12373 21:47:03.859 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12374 21:47:03.859 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12375 21:47:03.859 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12376 21:47:03.859 0.00036741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12377 21:47:03.859 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12378 21:47:03.859 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12379 21:47:03.859 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12380 21:47:03.859 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12381 21:47:03.859 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12382 21:47:03.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12383 21:47:03.859 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12384 21:47:03.859 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12385 21:47:03.859 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12386 21:47:03.859 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12387 21:47:03.859 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12388 21:47:03.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12389 21:47:03.859 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12390 21:47:03.859 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12391 21:47:03.859 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12392 21:47:03.859 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12393 21:47:03.859 0.00008810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12394 21:47:03.859 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12395 21:47:03.859 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12396 21:47:03.859 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12397 21:47:03.859 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12398 21:47:03.859 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12399 21:47:03.859 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12400 21:47:03.859 0.00028563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12402 21:47:03.859 0.00008454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12403 21:47:03.859 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12404 21:47:03.859 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12405 21:47:03.859 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12406 21:47:03.859 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12407 21:47:03.859 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12408 21:47:03.859 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12409 21:47:03.859 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12410 21:47:03.859 0.00027496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12411 21:47:03.859 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12412 21:47:03.859 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12413 21:47:03.859 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12414 21:47:03.859 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12415 21:47:03.859 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12416 21:47:03.859 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12417 21:47:03.859 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12418 21:47:03.859 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12419 21:47:03.859 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12420 21:47:03.859 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12421 21:47:03.859 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12422 21:47:03.859 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12423 21:47:03.859 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12424 21:47:03.859 0.02687566 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12425 21:47:03.891 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12426 21:47:03.891 0.01332544 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12427 21:47:03.891 0.00002805 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12428 21:47:03.906 0.00033738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12429 21:47:03.906 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12430 21:47:03.906 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12431 21:47:03.906 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12432 21:47:03.906 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12435 21:47:03.906 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 12436 21:47:03.906 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12437 21:47:03.906 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12438 21:47:03.906 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12439 21:47:03.906 0.00040375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12440 21:47:03.906 0.00026430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12441 21:47:03.906 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12442 21:47:03.906 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12443 21:47:03.906 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12444 21:47:03.906 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12445 21:47:03.906 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12446 21:47:03.906 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12447 21:47:03.906 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 12450 21:47:03.906 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12451 21:47:03.906 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12452 21:47:03.906 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12453 21:47:03.906 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12454 21:47:03.906 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12455 21:47:03.906 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12456 21:47:03.906 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12457 21:47:03.906 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12458 21:47:03.906 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12459 21:47:03.906 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12460 21:47:03.906 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12461 21:47:03.906 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12462 21:47:03.906 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 12466 21:47:03.906 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12467 21:47:03.906 0.00028128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12468 21:47:03.906 0.00020622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12469 21:47:03.906 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12470 21:47:03.906 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12471 21:47:03.906 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12472 21:47:03.906 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12473 21:47:03.906 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12474 21:47:03.906 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12475 21:47:03.906 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12476 21:47:03.906 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12477 21:47:03.906 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12478 21:47:03.906 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12479 21:47:03.906 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12480 21:47:03.906 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12481 21:47:03.906 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12482 21:47:03.906 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12483 21:47:03.906 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12484 21:47:03.906 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12485 21:47:03.906 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12486 21:47:03.906 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12487 21:47:03.906 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12488 21:47:03.906 0.02672159 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12489 21:47:03.937 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12490 21:47:03.937 0.01435734 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12491 21:47:03.937 0.00003556 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12492 21:47:03.953 0.00038400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12493 21:47:03.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12494 21:47:03.953 0.00030064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12495 21:47:03.953 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12496 21:47:03.953 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12497 21:47:03.953 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12498 21:47:03.953 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 12499 21:47:03.953 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12500 21:47:03.953 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12501 21:47:03.953 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 12502 21:47:03.953 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12503 21:47:03.953 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12504 21:47:03.953 0.00040020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12505 21:47:03.953 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12506 21:47:03.953 0.00030143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12507 21:47:03.953 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12508 21:47:03.953 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12509 21:47:03.953 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12510 21:47:03.953 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12511 21:47:03.953 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12512 21:47:03.953 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12513 21:47:03.953 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12514 21:47:03.953 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12515 21:47:03.953 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12516 21:47:03.953 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12517 21:47:03.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12518 21:47:03.953 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12519 21:47:03.953 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12520 21:47:03.953 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12521 21:47:03.953 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12522 21:47:03.953 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12523 21:47:03.953 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12524 21:47:03.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12525 21:47:03.953 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12526 21:47:03.953 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12527 21:47:03.953 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12528 21:47:03.953 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12529 21:47:03.953 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12530 21:47:03.953 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12531 21:47:03.953 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12532 21:47:03.953 0.00007822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12533 21:47:03.953 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12534 21:47:03.953 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12535 21:47:03.953 0.00032514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12536 21:47:03.953 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12537 21:47:03.953 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12538 21:47:03.953 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12539 21:47:03.953 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12540 21:47:03.953 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12541 21:47:03.953 0.00007664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12542 21:47:03.953 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12543 21:47:03.953 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12544 21:47:03.953 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12545 21:47:03.953 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12546 21:47:03.953 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12547 21:47:03.953 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12548 21:47:03.953 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12549 21:47:03.953 0.00007941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12550 21:47:03.953 0.00007664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12551 21:47:03.953 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12552 21:47:03.953 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12553 21:47:03.953 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12554 21:47:03.953 0.02688594 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12555 21:47:03.985 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12556 21:47:03.985 0.01403378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12558 21:47:04.000 0.00049936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12559 21:47:04.000 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12560 21:47:04.000 0.00072296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12561 21:47:04.000 0.00045985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12562 21:47:04.000 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12563 21:47:04.000 0.00029195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12564 21:47:04.000 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 12565 21:47:04.000 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12566 21:47:04.000 0.00031842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12567 21:47:04.000 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 12568 21:47:04.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12569 21:47:04.000 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12570 21:47:04.000 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12571 21:47:04.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12572 21:47:04.000 0.00033422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12573 21:47:04.000 0.00026272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12574 21:47:04.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12575 21:47:04.000 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12576 21:47:04.000 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12577 21:47:04.000 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12578 21:47:04.000 0.00037965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12580 21:47:04.000 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12581 21:47:04.000 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12582 21:47:04.000 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12583 21:47:04.000 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12584 21:47:04.000 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12585 21:47:04.000 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12586 21:47:04.000 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12587 21:47:04.000 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12588 21:47:04.000 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12589 21:47:04.000 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12590 21:47:04.000 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12591 21:47:04.000 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12592 21:47:04.000 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12593 21:47:04.000 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12594 21:47:04.000 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12595 21:47:04.000 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12596 21:47:04.000 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12597 21:47:04.000 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12598 21:47:04.000 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12599 21:47:04.000 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12600 21:47:04.000 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12601 21:47:04.000 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12602 21:47:04.000 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12603 21:47:04.000 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12604 21:47:04.000 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12605 21:47:04.000 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12606 21:47:04.000 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12607 21:47:04.000 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12608 21:47:04.000 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12609 21:47:04.000 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12610 21:47:04.000 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12611 21:47:04.000 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12612 21:47:04.000 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12613 21:47:04.000 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12614 21:47:04.000 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12615 21:47:04.000 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12616 21:47:04.000 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12617 21:47:04.000 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12618 21:47:04.000 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12619 21:47:04.000 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12620 21:47:04.000 0.02570036 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12621 21:47:04.032 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12622 21:47:04.032 0.01464139 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12623 21:47:04.032 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12624 21:47:04.047 0.00030499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12625 21:47:04.047 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12626 21:47:04.047 0.00028168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12627 21:47:04.047 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12628 21:47:04.047 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12629 21:47:04.047 0.00041758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12630 21:47:04.047 0.00038637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 12631 21:47:04.047 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12632 21:47:04.047 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12633 21:47:04.047 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 12634 21:47:04.047 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12635 21:47:04.047 0.00028840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12636 21:47:04.047 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12637 21:47:04.047 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12638 21:47:04.047 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12639 21:47:04.047 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12640 21:47:04.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12641 21:47:04.047 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12642 21:47:04.047 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12643 21:47:04.047 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12644 21:47:04.047 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12645 21:47:04.047 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12646 21:47:04.047 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12647 21:47:04.047 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12648 21:47:04.047 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12649 21:47:04.047 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12650 21:47:04.047 0.00040573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12651 21:47:04.047 0.00046222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12652 21:47:04.047 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12653 21:47:04.047 0.00030617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12655 21:47:04.047 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12656 21:47:04.047 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12657 21:47:04.047 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12658 21:47:04.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12659 21:47:04.047 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12660 21:47:04.047 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12661 21:47:04.047 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12662 21:47:04.047 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12663 21:47:04.047 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12664 21:47:04.047 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12665 21:47:04.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12666 21:47:04.047 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 12670 21:47:04.047 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12671 21:47:04.047 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12672 21:47:04.047 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12673 21:47:04.047 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12674 21:47:04.047 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12675 21:47:04.047 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12676 21:47:04.047 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12677 21:47:04.047 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12678 21:47:04.047 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12679 21:47:04.047 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12680 21:47:04.047 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12681 21:47:04.047 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12682 21:47:04.047 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12683 21:47:04.047 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12684 21:47:04.047 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12685 21:47:04.047 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12686 21:47:04.047 0.02623606 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12687 21:47:04.079 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12688 21:47:04.079 0.01321561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12689 21:47:04.079 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12690 21:47:04.094 0.00033975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12691 21:47:04.094 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12692 21:47:04.094 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12693 21:47:04.094 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12694 21:47:04.094 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12695 21:47:04.094 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12696 21:47:04.094 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 12697 21:47:04.094 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12698 21:47:04.094 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: E0 12699 21:47:04.094 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12702 21:47:04.094 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12703 21:47:04.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12704 21:47:04.094 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12705 21:47:04.094 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12706 21:47:04.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12707 21:47:04.094 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12708 21:47:04.094 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12709 21:47:04.094 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12710 21:47:04.094 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12711 21:47:04.094 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12712 21:47:04.094 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12713 21:47:04.094 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12714 21:47:04.094 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12715 21:47:04.094 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12716 21:47:04.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12717 21:47:04.094 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12718 21:47:04.094 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12719 21:47:04.094 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12720 21:47:04.094 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12721 21:47:04.094 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12722 21:47:04.094 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12723 21:47:04.094 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12724 21:47:04.094 0.00008336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12725 21:47:04.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12726 21:47:04.094 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12727 21:47:04.094 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12728 21:47:04.094 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12729 21:47:04.094 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12730 21:47:04.094 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12731 21:47:04.094 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12732 21:47:04.094 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12733 21:47:04.094 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12734 21:47:04.094 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12735 21:47:04.094 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12736 21:47:04.094 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12737 21:47:04.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12738 21:47:04.094 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12739 21:47:04.094 0.00008652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12740 21:47:04.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12741 21:47:04.094 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12742 21:47:04.094 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12743 21:47:04.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12744 21:47:04.094 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12745 21:47:04.094 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12746 21:47:04.094 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12747 21:47:04.094 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12748 21:47:04.094 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12749 21:47:04.094 0.00026785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12750 21:47:04.094 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12751 21:47:04.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12752 21:47:04.094 0.02726283 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12753 21:47:04.125 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12754 21:47:04.125 0.01331359 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12755 21:47:04.125 0.00001462 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12756 21:47:04.141 0.00033462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12757 21:47:04.141 0.00030657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12758 21:47:04.141 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12759 21:47:04.141 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12760 21:47:04.141 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12761 21:47:04.141 0.00042904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12762 21:47:04.141 0.00036267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 12763 21:47:04.141 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12764 21:47:04.141 0.00038440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 12765 21:47:04.141 0.00043931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12766 21:47:04.141 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12767 21:47:04.141 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12768 21:47:04.141 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12769 21:47:04.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12770 21:47:04.141 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12771 21:47:04.141 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12772 21:47:04.141 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12773 21:47:04.141 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12774 21:47:04.141 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12775 21:47:04.141 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12776 21:47:04.141 0.00023664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12777 21:47:04.141 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12778 21:47:04.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12779 21:47:04.141 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 12780 21:47:04.141 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 12783 21:47:04.141 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12784 21:47:04.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12785 21:47:04.141 0.00032553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12786 21:47:04.141 0.00025877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12787 21:47:04.141 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12788 21:47:04.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12789 21:47:04.141 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12790 21:47:04.141 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12791 21:47:04.141 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12792 21:47:04.141 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12793 21:47:04.141 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12794 21:47:04.141 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12795 21:47:04.141 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12796 21:47:04.141 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12797 21:47:04.141 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12798 21:47:04.141 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12799 21:47:04.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12800 21:47:04.141 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12801 21:47:04.141 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12802 21:47:04.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12803 21:47:04.141 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12804 21:47:04.141 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12805 21:47:04.141 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12806 21:47:04.141 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12807 21:47:04.141 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12808 21:47:04.141 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12809 21:47:04.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12810 21:47:04.141 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12811 21:47:04.141 0.00028247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12812 21:47:04.141 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12813 21:47:04.141 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12814 21:47:04.141 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12815 21:47:04.141 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12816 21:47:04.141 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12817 21:47:04.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12818 21:47:04.141 0.02522115 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12819 21:47:04.172 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12820 21:47:04.172 0.01339141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12821 21:47:04.172 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12822 21:47:04.187 0.00029669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12823 21:47:04.187 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12824 21:47:04.187 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12825 21:47:04.187 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12826 21:47:04.187 0.00028840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 15 12827 21:47:04.187 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12828 21:47:04.187 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12829 21:47:04.187 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12830 21:47:04.187 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 12831 21:47:04.187 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12832 21:47:04.187 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12833 21:47:04.187 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12834 21:47:04.187 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12835 21:47:04.187 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12836 21:47:04.187 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12837 21:47:04.187 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12838 21:47:04.187 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12839 21:47:04.187 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12840 21:47:04.187 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12841 21:47:04.187 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12842 21:47:04.187 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12843 21:47:04.187 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12844 21:47:04.187 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12845 21:47:04.187 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12846 21:47:04.187 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12847 21:47:04.187 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12848 21:47:04.187 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12849 21:47:04.187 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12850 21:47:04.187 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12851 21:47:04.187 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12852 21:47:04.187 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12853 21:47:04.187 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12854 21:47:04.187 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12855 21:47:04.187 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12856 21:47:04.187 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12857 21:47:04.187 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12858 21:47:04.187 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12859 21:47:04.187 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12860 21:47:04.187 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12861 21:47:04.187 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12862 21:47:04.187 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12863 21:47:04.187 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12864 21:47:04.187 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12865 21:47:04.187 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12866 21:47:04.187 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12867 21:47:04.187 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12868 21:47:04.187 0.00007901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12869 21:47:04.187 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12870 21:47:04.187 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12871 21:47:04.187 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12872 21:47:04.187 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12873 21:47:04.187 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12874 21:47:04.187 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12875 21:47:04.187 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12876 21:47:04.187 0.00007111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12877 21:47:04.187 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12878 21:47:04.187 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12879 21:47:04.187 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12880 21:47:04.187 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12881 21:47:04.187 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12882 21:47:04.187 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12883 21:47:04.187 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12884 21:47:04.187 0.02736080 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12885 21:47:04.219 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12886 21:47:04.219 0.01418154 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12887 21:47:04.219 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12888 21:47:04.234 0.00030538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12889 21:47:04.234 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12890 21:47:04.234 0.00033146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12891 21:47:04.234 0.00027852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12892 21:47:04.234 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12893 21:47:04.234 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12894 21:47:04.234 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12895 21:47:04.234 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12896 21:47:04.234 0.00034054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12897 21:47:04.234 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 12898 21:47:04.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12899 21:47:04.234 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12900 21:47:04.234 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 12901 21:47:04.234 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12902 21:47:04.234 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12903 21:47:04.234 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12904 21:47:04.234 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12905 21:47:04.234 0.00027496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12906 21:47:04.234 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12907 21:47:04.234 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12908 21:47:04.234 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12909 21:47:04.234 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12910 21:47:04.234 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12911 21:47:04.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12912 21:47:04.234 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12913 21:47:04.234 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12914 21:47:04.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12915 21:47:04.234 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12916 21:47:04.234 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12917 21:47:04.234 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12918 21:47:04.234 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12919 21:47:04.234 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12920 21:47:04.234 0.00029116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12921 21:47:04.234 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12922 21:47:04.234 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12923 21:47:04.234 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12924 21:47:04.234 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12925 21:47:04.234 0.00030696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12926 21:47:04.234 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12927 21:47:04.234 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12928 21:47:04.234 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12929 21:47:04.234 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12930 21:47:04.234 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12931 21:47:04.234 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12932 21:47:04.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12933 21:47:04.234 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12934 21:47:04.234 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12935 21:47:04.234 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12936 21:47:04.234 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12937 21:47:04.234 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12938 21:47:04.234 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12939 21:47:04.234 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12940 21:47:04.234 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12941 21:47:04.234 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12942 21:47:04.234 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12943 21:47:04.234 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12944 21:47:04.234 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12945 21:47:04.234 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12946 21:47:04.234 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12947 21:47:04.234 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12948 21:47:04.234 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12949 21:47:04.234 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12950 21:47:04.234 0.02656238 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12951 21:47:04.266 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12952 21:47:04.266 0.01332662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12953 21:47:04.266 0.00001659 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 12954 21:47:04.281 0.00029235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 12955 21:47:04.281 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12956 21:47:04.281 0.00028800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12957 21:47:04.281 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 12958 21:47:04.281 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12959 21:47:04.281 0.00039309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12960 21:47:04.281 0.00034805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 12961 21:47:04.281 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12962 21:47:04.281 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 12963 21:47:04.281 0.00029432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12967 21:47:04.281 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12968 21:47:04.281 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12969 21:47:04.281 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12970 21:47:04.281 0.00024731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12971 21:47:04.281 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12972 21:47:04.281 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12973 21:47:04.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12974 21:47:04.281 0.00030815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12975 21:47:04.281 0.00032869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12976 21:47:04.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12977 21:47:04.281 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12978 21:47:04.281 0.00032079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12979 21:47:04.281 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12980 21:47:04.281 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12981 21:47:04.281 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12982 21:47:04.281 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12983 21:47:04.281 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12984 21:47:04.281 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12985 21:47:04.281 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12986 21:47:04.281 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12987 21:47:04.281 0.00026667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12988 21:47:04.281 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12989 21:47:04.281 0.00030973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12990 21:47:04.281 0.00029906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12991 21:47:04.281 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12992 21:47:04.281 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12993 21:47:04.281 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 12994 21:47:04.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12996 21:47:04.281 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12997 21:47:04.281 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 12998 21:47:04.281 0.00035556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 12999 21:47:04.281 0.00028840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13000 21:47:04.281 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13001 21:47:04.281 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13002 21:47:04.281 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13003 21:47:04.281 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13004 21:47:04.281 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13005 21:47:04.281 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13006 21:47:04.281 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13007 21:47:04.281 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13008 21:47:04.281 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13009 21:47:04.281 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13010 21:47:04.281 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13011 21:47:04.281 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13012 21:47:04.281 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13013 21:47:04.281 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13014 21:47:04.281 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13015 21:47:04.281 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13016 21:47:04.281 0.02671487 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13017 21:47:04.313 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13018 21:47:04.313 0.01313107 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13019 21:47:04.313 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13020 21:47:04.329 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13021 21:47:04.329 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13022 21:47:04.329 0.00035595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13023 21:47:04.329 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13024 21:47:04.329 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13025 21:47:04.329 0.00024415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13026 21:47:04.329 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13027 21:47:04.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13028 21:47:04.329 0.00031605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13029 21:47:04.329 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13030 21:47:04.329 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 13031 21:47:04.329 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13032 21:47:04.329 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13036 21:47:04.329 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13037 21:47:04.329 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13038 21:47:04.329 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13039 21:47:04.329 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13040 21:47:04.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13041 21:47:04.329 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13042 21:47:04.329 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13043 21:47:04.329 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13044 21:47:04.329 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13045 21:47:04.329 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 13046 21:47:04.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13047 21:47:04.329 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13049 21:47:04.329 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13050 21:47:04.329 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13051 21:47:04.329 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13052 21:47:04.329 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13053 21:47:04.329 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13054 21:47:04.329 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13055 21:47:04.329 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13056 21:47:04.329 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13057 21:47:04.329 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13058 21:47:04.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13059 21:47:04.329 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13060 21:47:04.329 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13061 21:47:04.329 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13062 21:47:04.329 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13063 21:47:04.329 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13064 21:47:04.329 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13065 21:47:04.329 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13066 21:47:04.329 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13067 21:47:04.329 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13068 21:47:04.329 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13069 21:47:04.329 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13070 21:47:04.329 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13071 21:47:04.329 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13072 21:47:04.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13073 21:47:04.329 0.00032988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13074 21:47:04.329 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13075 21:47:04.329 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13076 21:47:04.329 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13077 21:47:04.329 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13078 21:47:04.329 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13079 21:47:04.329 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13080 21:47:04.329 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13081 21:47:04.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13082 21:47:04.329 0.02665127 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13083 21:47:04.360 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13084 21:47:04.360 0.01296435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13085 21:47:04.360 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13086 21:47:04.376 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13087 21:47:04.376 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13088 21:47:04.376 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13089 21:47:04.376 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13090 21:47:04.376 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13091 21:47:04.376 0.00024573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13092 21:47:04.376 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13093 21:47:04.376 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13094 21:47:04.376 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13095 21:47:04.376 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13096 21:47:04.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13097 21:47:04.376 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13098 21:47:04.376 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13099 21:47:04.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13100 21:47:04.376 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13101 21:47:04.376 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13102 21:47:04.376 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13103 21:47:04.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13104 21:47:04.376 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13105 21:47:04.376 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13106 21:47:04.376 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13107 21:47:04.376 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13108 21:47:04.376 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 13109 21:47:04.376 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13110 21:47:04.376 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13113 21:47:04.376 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13114 21:47:04.376 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13115 21:47:04.376 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13116 21:47:04.376 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13117 21:47:04.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13118 21:47:04.376 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13119 21:47:04.376 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13120 21:47:04.376 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13121 21:47:04.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13122 21:47:04.376 0.00031131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13123 21:47:04.376 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13124 21:47:04.376 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13125 21:47:04.376 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13126 21:47:04.376 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13127 21:47:04.376 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13128 21:47:04.376 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13129 21:47:04.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13130 21:47:04.376 0.00023704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13131 21:47:04.376 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13132 21:47:04.376 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13133 21:47:04.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13134 21:47:04.376 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13135 21:47:04.376 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13136 21:47:04.376 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13137 21:47:04.376 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13138 21:47:04.376 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13139 21:47:04.376 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13140 21:47:04.376 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13141 21:47:04.376 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13142 21:47:04.376 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13143 21:47:04.376 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13144 21:47:04.376 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13145 21:47:04.376 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13146 21:47:04.376 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13147 21:47:04.376 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13148 21:47:04.376 0.02701394 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13149 21:47:04.406 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13150 21:47:04.406 0.01314845 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13151 21:47:04.406 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13152 21:47:04.422 0.00032514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13153 21:47:04.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13154 21:47:04.422 0.00040691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13155 21:47:04.422 0.00034686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13156 21:47:04.422 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13157 21:47:04.422 0.00045195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13158 21:47:04.422 0.00039190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13159 21:47:04.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13160 21:47:04.422 0.00039822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 13161 21:47:04.422 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13162 21:47:04.422 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13163 21:47:04.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13164 21:47:04.422 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13165 21:47:04.422 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 13166 21:47:04.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13167 21:47:04.422 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13170 21:47:04.422 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13171 21:47:04.422 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13172 21:47:04.422 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13173 21:47:04.422 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13174 21:47:04.422 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13175 21:47:04.422 0.00034765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13176 21:47:04.422 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13177 21:47:04.422 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13178 21:47:04.422 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13179 21:47:04.422 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13180 21:47:04.422 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13181 21:47:04.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13182 21:47:04.422 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13183 21:47:04.422 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13184 21:47:04.422 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13185 21:47:04.422 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13186 21:47:04.422 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13187 21:47:04.422 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13188 21:47:04.422 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13189 21:47:04.422 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13190 21:47:04.422 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13191 21:47:04.422 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13192 21:47:04.422 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13193 21:47:04.422 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13194 21:47:04.422 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13195 21:47:04.422 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13196 21:47:04.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13197 21:47:04.422 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13198 21:47:04.422 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13199 21:47:04.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13200 21:47:04.422 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13201 21:47:04.422 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13202 21:47:04.422 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13203 21:47:04.422 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13204 21:47:04.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13205 21:47:04.422 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13206 21:47:04.422 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13207 21:47:04.422 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13208 21:47:04.422 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13209 21:47:04.422 0.00025719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13210 21:47:04.422 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13211 21:47:04.422 0.00037570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13212 21:47:04.422 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13213 21:47:04.422 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13214 21:47:04.422 0.02678164 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13215 21:47:04.453 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13216 21:47:04.453 0.01258272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13217 21:47:04.453 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13218 21:47:04.469 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13219 21:47:04.469 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13220 21:47:04.469 0.00033738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13221 21:47:04.469 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13222 21:47:04.469 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13223 21:47:04.469 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13224 21:47:04.469 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13225 21:47:04.469 0.00030815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 13226 21:47:04.469 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13227 21:47:04.469 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13228 21:47:04.469 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13229 21:47:04.469 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13230 21:47:04.469 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13231 21:47:04.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13232 21:47:04.469 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13233 21:47:04.469 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13234 21:47:04.469 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13235 21:47:04.469 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13236 21:47:04.469 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13237 21:47:04.469 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13238 21:47:04.469 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13239 21:47:04.469 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13240 21:47:04.469 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13241 21:47:04.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13242 21:47:04.469 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13243 21:47:04.469 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13244 21:47:04.469 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13245 21:47:04.469 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13246 21:47:04.469 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13247 21:47:04.469 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13248 21:47:04.469 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13249 21:47:04.469 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13250 21:47:04.469 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13251 21:47:04.469 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13252 21:47:04.469 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13253 21:47:04.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13254 21:47:04.469 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13255 21:47:04.469 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13256 21:47:04.469 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13257 21:47:04.469 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13258 21:47:04.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13259 21:47:04.469 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13260 21:47:04.469 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13261 21:47:04.469 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13262 21:47:04.469 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13263 21:47:04.469 0.00025877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13264 21:47:04.469 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13265 21:47:04.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13266 21:47:04.469 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13267 21:47:04.469 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13268 21:47:04.469 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13270 21:47:04.469 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13271 21:47:04.469 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13272 21:47:04.469 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13273 21:47:04.469 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13274 21:47:04.469 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13275 21:47:04.469 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13276 21:47:04.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13277 21:47:04.469 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13278 21:47:04.469 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13279 21:47:04.469 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13280 21:47:04.469 0.02635458 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13281 21:47:04.500 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13282 21:47:04.500 0.01492583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13283 21:47:04.500 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13284 21:47:04.516 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13285 21:47:04.516 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13286 21:47:04.516 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13287 21:47:04.516 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13288 21:47:04.516 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13289 21:47:04.516 0.00148859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13290 21:47:04.516 0.00043694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13291 21:47:04.516 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13292 21:47:04.516 0.00048869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13293 21:47:04.516 0.00041244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 13294 21:47:04.516 0.00034054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13295 21:47:04.516 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13296 21:47:04.516 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13297 21:47:04.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13298 21:47:04.516 0.00045353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13299 21:47:04.516 0.00032553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13300 21:47:04.516 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13301 21:47:04.516 0.00043062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13302 21:47:04.516 0.00034963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13303 21:47:04.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13304 21:47:04.516 0.00039941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13305 21:47:04.516 0.00026153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13306 21:47:04.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13307 21:47:04.516 0.00026114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13308 21:47:04.516 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13309 21:47:04.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13310 21:47:04.516 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13311 21:47:04.516 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13312 21:47:04.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13313 21:47:04.516 0.00027891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13314 21:47:04.516 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13315 21:47:04.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13316 21:47:04.516 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13317 21:47:04.516 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13318 21:47:04.516 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13319 21:47:04.516 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13320 21:47:04.516 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13321 21:47:04.516 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13322 21:47:04.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13323 21:47:04.516 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13324 21:47:04.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13325 21:47:04.516 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13326 21:47:04.516 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13327 21:47:04.516 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13328 21:47:04.516 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13329 21:47:04.516 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13330 21:47:04.516 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13332 21:47:04.516 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13333 21:47:04.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13334 21:47:04.516 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13335 21:47:04.516 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13336 21:47:04.516 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13337 21:47:04.516 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13338 21:47:04.516 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13339 21:47:04.516 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13340 21:47:04.516 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13341 21:47:04.516 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13342 21:47:04.516 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13343 21:47:04.516 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13344 21:47:04.516 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13345 21:47:04.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13346 21:47:04.516 0.02443576 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13347 21:47:04.547 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13348 21:47:04.547 0.01421393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13349 21:47:04.547 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13350 21:47:04.563 0.00036069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13351 21:47:04.563 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13352 21:47:04.563 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13353 21:47:04.563 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13354 21:47:04.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13355 21:47:04.563 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13356 21:47:04.563 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13357 21:47:04.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13358 21:47:04.563 0.00034647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13359 21:47:04.563 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 13360 21:47:04.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13361 21:47:04.563 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13362 21:47:04.563 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13363 21:47:04.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13364 21:47:04.563 0.00031368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13365 21:47:04.563 0.00032316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13366 21:47:04.563 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13367 21:47:04.563 0.00025877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13368 21:47:04.563 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13369 21:47:04.563 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13370 21:47:04.563 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13371 21:47:04.563 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13372 21:47:04.563 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13373 21:47:04.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13374 21:47:04.563 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13375 21:47:04.563 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13376 21:47:04.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13377 21:47:04.563 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13378 21:47:04.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13379 21:47:04.563 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13380 21:47:04.563 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13381 21:47:04.563 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13382 21:47:04.563 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13383 21:47:04.563 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13384 21:47:04.563 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13385 21:47:04.563 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13386 21:47:04.563 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13387 21:47:04.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13388 21:47:04.563 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13389 21:47:04.563 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13390 21:47:04.563 0.00034568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13391 21:47:04.563 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13392 21:47:04.563 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13393 21:47:04.563 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13394 21:47:04.563 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13395 21:47:04.563 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13396 21:47:04.563 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13397 21:47:04.563 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13398 21:47:04.563 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13399 21:47:04.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13400 21:47:04.563 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13401 21:47:04.563 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13402 21:47:04.563 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13403 21:47:04.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13404 21:47:04.563 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13405 21:47:04.563 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13406 21:47:04.563 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13407 21:47:04.563 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13408 21:47:04.563 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13409 21:47:04.563 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13410 21:47:04.563 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13411 21:47:04.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13412 21:47:04.563 0.02659557 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13413 21:47:04.594 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13414 21:47:04.594 0.01295131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13415 21:47:04.594 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13416 21:47:04.610 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13417 21:47:04.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13418 21:47:04.610 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13419 21:47:04.610 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13420 21:47:04.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13421 21:47:04.610 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13422 21:47:04.610 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13423 21:47:04.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13424 21:47:04.610 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13425 21:47:04.610 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 13426 21:47:04.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13427 21:47:04.610 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13428 21:47:04.610 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13429 21:47:04.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13430 21:47:04.610 0.00027417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13431 21:47:04.610 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13432 21:47:04.610 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 87 13433 21:47:04.610 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13434 21:47:04.610 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13435 21:47:04.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13436 21:47:04.610 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13437 21:47:04.610 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 13438 21:47:04.610 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13439 21:47:04.610 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 13440 21:47:04.610 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13441 21:47:04.610 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13442 21:47:04.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13443 21:47:04.610 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13444 21:47:04.610 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 87 13445 21:47:04.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13446 21:47:04.610 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13447 21:47:04.610 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 49 13448 21:47:04.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13449 21:47:04.610 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13450 21:47:04.610 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13451 21:47:04.610 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 13452 21:47:04.610 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13453 21:47:04.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13454 21:47:04.610 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13455 21:47:04.610 0.00025995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13456 21:47:04.610 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13457 21:47:04.610 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13458 21:47:04.610 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13459 21:47:04.610 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13460 21:47:04.610 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 13461 21:47:04.610 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13462 21:47:04.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13463 21:47:04.610 0.00027457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13464 21:47:04.610 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 13465 21:47:04.610 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13466 21:47:04.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13467 21:47:04.610 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13468 21:47:04.610 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13469 21:47:04.610 0.00040810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13470 21:47:04.610 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13471 21:47:04.610 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13472 21:47:04.610 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 13473 21:47:04.610 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13474 21:47:04.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13475 21:47:04.610 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13476 21:47:04.610 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13477 21:47:04.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13478 21:47:04.610 0.02722569 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13479 21:47:04.641 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13480 21:47:04.641 0.01323813 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13481 21:47:04.641 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13482 21:47:04.656 0.00030894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13483 21:47:04.656 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13484 21:47:04.656 0.00029156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13485 21:47:04.656 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13486 21:47:04.656 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13487 21:47:04.656 0.00028365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13488 21:47:04.656 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13489 21:47:04.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13490 21:47:04.656 0.00035951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13491 21:47:04.656 0.00032237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 13492 21:47:04.656 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13493 21:47:04.656 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13494 21:47:04.656 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13495 21:47:04.656 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 49 13496 21:47:04.656 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13497 21:47:04.656 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13498 21:47:04.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13499 21:47:04.656 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13500 21:47:04.656 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 13501 21:47:04.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13502 21:47:04.656 0.00033027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13503 21:47:04.656 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 13504 21:47:04.656 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 13505 21:47:04.656 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13506 21:47:04.656 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13507 21:47:04.656 0.00034686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 13508 21:47:04.656 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13509 21:47:04.656 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13510 21:47:04.656 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13511 21:47:04.656 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13513 21:47:04.656 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13514 21:47:04.656 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13515 21:47:04.656 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13516 21:47:04.656 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13517 21:47:04.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13518 21:47:04.656 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13519 21:47:04.656 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13520 21:47:04.656 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13521 21:47:04.656 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13522 21:47:04.656 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13523 21:47:04.656 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13524 21:47:04.656 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13525 21:47:04.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13526 21:47:04.656 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13527 21:47:04.656 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13528 21:47:04.656 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13529 21:47:04.656 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13530 21:47:04.656 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13531 21:47:04.656 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13532 21:47:04.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13533 21:47:04.656 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13534 21:47:04.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13535 21:47:04.656 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13536 21:47:04.656 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13537 21:47:04.656 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13538 21:47:04.656 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13539 21:47:04.656 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13540 21:47:04.656 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13541 21:47:04.656 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13542 21:47:04.656 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13543 21:47:04.656 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13544 21:47:04.656 0.02643833 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13545 21:47:04.688 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13546 21:47:04.688 0.01386154 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13547 21:47:04.688 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13548 21:47:04.703 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13549 21:47:04.703 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13550 21:47:04.703 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13551 21:47:04.703 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13552 21:47:04.703 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13553 21:47:04.703 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13554 21:47:04.703 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13555 21:47:04.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13556 21:47:04.703 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13557 21:47:04.703 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13558 21:47:04.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13559 21:47:04.703 0.00037017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13560 21:47:04.703 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13561 21:47:04.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13562 21:47:04.703 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13563 21:47:04.703 0.00030143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13564 21:47:04.703 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13565 21:47:04.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13566 21:47:04.703 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13567 21:47:04.703 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 56 13568 21:47:04.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13569 21:47:04.703 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13570 21:47:04.703 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 13571 21:47:04.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13572 21:47:04.703 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13573 21:47:04.703 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13574 21:47:04.703 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13575 21:47:04.703 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13576 21:47:04.703 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13577 21:47:04.703 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13578 21:47:04.703 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13579 21:47:04.703 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13580 21:47:04.703 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13581 21:47:04.703 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13582 21:47:04.703 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 13583 21:47:04.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13584 21:47:04.703 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13585 21:47:04.703 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13586 21:47:04.703 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13587 21:47:04.703 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13588 21:47:04.703 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13589 21:47:04.703 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13590 21:47:04.703 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13591 21:47:04.703 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13592 21:47:04.703 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13593 21:47:04.703 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13594 21:47:04.703 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13595 21:47:04.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13596 21:47:04.703 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13597 21:47:04.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13598 21:47:04.703 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13599 21:47:04.703 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13600 21:47:04.703 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13601 21:47:04.703 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13602 21:47:04.703 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13603 21:47:04.703 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 13604 21:47:04.703 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13605 21:47:04.703 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13606 21:47:04.703 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13607 21:47:04.703 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13608 21:47:04.703 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13609 21:47:04.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13610 21:47:04.703 0.02814302 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13611 21:47:04.735 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13612 21:47:04.735 0.01366954 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13613 21:47:04.735 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13614 21:47:04.750 0.00042983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13615 21:47:04.750 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13616 21:47:04.750 0.00064277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13617 21:47:04.750 0.00033462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13618 21:47:04.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13619 21:47:04.750 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13620 21:47:04.750 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13621 21:47:04.750 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13622 21:47:04.750 0.00030341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13623 21:47:04.750 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 13624 21:47:04.750 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13625 21:47:04.750 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13626 21:47:04.750 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13627 21:47:04.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13628 21:47:04.750 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 13629 21:47:04.750 0.00026706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13630 21:47:04.750 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 13631 21:47:04.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13632 21:47:04.750 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13633 21:47:04.750 0.00008454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13634 21:47:04.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13635 21:47:04.750 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13636 21:47:04.750 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13637 21:47:04.750 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13638 21:47:04.750 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13639 21:47:04.750 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13640 21:47:04.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13641 21:47:04.750 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13642 21:47:04.750 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13643 21:47:04.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13644 21:47:04.750 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13645 21:47:04.750 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13646 21:47:04.750 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13647 21:47:04.750 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13648 21:47:04.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13649 21:47:04.750 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13650 21:47:04.750 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13651 21:47:04.750 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13652 21:47:04.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13653 21:47:04.750 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13654 21:47:04.750 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13655 21:47:04.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13656 21:47:04.750 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13657 21:47:04.750 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13658 21:47:04.750 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13659 21:47:04.750 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13660 21:47:04.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13661 21:47:04.750 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13662 21:47:04.750 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13663 21:47:04.750 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13664 21:47:04.750 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13665 21:47:04.750 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13666 21:47:04.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13667 21:47:04.750 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13668 21:47:04.750 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13669 21:47:04.750 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13670 21:47:04.750 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13671 21:47:04.750 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13672 21:47:04.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13673 21:47:04.750 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13674 21:47:04.750 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13675 21:47:04.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13676 21:47:04.750 0.02702500 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13677 21:47:04.781 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13678 21:47:04.781 0.01341670 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13679 21:47:04.781 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13680 21:47:04.797 0.00036188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13681 21:47:04.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13682 21:47:04.797 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13683 21:47:04.797 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13684 21:47:04.797 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13685 21:47:04.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13686 21:47:04.797 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13687 21:47:04.797 0.00024849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 13688 21:47:04.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13689 21:47:04.797 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13690 21:47:04.797 0.00029748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13691 21:47:04.797 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13692 21:47:04.797 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13693 21:47:04.797 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13694 21:47:04.797 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13695 21:47:04.797 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13696 21:47:04.797 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13697 21:47:04.797 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13698 21:47:04.797 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13699 21:47:04.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13700 21:47:04.797 0.00021057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13701 21:47:04.797 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 13702 21:47:04.797 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13703 21:47:04.797 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 13704 21:47:04.797 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13705 21:47:04.797 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13706 21:47:04.797 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13707 21:47:04.797 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13708 21:47:04.797 0.00030025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13709 21:47:04.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13710 21:47:04.797 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13711 21:47:04.797 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 13712 21:47:04.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13713 21:47:04.797 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13714 21:47:04.797 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 13715 21:47:04.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13716 21:47:04.797 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13717 21:47:04.797 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13718 21:47:04.797 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13720 21:47:04.797 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13721 21:47:04.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13722 21:47:04.797 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13723 21:47:04.797 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13724 21:47:04.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13725 21:47:04.797 0.00032040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13726 21:47:04.797 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13727 21:47:04.797 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13728 21:47:04.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13729 21:47:04.797 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13730 21:47:04.797 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13731 21:47:04.797 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13732 21:47:04.797 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13733 21:47:04.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13734 21:47:04.797 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13735 21:47:04.797 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13736 21:47:04.797 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13737 21:47:04.797 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 13738 21:47:04.797 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13739 21:47:04.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13740 21:47:04.797 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13741 21:47:04.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13742 21:47:04.797 0.02683418 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13743 21:47:04.828 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13744 21:47:04.828 0.01407092 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13746 21:47:04.844 0.00038044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13747 21:47:04.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13748 21:47:04.844 0.00032593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13749 21:47:04.844 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13750 21:47:04.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13751 21:47:04.844 0.00030025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13752 21:47:04.844 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13753 21:47:04.844 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 13754 21:47:04.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13755 21:47:04.844 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13756 21:47:04.844 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13757 21:47:04.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13758 21:47:04.844 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13759 21:47:04.844 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 13760 21:47:04.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13761 21:47:04.844 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13762 21:47:04.844 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13763 21:47:04.844 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13764 21:47:04.844 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 13765 21:47:04.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13766 21:47:04.844 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13767 21:47:04.844 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13768 21:47:04.844 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13769 21:47:04.844 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13770 21:47:04.844 0.00025561 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13771 21:47:04.844 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13772 21:47:04.844 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13773 21:47:04.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13774 21:47:04.844 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13775 21:47:04.844 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13776 21:47:04.844 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13777 21:47:04.844 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13778 21:47:04.844 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13779 21:47:04.844 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13780 21:47:04.844 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13781 21:47:04.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13782 21:47:04.844 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13783 21:47:04.844 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13784 21:47:04.844 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13785 21:47:04.844 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13786 21:47:04.844 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13787 21:47:04.844 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13788 21:47:04.844 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13789 21:47:04.844 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13790 21:47:04.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13791 21:47:04.844 0.00024889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13792 21:47:04.844 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13793 21:47:04.844 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13794 21:47:04.844 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13795 21:47:04.844 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13799 21:47:04.844 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13800 21:47:04.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13801 21:47:04.844 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13802 21:47:04.844 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 13803 21:47:04.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13804 21:47:04.844 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13807 21:47:04.875 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13808 21:47:04.875 0.01330529 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13809 21:47:04.875 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13810 21:47:04.891 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13811 21:47:04.891 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13812 21:47:04.891 0.00124642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13813 21:47:04.891 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13814 21:47:04.891 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13815 21:47:04.891 0.00055783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13816 21:47:04.891 0.00049343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13817 21:47:04.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13818 21:47:04.891 0.00028879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13819 21:47:04.891 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 13820 21:47:04.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13821 21:47:04.891 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13822 21:47:04.891 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13823 21:47:04.891 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13824 21:47:04.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13825 21:47:04.891 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 13826 21:47:04.891 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13827 21:47:04.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13828 21:47:04.891 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13830 21:47:04.891 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 13831 21:47:04.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13832 21:47:04.891 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13833 21:47:04.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13834 21:47:04.891 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13835 21:47:04.891 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13836 21:47:04.891 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 25 13837 21:47:04.891 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13838 21:47:04.891 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13839 21:47:04.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13840 21:47:04.891 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 13841 21:47:04.891 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13842 21:47:04.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13843 21:47:04.891 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 13844 21:47:04.891 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13845 21:47:04.891 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13846 21:47:04.891 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13847 21:47:04.891 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13848 21:47:04.891 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13849 21:47:04.891 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13850 21:47:04.891 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13851 21:47:04.891 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 13852 21:47:04.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13853 21:47:04.891 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13854 21:47:04.891 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13855 21:47:04.891 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13856 21:47:04.891 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 13857 21:47:04.891 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13858 21:47:04.891 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13859 21:47:04.891 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13860 21:47:04.891 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13861 21:47:04.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13862 21:47:04.891 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13863 21:47:04.891 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 13864 21:47:04.891 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13865 21:47:04.891 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13866 21:47:04.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13867 21:47:04.891 0.00008691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13868 21:47:04.891 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13869 21:47:04.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13870 21:47:04.891 0.02620169 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13871 21:47:04.922 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13872 21:47:04.922 0.01412623 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13873 21:47:04.922 0.00001462 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13874 21:47:04.938 0.00029748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13875 21:47:04.938 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13876 21:47:04.938 0.00039625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13877 21:47:04.938 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13878 21:47:04.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13879 21:47:04.938 0.00024217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13880 21:47:04.938 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 13881 21:47:04.938 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 13882 21:47:04.938 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13883 21:47:04.938 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13884 21:47:04.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13885 21:47:04.938 0.00026351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13886 21:47:04.938 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13887 21:47:04.938 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 13888 21:47:04.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13889 21:47:04.938 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13890 21:47:04.938 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 13891 21:47:04.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13892 21:47:04.938 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13893 21:47:04.938 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13894 21:47:04.938 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13895 21:47:04.938 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13896 21:47:04.938 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 13897 21:47:04.938 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13898 21:47:04.938 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13899 21:47:04.938 0.00033857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 33 13900 21:47:04.938 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13901 21:47:04.938 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13902 21:47:04.938 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13903 21:47:04.938 0.00022519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13904 21:47:04.938 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13905 21:47:04.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13906 21:47:04.938 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13907 21:47:04.938 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13908 21:47:04.938 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13909 21:47:04.938 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13910 21:47:04.938 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13911 21:47:04.938 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13912 21:47:04.938 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13913 21:47:04.938 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13914 21:47:04.938 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13915 21:47:04.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13916 21:47:04.938 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13917 21:47:04.938 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13918 21:47:04.938 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13919 21:47:04.938 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13920 21:47:04.938 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13921 21:47:04.938 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13922 21:47:04.938 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13923 21:47:04.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 13924 21:47:04.938 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13925 21:47:04.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13929 21:47:04.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13930 21:47:04.938 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13931 21:47:04.938 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 13932 21:47:04.938 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13933 21:47:04.938 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13934 21:47:04.938 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13935 21:47:04.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13936 21:47:04.938 0.02643596 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13937 21:47:04.969 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13938 21:47:04.969 0.01454973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13939 21:47:04.969 0.00001422 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 13940 21:47:04.985 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13941 21:47:04.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13942 21:47:04.985 0.00032356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13943 21:47:04.985 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 13944 21:47:04.985 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13945 21:47:04.985 0.00024257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13946 21:47:04.985 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 13947 21:47:04.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13948 21:47:04.985 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13949 21:47:04.985 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 13950 21:47:04.985 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13951 21:47:04.985 0.00031052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 13952 21:47:04.985 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13953 21:47:04.985 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13954 21:47:04.985 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13955 21:47:04.985 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13956 21:47:04.985 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 13957 21:47:04.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13958 21:47:04.985 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13959 21:47:04.985 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 13960 21:47:04.985 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13961 21:47:04.985 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13962 21:47:04.985 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 13963 21:47:04.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13964 21:47:04.985 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13965 21:47:04.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13966 21:47:04.985 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13967 21:47:04.985 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13968 21:47:04.985 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 13969 21:47:04.985 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13970 21:47:04.985 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13971 21:47:04.985 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 13972 21:47:04.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13973 21:47:04.985 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13974 21:47:04.985 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 13975 21:47:04.985 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13976 21:47:04.985 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 13977 21:47:04.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13978 21:47:04.985 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13979 21:47:04.985 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13980 21:47:04.985 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13981 21:47:04.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13983 21:47:04.985 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13984 21:47:04.985 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 13985 21:47:04.985 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13986 21:47:04.985 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 13987 21:47:04.985 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13988 21:47:04.985 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13989 21:47:04.985 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13990 21:47:04.985 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13991 21:47:04.985 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13992 21:47:04.985 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 13993 21:47:04.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13994 21:47:04.985 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13995 21:47:04.985 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 13996 21:47:04.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13997 21:47:04.985 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 13998 21:47:04.985 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 13999 21:47:04.985 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14000 21:47:04.985 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14001 21:47:04.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14002 21:47:04.985 0.02757650 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14003 21:47:05.016 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14004 21:47:05.016 0.01300662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14005 21:47:05.016 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14006 21:47:05.032 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14007 21:47:05.032 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14008 21:47:05.032 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14009 21:47:05.032 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14010 21:47:05.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14011 21:47:05.032 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14012 21:47:05.032 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14013 21:47:05.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14014 21:47:05.032 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14015 21:47:05.032 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 14016 21:47:05.032 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14017 21:47:05.032 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14018 21:47:05.032 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14019 21:47:05.032 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 14020 21:47:05.032 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14021 21:47:05.032 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14022 21:47:05.032 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 14023 21:47:05.032 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14024 21:47:05.032 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14025 21:47:05.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14026 21:47:05.032 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14027 21:47:05.032 0.00032316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14028 21:47:05.032 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 14029 21:47:05.032 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 35 14030 21:47:05.032 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14031 21:47:05.032 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14032 21:47:05.032 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14033 21:47:05.032 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14034 21:47:05.032 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14035 21:47:05.032 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14036 21:47:05.032 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14037 21:47:05.032 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14038 21:47:05.032 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14039 21:47:05.032 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14040 21:47:05.032 0.00028168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14041 21:47:05.032 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14042 21:47:05.032 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14043 21:47:05.032 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14044 21:47:05.032 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14045 21:47:05.032 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14046 21:47:05.032 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14047 21:47:05.032 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14048 21:47:05.032 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 14049 21:47:05.032 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 14053 21:47:05.032 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14054 21:47:05.032 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14055 21:47:05.032 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14056 21:47:05.032 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14057 21:47:05.032 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14058 21:47:05.032 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14059 21:47:05.032 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14060 21:47:05.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14061 21:47:05.032 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14062 21:47:05.032 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14063 21:47:05.032 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14064 21:47:05.032 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14065 21:47:05.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14066 21:47:05.032 0.02893710 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14067 21:47:05.063 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14068 21:47:05.063 0.01211102 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14069 21:47:05.063 0.00002173 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14070 21:47:05.079 0.00036109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14071 21:47:05.079 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14072 21:47:05.079 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14073 21:47:05.079 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14074 21:47:05.079 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14075 21:47:05.079 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14076 21:47:05.079 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14077 21:47:05.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14078 21:47:05.079 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 14079 21:47:05.079 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14080 21:47:05.079 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14081 21:47:05.079 0.00026390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14082 21:47:05.079 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14083 21:47:05.079 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 14084 21:47:05.079 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14085 21:47:05.079 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 14086 21:47:05.079 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14087 21:47:05.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14088 21:47:05.079 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14089 21:47:05.079 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14090 21:47:05.079 0.00037689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14091 21:47:05.079 0.00032079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 14092 21:47:05.079 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 14094 21:47:05.079 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14095 21:47:05.079 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14096 21:47:05.079 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14097 21:47:05.079 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 14098 21:47:05.079 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 12 14099 21:47:05.079 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14100 21:47:05.079 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14101 21:47:05.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14102 21:47:05.079 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 29 14103 21:47:05.079 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14104 21:47:05.079 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 14105 21:47:05.079 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14106 21:47:05.079 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14107 21:47:05.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14108 21:47:05.079 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14109 21:47:05.079 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14110 21:47:05.079 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14111 21:47:05.079 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14112 21:47:05.079 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14113 21:47:05.079 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 14114 21:47:05.079 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14115 21:47:05.079 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14116 21:47:05.079 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 14117 21:47:05.079 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14118 21:47:05.079 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14119 21:47:05.079 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14120 21:47:05.079 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14121 21:47:05.079 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14122 21:47:05.079 0.00026153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14123 21:47:05.079 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14124 21:47:05.079 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14125 21:47:05.079 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 14126 21:47:05.079 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14127 21:47:05.079 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14128 21:47:05.079 0.00030380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14129 21:47:05.079 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14130 21:47:05.079 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14131 21:47:05.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14132 21:47:05.079 0.02629808 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14133 21:47:05.110 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14134 21:47:05.110 0.01365255 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14136 21:47:05.125 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14137 21:47:05.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14138 21:47:05.125 0.00021096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14139 21:47:05.125 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14140 21:47:05.125 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14141 21:47:05.125 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14142 21:47:05.125 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14143 21:47:05.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14144 21:47:05.125 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14145 21:47:05.125 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 14146 21:47:05.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14147 21:47:05.125 0.00033778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14148 21:47:05.125 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14149 21:47:05.125 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 14150 21:47:05.125 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14151 21:47:05.125 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14152 21:47:05.125 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14153 21:47:05.125 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 14154 21:47:05.125 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14155 21:47:05.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14156 21:47:05.125 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14157 21:47:05.125 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14158 21:47:05.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14159 21:47:05.125 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 31 14160 21:47:05.125 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14161 21:47:05.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14162 21:47:05.125 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14163 21:47:05.125 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 14164 21:47:05.125 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 41 14165 21:47:05.125 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14166 21:47:05.125 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14167 21:47:05.125 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14168 21:47:05.125 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14169 21:47:05.125 0.00016869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14170 21:47:05.125 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14171 21:47:05.125 0.00033620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14172 21:47:05.125 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14173 21:47:05.125 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14174 21:47:05.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14175 21:47:05.125 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14176 21:47:05.125 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14177 21:47:05.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14178 21:47:05.125 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14179 21:47:05.125 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14180 21:47:05.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14181 21:47:05.125 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14182 21:47:05.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14183 21:47:05.125 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14184 21:47:05.125 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14185 21:47:05.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14186 21:47:05.125 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14187 21:47:05.125 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14188 21:47:05.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14189 21:47:05.125 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14190 21:47:05.125 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14191 21:47:05.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14192 21:47:05.125 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14193 21:47:05.125 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14194 21:47:05.125 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14195 21:47:05.125 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14196 21:47:05.125 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14197 21:47:05.125 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14198 21:47:05.125 0.02735843 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14199 21:47:05.157 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14200 21:47:05.157 0.01353917 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14201 21:47:05.157 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14202 21:47:05.172 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14203 21:47:05.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14204 21:47:05.172 0.00033778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14205 21:47:05.172 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14206 21:47:05.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14207 21:47:05.172 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14208 21:47:05.172 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14209 21:47:05.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14210 21:47:05.172 0.00032277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14211 21:47:05.172 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 14212 21:47:05.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14213 21:47:05.172 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14214 21:47:05.172 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14215 21:47:05.172 0.00029709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14216 21:47:05.172 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14217 21:47:05.172 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14218 21:47:05.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14219 21:47:05.172 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14220 21:47:05.172 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 14221 21:47:05.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14222 21:47:05.172 0.00036780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14223 21:47:05.172 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 13 14224 21:47:05.172 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 14225 21:47:05.172 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14226 21:47:05.172 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14227 21:47:05.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14228 21:47:05.172 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14229 21:47:05.172 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14230 21:47:05.172 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14231 21:47:05.172 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14232 21:47:05.172 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 14233 21:47:05.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14234 21:47:05.172 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 29 14235 21:47:05.172 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14236 21:47:05.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14237 21:47:05.172 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14238 21:47:05.172 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 14239 21:47:05.172 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14240 21:47:05.172 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14241 21:47:05.172 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14242 21:47:05.172 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14243 21:47:05.172 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14244 21:47:05.172 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14245 21:47:05.172 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 75 14246 21:47:05.172 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14247 21:47:05.172 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14248 21:47:05.172 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 14249 21:47:05.172 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14250 21:47:05.172 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14251 21:47:05.172 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14252 21:47:05.172 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14253 21:47:05.172 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14254 21:47:05.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14255 21:47:05.172 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14256 21:47:05.172 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14257 21:47:05.172 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14258 21:47:05.172 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14259 21:47:05.172 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 14260 21:47:05.172 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 14261 21:47:05.172 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14262 21:47:05.172 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14263 21:47:05.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14265 21:47:05.204 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14266 21:47:05.204 0.01244563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14267 21:47:05.204 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14268 21:47:05.219 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14269 21:47:05.219 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14270 21:47:05.219 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14271 21:47:05.219 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14272 21:47:05.219 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14273 21:47:05.219 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14274 21:47:05.219 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14275 21:47:05.219 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 14276 21:47:05.219 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14277 21:47:05.219 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14278 21:47:05.219 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14279 21:47:05.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14280 21:47:05.219 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14281 21:47:05.219 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 52 14282 21:47:05.219 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14283 21:47:05.219 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14284 21:47:05.219 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14285 21:47:05.219 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14286 21:47:05.219 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 14287 21:47:05.219 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14288 21:47:05.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14289 21:47:05.219 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14290 21:47:05.219 0.00008020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 14291 21:47:05.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14292 21:47:05.219 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14293 21:47:05.219 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 32 14294 21:47:05.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14295 21:47:05.219 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14296 21:47:05.219 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14297 21:47:05.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14298 21:47:05.219 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14299 21:47:05.219 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14300 21:47:05.219 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14301 21:47:05.219 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14302 21:47:05.219 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14303 21:47:05.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14304 21:47:05.219 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14305 21:47:05.219 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14306 21:47:05.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14307 21:47:05.219 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14308 21:47:05.219 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14309 21:47:05.219 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14310 21:47:05.219 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14311 21:47:05.219 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14312 21:47:05.219 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14313 21:47:05.219 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14314 21:47:05.219 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14315 21:47:05.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14316 21:47:05.219 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14317 21:47:05.219 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14318 21:47:05.219 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14319 21:47:05.219 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14320 21:47:05.219 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14321 21:47:05.219 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14322 21:47:05.219 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14323 21:47:05.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14324 21:47:05.219 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 14325 21:47:05.219 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 14328 21:47:05.219 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14329 21:47:05.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14330 21:47:05.219 0.02835320 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14331 21:47:05.251 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14332 21:47:05.251 0.01382164 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14333 21:47:05.251 0.00000395 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14334 21:47:05.266 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14335 21:47:05.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14336 21:47:05.266 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14337 21:47:05.266 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14338 21:47:05.266 0.00047052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14339 21:47:05.266 0.00026074 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14340 21:47:05.266 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14341 21:47:05.266 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14342 21:47:05.266 0.00031526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14343 21:47:05.266 0.00038202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 14344 21:47:05.266 0.00088691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14345 21:47:05.266 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14346 21:47:05.266 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14347 21:47:05.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14348 21:47:05.266 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14349 21:47:05.266 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14350 21:47:05.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14351 21:47:05.266 0.00021136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14352 21:47:05.266 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14353 21:47:05.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14354 21:47:05.266 0.00025047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14355 21:47:05.266 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14356 21:47:05.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14357 21:47:05.266 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14358 21:47:05.266 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14359 21:47:05.266 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14360 21:47:05.266 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14361 21:47:05.266 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14362 21:47:05.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14363 21:47:05.266 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14364 21:47:05.266 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14365 21:47:05.266 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14366 21:47:05.266 0.00029630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14367 21:47:05.266 0.00032198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14368 21:47:05.266 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14369 21:47:05.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14370 21:47:05.266 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14371 21:47:05.266 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14372 21:47:05.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14373 21:47:05.266 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14374 21:47:05.266 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14375 21:47:05.266 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14376 21:47:05.266 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14377 21:47:05.266 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14378 21:47:05.266 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14380 21:47:05.266 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14381 21:47:05.266 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14382 21:47:05.266 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14383 21:47:05.266 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14384 21:47:05.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14385 21:47:05.266 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14386 21:47:05.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14387 21:47:05.266 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14388 21:47:05.266 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14389 21:47:05.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14390 21:47:05.266 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14391 21:47:05.266 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14392 21:47:05.266 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14393 21:47:05.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14394 21:47:05.266 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14395 21:47:05.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14396 21:47:05.266 0.02570273 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14397 21:47:05.297 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14398 21:47:05.297 0.01298647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14399 21:47:05.297 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14400 21:47:05.312 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14401 21:47:05.312 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14402 21:47:05.312 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14403 21:47:05.312 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14404 21:47:05.312 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14405 21:47:05.312 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14406 21:47:05.312 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14407 21:47:05.312 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14408 21:47:05.312 0.00045353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14409 21:47:05.312 0.00057007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 14410 21:47:05.312 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14411 21:47:05.312 0.00036109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14412 21:47:05.312 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14413 21:47:05.312 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 14415 21:47:05.312 0.00027338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14416 21:47:05.312 0.00034370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14417 21:47:05.312 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14418 21:47:05.312 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14420 21:47:05.312 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14421 21:47:05.312 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14422 21:47:05.312 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14423 21:47:05.312 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14424 21:47:05.312 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14425 21:47:05.312 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14426 21:47:05.312 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14427 21:47:05.312 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14428 21:47:05.312 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14429 21:47:05.312 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14430 21:47:05.312 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14431 21:47:05.312 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14432 21:47:05.312 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14433 21:47:05.312 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14434 21:47:05.312 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14435 21:47:05.312 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14436 21:47:05.312 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14437 21:47:05.312 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14438 21:47:05.312 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14439 21:47:05.312 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14440 21:47:05.312 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14441 21:47:05.312 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14442 21:47:05.312 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14443 21:47:05.312 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14444 21:47:05.312 0.00032514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14445 21:47:05.312 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14446 21:47:05.312 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14447 21:47:05.312 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14448 21:47:05.312 0.00030341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14449 21:47:05.312 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14450 21:47:05.312 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14451 21:47:05.312 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14452 21:47:05.312 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14453 21:47:05.312 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14454 21:47:05.312 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14455 21:47:05.312 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14456 21:47:05.312 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14457 21:47:05.312 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14458 21:47:05.312 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14459 21:47:05.312 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14460 21:47:05.312 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14461 21:47:05.312 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14462 21:47:05.312 0.02785147 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14463 21:47:05.344 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14464 21:47:05.344 0.01224613 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14465 21:47:05.344 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14466 21:47:05.359 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14467 21:47:05.359 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14468 21:47:05.359 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14469 21:47:05.359 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14470 21:47:05.359 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14471 21:47:05.359 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14472 21:47:05.359 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14473 21:47:05.359 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 14474 21:47:05.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14475 21:47:05.359 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14476 21:47:05.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14477 21:47:05.359 0.00031881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14478 21:47:05.359 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14479 21:47:05.359 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14480 21:47:05.359 0.00033778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14481 21:47:05.359 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14482 21:47:05.359 0.00028563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14483 21:47:05.359 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14484 21:47:05.359 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14485 21:47:05.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14486 21:47:05.359 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14487 21:47:05.359 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14488 21:47:05.359 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14489 21:47:05.359 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14490 21:47:05.359 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14491 21:47:05.359 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14492 21:47:05.359 0.00030617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14493 21:47:05.359 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14494 21:47:05.359 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14495 21:47:05.359 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 14496 21:47:05.359 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 14498 21:47:05.359 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14499 21:47:05.359 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14500 21:47:05.359 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14501 21:47:05.359 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14502 21:47:05.359 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14503 21:47:05.359 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14504 21:47:05.359 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14505 21:47:05.359 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14506 21:47:05.359 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14507 21:47:05.359 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14508 21:47:05.359 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14509 21:47:05.359 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14510 21:47:05.359 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14511 21:47:05.359 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14512 21:47:05.359 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14513 21:47:05.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14514 21:47:05.359 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14515 21:47:05.359 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14516 21:47:05.359 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14517 21:47:05.359 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14518 21:47:05.359 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14519 21:47:05.359 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14520 21:47:05.359 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14521 21:47:05.359 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14522 21:47:05.359 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14523 21:47:05.359 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14524 21:47:05.359 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14525 21:47:05.359 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14526 21:47:05.359 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14527 21:47:05.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14528 21:47:05.359 0.02561897 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14529 21:47:05.391 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14530 21:47:05.391 0.01459043 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14531 21:47:05.391 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14532 21:47:05.406 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14533 21:47:05.406 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14534 21:47:05.406 0.00042351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14535 21:47:05.406 0.00038598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14536 21:47:05.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14537 21:47:05.406 0.00023901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14538 21:47:05.406 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14539 21:47:05.406 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14540 21:47:05.406 0.00021057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14541 21:47:05.406 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 14542 21:47:05.406 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14543 21:47:05.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14544 21:47:05.406 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14545 21:47:05.406 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14546 21:47:05.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14547 21:47:05.406 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14548 21:47:05.406 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14549 21:47:05.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14550 21:47:05.406 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14551 21:47:05.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14552 21:47:05.406 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14553 21:47:05.406 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14554 21:47:05.406 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14555 21:47:05.406 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14556 21:47:05.406 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14557 21:47:05.406 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14558 21:47:05.406 0.00043615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14560 21:47:05.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14561 21:47:05.406 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14562 21:47:05.406 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14563 21:47:05.406 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14564 21:47:05.406 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14565 21:47:05.406 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14566 21:47:05.406 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14567 21:47:05.406 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14568 21:47:05.406 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14569 21:47:05.406 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14570 21:47:05.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14571 21:47:05.406 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14572 21:47:05.406 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14573 21:47:05.406 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14574 21:47:05.406 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14575 21:47:05.406 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14576 21:47:05.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14577 21:47:05.406 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14578 21:47:05.406 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14579 21:47:05.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14580 21:47:05.406 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14581 21:47:05.406 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14582 21:47:05.406 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14583 21:47:05.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14584 21:47:05.406 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14585 21:47:05.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14586 21:47:05.406 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14587 21:47:05.406 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14588 21:47:05.406 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14589 21:47:05.406 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14590 21:47:05.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14591 21:47:05.406 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14592 21:47:05.406 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14593 21:47:05.406 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14594 21:47:05.406 0.02789413 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14595 21:47:05.438 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14596 21:47:05.438 0.01351349 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14597 21:47:05.438 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14598 21:47:05.453 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14599 21:47:05.453 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14600 21:47:05.453 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14601 21:47:05.453 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14602 21:47:05.453 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14603 21:47:05.453 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14604 21:47:05.453 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14605 21:47:05.453 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 14606 21:47:05.453 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14607 21:47:05.453 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14608 21:47:05.453 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14609 21:47:05.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14610 21:47:05.453 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14611 21:47:05.453 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14612 21:47:05.453 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14613 21:47:05.453 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14614 21:47:05.453 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14615 21:47:05.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14616 21:47:05.453 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14617 21:47:05.453 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14618 21:47:05.453 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14619 21:47:05.453 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14620 21:47:05.453 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14621 21:47:05.453 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14622 21:47:05.453 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14623 21:47:05.453 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14624 21:47:05.453 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14625 21:47:05.453 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14626 21:47:05.453 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14627 21:47:05.453 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14628 21:47:05.453 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14629 21:47:05.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14630 21:47:05.453 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14631 21:47:05.453 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14632 21:47:05.453 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14633 21:47:05.453 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14634 21:47:05.453 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14635 21:47:05.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14636 21:47:05.453 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14637 21:47:05.453 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14638 21:47:05.453 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14639 21:47:05.453 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14640 21:47:05.453 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14641 21:47:05.453 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14642 21:47:05.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14643 21:47:05.453 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14644 21:47:05.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14645 21:47:05.453 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14646 21:47:05.453 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14647 21:47:05.453 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14648 21:47:05.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14649 21:47:05.453 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14650 21:47:05.453 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14651 21:47:05.453 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14652 21:47:05.453 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14653 21:47:05.453 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14654 21:47:05.453 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14655 21:47:05.453 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14656 21:47:05.453 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14657 21:47:05.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14658 21:47:05.453 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14659 21:47:05.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14660 21:47:05.453 0.02896949 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14661 21:47:05.485 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14662 21:47:05.485 0.01290983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14663 21:47:05.485 0.00001185 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14664 21:47:05.500 0.00029432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14665 21:47:05.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14666 21:47:05.500 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14667 21:47:05.500 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14668 21:47:05.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14669 21:47:05.500 0.00038993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14670 21:47:05.500 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14671 21:47:05.500 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 14672 21:47:05.500 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14673 21:47:05.500 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14674 21:47:05.500 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14675 21:47:05.500 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14676 21:47:05.500 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14677 21:47:05.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14678 21:47:05.500 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14679 21:47:05.500 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14680 21:47:05.500 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14681 21:47:05.500 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14682 21:47:05.500 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14683 21:47:05.500 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14684 21:47:05.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14685 21:47:05.500 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14686 21:47:05.500 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14687 21:47:05.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14688 21:47:05.500 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14689 21:47:05.500 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14690 21:47:05.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14691 21:47:05.500 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14692 21:47:05.500 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14693 21:47:05.500 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14694 21:47:05.500 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14695 21:47:05.500 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14696 21:47:05.500 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14697 21:47:05.500 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14698 21:47:05.500 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14699 21:47:05.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14700 21:47:05.500 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14701 21:47:05.500 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14702 21:47:05.500 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14703 21:47:05.500 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14704 21:47:05.500 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14705 21:47:05.500 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14706 21:47:05.500 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14707 21:47:05.500 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14708 21:47:05.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14709 21:47:05.500 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14711 21:47:05.500 0.00025561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14712 21:47:05.500 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14713 21:47:05.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14714 21:47:05.500 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14715 21:47:05.500 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14716 21:47:05.500 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14717 21:47:05.500 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14718 21:47:05.500 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14719 21:47:05.500 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14720 21:47:05.500 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14721 21:47:05.500 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14722 21:47:05.500 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14723 21:47:05.500 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14724 21:47:05.500 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14725 21:47:05.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14726 21:47:05.500 0.02605354 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14727 21:47:05.531 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14728 21:47:05.531 0.01440080 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14729 21:47:05.531 0.00001936 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14730 21:47:05.547 0.00035279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14731 21:47:05.547 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14732 21:47:05.547 0.00035398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14733 21:47:05.547 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14734 21:47:05.547 0.00029037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14735 21:47:05.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14736 21:47:05.547 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14737 21:47:05.547 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 14738 21:47:05.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14739 21:47:05.547 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14740 21:47:05.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14741 21:47:05.547 0.00040099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14742 21:47:05.547 0.00034015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14743 21:47:05.547 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14744 21:47:05.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14745 21:47:05.547 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14746 21:47:05.547 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14747 21:47:05.547 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14748 21:47:05.547 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14749 21:47:05.547 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14750 21:47:05.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14751 21:47:05.547 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14752 21:47:05.547 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14753 21:47:05.547 0.00032553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14754 21:47:05.547 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14755 21:47:05.547 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14756 21:47:05.547 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14757 21:47:05.547 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14758 21:47:05.547 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14759 21:47:05.547 0.00022519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14760 21:47:05.547 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14761 21:47:05.547 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14762 21:47:05.547 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14763 21:47:05.547 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14764 21:47:05.547 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14765 21:47:05.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14766 21:47:05.547 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14767 21:47:05.547 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14768 21:47:05.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14769 21:47:05.547 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14770 21:47:05.547 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14771 21:47:05.547 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14772 21:47:05.547 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14773 21:47:05.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14774 21:47:05.547 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14775 21:47:05.547 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14776 21:47:05.547 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14777 21:47:05.547 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14778 21:47:05.547 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14779 21:47:05.547 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14780 21:47:05.547 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14781 21:47:05.547 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14782 21:47:05.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14783 21:47:05.547 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14784 21:47:05.547 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14785 21:47:05.547 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14786 21:47:05.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14787 21:47:05.547 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14788 21:47:05.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14789 21:47:05.547 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14790 21:47:05.547 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14791 21:47:05.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14792 21:47:05.547 0.02602549 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14793 21:47:05.578 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14794 21:47:05.578 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14795 21:47:05.578 0.01377462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14796 21:47:05.594 0.00030854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14797 21:47:05.594 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14798 21:47:05.594 0.00048000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14799 21:47:05.594 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14800 21:47:05.594 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14801 21:47:05.594 0.00030775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14802 21:47:05.594 0.00024138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14803 21:47:05.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14804 21:47:05.594 0.00053254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14805 21:47:05.594 0.00047249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 14806 21:47:05.594 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14807 21:47:05.594 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14808 21:47:05.594 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14809 21:47:05.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14810 21:47:05.594 0.00024573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14811 21:47:05.594 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14812 21:47:05.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14813 21:47:05.594 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14814 21:47:05.594 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14815 21:47:05.594 0.00029985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14816 21:47:05.594 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14817 21:47:05.594 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14818 21:47:05.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14819 21:47:05.594 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14820 21:47:05.594 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14821 21:47:05.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14822 21:47:05.594 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14823 21:47:05.594 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14824 21:47:05.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14825 21:47:05.594 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14826 21:47:05.594 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14827 21:47:05.594 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14828 21:47:05.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14829 21:47:05.594 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14830 21:47:05.594 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14831 21:47:05.594 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14832 21:47:05.594 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14833 21:47:05.594 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14834 21:47:05.594 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14835 21:47:05.594 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14836 21:47:05.594 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14837 21:47:05.594 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14838 21:47:05.594 0.00023269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14839 21:47:05.594 0.00030104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14840 21:47:05.594 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14841 21:47:05.594 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14842 21:47:05.594 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14843 21:47:05.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14844 21:47:05.594 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14845 21:47:05.594 0.00008099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14846 21:47:05.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14847 21:47:05.594 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14848 21:47:05.594 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14849 21:47:05.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14850 21:47:05.594 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14851 21:47:05.594 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14852 21:47:05.594 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14853 21:47:05.594 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14854 21:47:05.594 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14855 21:47:05.594 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14856 21:47:05.594 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14857 21:47:05.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14858 21:47:05.594 0.02645334 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14859 21:47:05.625 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14860 21:47:05.625 0.01362055 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14861 21:47:05.625 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14862 21:47:05.641 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14863 21:47:05.641 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14864 21:47:05.641 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14865 21:47:05.641 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14866 21:47:05.641 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14867 21:47:05.641 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14868 21:47:05.641 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14869 21:47:05.641 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 14870 21:47:05.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14871 21:47:05.641 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14872 21:47:05.641 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14873 21:47:05.641 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14874 21:47:05.641 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 14875 21:47:05.641 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14876 21:47:05.641 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14877 21:47:05.641 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14878 21:47:05.641 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14879 21:47:05.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14880 21:47:05.641 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14881 21:47:05.641 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14882 21:47:05.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14883 21:47:05.641 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14884 21:47:05.641 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14885 21:47:05.641 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14886 21:47:05.641 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14887 21:47:05.641 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14888 21:47:05.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14889 21:47:05.641 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14890 21:47:05.641 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14891 21:47:05.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14892 21:47:05.641 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14893 21:47:05.641 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14894 21:47:05.641 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14895 21:47:05.641 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14896 21:47:05.641 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14897 21:47:05.641 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14898 21:47:05.641 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14899 21:47:05.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14900 21:47:05.641 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14901 21:47:05.641 0.00028879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14902 21:47:05.641 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14903 21:47:05.641 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14904 21:47:05.641 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14905 21:47:05.641 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14906 21:47:05.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14907 21:47:05.641 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14908 21:47:05.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14909 21:47:05.641 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14910 21:47:05.641 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14911 21:47:05.641 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14912 21:47:05.641 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14913 21:47:05.641 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14914 21:47:05.641 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14915 21:47:05.641 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14916 21:47:05.641 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14917 21:47:05.641 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 14918 21:47:05.641 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14919 21:47:05.641 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14920 21:47:05.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14921 21:47:05.641 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14922 21:47:05.641 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14923 21:47:05.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14924 21:47:05.641 0.02713008 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14925 21:47:05.672 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14926 21:47:05.672 0.01311131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14927 21:47:05.672 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14928 21:47:05.688 0.00027694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14929 21:47:05.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14930 21:47:05.688 0.00029709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14931 21:47:05.688 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14932 21:47:05.688 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 14933 21:47:05.688 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14934 21:47:05.688 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14935 21:47:05.688 0.00039348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 14936 21:47:05.688 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14937 21:47:05.688 0.00046025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14939 21:47:05.688 0.00029077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14940 21:47:05.688 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14941 21:47:05.688 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14942 21:47:05.688 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14943 21:47:05.688 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14944 21:47:05.688 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14945 21:47:05.688 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14946 21:47:05.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14947 21:47:05.688 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14948 21:47:05.688 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14949 21:47:05.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14950 21:47:05.688 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14951 21:47:05.688 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14952 21:47:05.688 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14953 21:47:05.688 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14954 21:47:05.688 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14955 21:47:05.688 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14956 21:47:05.688 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14957 21:47:05.688 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14958 21:47:05.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14959 21:47:05.688 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14960 21:47:05.688 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14961 21:47:05.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14962 21:47:05.688 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14963 21:47:05.688 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14964 21:47:05.688 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14965 21:47:05.688 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14966 21:47:05.688 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14967 21:47:05.688 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14968 21:47:05.688 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14969 21:47:05.688 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14970 21:47:05.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14971 21:47:05.688 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14972 21:47:05.688 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14973 21:47:05.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14974 21:47:05.688 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14975 21:47:05.688 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14976 21:47:05.688 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14977 21:47:05.688 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14978 21:47:05.688 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14979 21:47:05.688 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14980 21:47:05.688 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14981 21:47:05.688 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14982 21:47:05.688 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14983 21:47:05.688 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14984 21:47:05.688 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 14985 21:47:05.688 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14986 21:47:05.688 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14987 21:47:05.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14988 21:47:05.688 0.02730470 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14989 21:47:05.719 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14990 21:47:05.719 0.01421077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14991 21:47:05.719 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 14992 21:47:05.735 0.00038400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 14993 21:47:05.735 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14994 21:47:05.735 0.00030815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14995 21:47:05.735 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 14996 21:47:05.735 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 14997 21:47:05.735 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 14998 21:47:05.735 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 14999 21:47:05.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15000 21:47:05.735 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15001 21:47:05.735 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 15002 21:47:05.735 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15003 21:47:05.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15004 21:47:05.735 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15005 21:47:05.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15006 21:47:05.735 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15007 21:47:05.735 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15008 21:47:05.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15009 21:47:05.735 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15010 21:47:05.735 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15011 21:47:05.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15012 21:47:05.735 0.00034686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15013 21:47:05.735 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15014 21:47:05.735 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15015 21:47:05.735 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15016 21:47:05.735 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15017 21:47:05.735 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15018 21:47:05.735 0.00032948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15019 21:47:05.735 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15020 21:47:05.735 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15021 21:47:05.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15022 21:47:05.735 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15023 21:47:05.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15024 21:47:05.735 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15025 21:47:05.735 0.00027733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15026 21:47:05.735 0.00026272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15027 21:47:05.735 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15028 21:47:05.735 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15029 21:47:05.735 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15030 21:47:05.735 0.00029077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15031 21:47:05.735 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15032 21:47:05.735 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 15033 21:47:05.735 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15034 21:47:05.735 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 15038 21:47:05.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15039 21:47:05.735 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15040 21:47:05.735 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15041 21:47:05.735 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15042 21:47:05.735 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15043 21:47:05.735 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15044 21:47:05.735 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15045 21:47:05.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15046 21:47:05.735 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15047 21:47:05.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15048 21:47:05.735 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15049 21:47:05.735 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15050 21:47:05.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15051 21:47:05.735 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15052 21:47:05.735 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15053 21:47:05.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15054 21:47:05.735 0.02565097 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15055 21:47:05.766 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15056 21:47:05.766 0.01265778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15057 21:47:05.766 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15058 21:47:05.781 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15059 21:47:05.781 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15060 21:47:05.781 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15061 21:47:05.781 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15062 21:47:05.781 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15063 21:47:05.781 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15064 21:47:05.781 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15065 21:47:05.781 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15066 21:47:05.781 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 15067 21:47:05.781 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15068 21:47:05.781 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15069 21:47:05.781 0.00028049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15070 21:47:05.781 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15071 21:47:05.781 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15072 21:47:05.781 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15073 21:47:05.781 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15074 21:47:05.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15075 21:47:05.781 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15076 21:47:05.781 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15077 21:47:05.781 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15078 21:47:05.781 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15079 21:47:05.781 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15080 21:47:05.781 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15081 21:47:05.781 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15082 21:47:05.781 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15083 21:47:05.781 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15084 21:47:05.781 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15085 21:47:05.781 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15086 21:47:05.781 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15087 21:47:05.781 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15088 21:47:05.781 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15089 21:47:05.781 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15090 21:47:05.781 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15091 21:47:05.781 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15092 21:47:05.781 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15093 21:47:05.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15094 21:47:05.781 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15095 21:47:05.781 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15096 21:47:05.781 0.00027931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15097 21:47:05.781 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15098 21:47:05.781 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 15099 21:47:05.781 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15101 21:47:05.781 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15102 21:47:05.781 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15103 21:47:05.781 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15104 21:47:05.781 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15105 21:47:05.781 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15106 21:47:05.781 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15107 21:47:05.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15108 21:47:05.781 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15109 21:47:05.781 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15110 21:47:05.781 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15111 21:47:05.781 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15112 21:47:05.781 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15113 21:47:05.781 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15114 21:47:05.781 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15115 21:47:05.781 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15116 21:47:05.781 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15117 21:47:05.781 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15118 21:47:05.781 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15119 21:47:05.781 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15120 21:47:05.781 0.02787675 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15121 21:47:05.813 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15122 21:47:05.813 0.01338391 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15123 21:47:05.813 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15124 21:47:05.828 0.00028405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15125 21:47:05.828 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15126 21:47:05.828 0.00034449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15127 21:47:05.828 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15128 21:47:05.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15129 21:47:05.828 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15130 21:47:05.828 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15131 21:47:05.828 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15132 21:47:05.828 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15133 21:47:05.828 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15134 21:47:05.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15135 21:47:05.828 0.00034765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15136 21:47:05.828 0.00033067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15137 21:47:05.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15138 21:47:05.828 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15139 21:47:05.828 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15140 21:47:05.828 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15141 21:47:05.828 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15142 21:47:05.828 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15143 21:47:05.828 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15144 21:47:05.828 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15145 21:47:05.828 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15146 21:47:05.828 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15147 21:47:05.828 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15148 21:47:05.828 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15149 21:47:05.828 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15150 21:47:05.828 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15151 21:47:05.828 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15152 21:47:05.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15153 21:47:05.828 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15154 21:47:05.828 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15155 21:47:05.828 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15156 21:47:05.828 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15157 21:47:05.828 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15158 21:47:05.828 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15159 21:47:05.828 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15160 21:47:05.828 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15161 21:47:05.828 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15162 21:47:05.828 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15163 21:47:05.828 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15164 21:47:05.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15165 21:47:05.828 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15166 21:47:05.828 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15167 21:47:05.828 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15168 21:47:05.828 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15169 21:47:05.828 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15170 21:47:05.828 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15171 21:47:05.828 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15172 21:47:05.828 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15173 21:47:05.828 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15174 21:47:05.828 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15175 21:47:05.828 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15176 21:47:05.828 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15177 21:47:05.828 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15178 21:47:05.828 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15179 21:47:05.828 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15180 21:47:05.828 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15181 21:47:05.828 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15182 21:47:05.828 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15183 21:47:05.828 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15184 21:47:05.828 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15185 21:47:05.828 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15186 21:47:05.828 0.02685986 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15187 21:47:05.859 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15188 21:47:05.859 0.01422341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15189 21:47:05.859 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15190 21:47:05.875 0.00030775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15191 21:47:05.875 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15192 21:47:05.875 0.00036701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15193 21:47:05.875 0.00031131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15194 21:47:05.875 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15195 21:47:05.875 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15196 21:47:05.875 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15197 21:47:05.875 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15198 21:47:05.875 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15199 21:47:05.875 0.00029195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15200 21:47:05.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15201 21:47:05.875 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15202 21:47:05.875 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15203 21:47:05.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15204 21:47:05.875 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15205 21:47:05.875 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15206 21:47:05.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15207 21:47:05.875 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15208 21:47:05.875 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15209 21:47:05.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15210 21:47:05.875 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15211 21:47:05.875 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15212 21:47:05.875 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15213 21:47:05.875 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15214 21:47:05.875 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15215 21:47:05.875 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15216 21:47:05.875 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15217 21:47:05.875 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15218 21:47:05.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15219 21:47:05.875 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15220 21:47:05.875 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15221 21:47:05.875 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15222 21:47:05.875 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15223 21:47:05.875 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15224 21:47:05.875 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15225 21:47:05.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15226 21:47:05.875 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15227 21:47:05.875 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15228 21:47:05.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15229 21:47:05.875 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15230 21:47:05.875 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15231 21:47:05.875 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15232 21:47:05.875 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15233 21:47:05.875 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15234 21:47:05.875 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15235 21:47:05.875 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15236 21:47:05.875 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15237 21:47:05.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15238 21:47:05.875 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15239 21:47:05.875 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15240 21:47:05.875 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15241 21:47:05.875 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15242 21:47:05.875 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15243 21:47:05.875 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15244 21:47:05.875 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15245 21:47:05.875 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15246 21:47:05.875 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15247 21:47:05.875 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15248 21:47:05.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15249 21:47:05.875 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15250 21:47:05.875 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15251 21:47:05.875 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15252 21:47:05.875 0.02802490 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15253 21:47:05.906 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15254 21:47:05.906 0.01312672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15255 21:47:05.906 0.00001936 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15256 21:47:05.922 0.00034370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15257 21:47:05.922 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15258 21:47:05.922 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15259 21:47:05.922 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15260 21:47:05.922 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15261 21:47:05.922 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15262 21:47:05.922 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15263 21:47:05.922 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 15264 21:47:05.922 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15265 21:47:05.922 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15266 21:47:05.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15267 21:47:05.922 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15268 21:47:05.922 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15269 21:47:05.922 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15270 21:47:05.922 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15271 21:47:05.922 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15272 21:47:05.922 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15273 21:47:05.922 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15274 21:47:05.922 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15275 21:47:05.922 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15276 21:47:05.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15277 21:47:05.922 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15278 21:47:05.922 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15279 21:47:05.922 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15280 21:47:05.922 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15281 21:47:05.922 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15282 21:47:05.922 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15283 21:47:05.922 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15284 21:47:05.922 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15285 21:47:05.922 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15286 21:47:05.922 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15287 21:47:05.922 0.00007941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15288 21:47:05.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15289 21:47:05.922 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15290 21:47:05.922 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15291 21:47:05.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15292 21:47:05.922 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15293 21:47:05.922 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15294 21:47:05.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15295 21:47:05.922 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15296 21:47:05.922 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15297 21:47:05.922 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15298 21:47:05.922 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15299 21:47:05.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15300 21:47:05.922 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15301 21:47:05.922 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15302 21:47:05.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15303 21:47:05.922 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15304 21:47:05.922 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15305 21:47:05.922 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15306 21:47:05.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15307 21:47:05.922 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15308 21:47:05.922 0.00007704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15309 21:47:05.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15310 21:47:05.922 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15311 21:47:05.922 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15312 21:47:05.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15313 21:47:05.922 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15314 21:47:05.922 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15315 21:47:05.922 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15316 21:47:05.922 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15317 21:47:05.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15318 21:47:05.922 0.02925591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15319 21:47:05.953 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15320 21:47:05.953 0.01323576 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15321 21:47:05.953 0.00001620 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15322 21:47:05.969 0.00031644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15323 21:47:05.969 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15324 21:47:05.969 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15325 21:47:05.969 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15326 21:47:05.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15327 21:47:05.969 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15328 21:47:05.969 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15329 21:47:05.969 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15330 21:47:05.969 0.00023546 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 15331 21:47:05.969 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15332 21:47:05.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15333 21:47:05.969 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15334 21:47:05.969 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15335 21:47:05.969 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15336 21:47:05.969 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15337 21:47:05.969 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15338 21:47:05.969 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15339 21:47:05.969 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15340 21:47:05.969 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15341 21:47:05.969 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15342 21:47:05.969 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15343 21:47:05.969 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15344 21:47:05.969 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15345 21:47:05.969 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15346 21:47:05.969 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15347 21:47:05.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15348 21:47:05.969 0.00037965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15349 21:47:05.969 0.00029432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15350 21:47:05.969 0.00031368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15351 21:47:05.969 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15352 21:47:05.969 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15353 21:47:05.969 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15354 21:47:05.969 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15355 21:47:05.969 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15356 21:47:05.969 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15357 21:47:05.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15358 21:47:05.969 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15359 21:47:05.969 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15360 21:47:05.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15361 21:47:05.969 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15362 21:47:05.969 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15363 21:47:05.969 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15364 21:47:05.969 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15365 21:47:05.969 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15366 21:47:05.969 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15367 21:47:05.969 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15368 21:47:05.969 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15369 21:47:05.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15370 21:47:05.969 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15371 21:47:05.969 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15372 21:47:05.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15373 21:47:05.969 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15374 21:47:05.969 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15375 21:47:05.969 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15376 21:47:05.969 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15377 21:47:05.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15378 21:47:05.969 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15379 21:47:05.969 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15380 21:47:05.969 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15381 21:47:05.969 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15382 21:47:05.969 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15383 21:47:05.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15384 21:47:05.969 0.02652999 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15385 21:47:06.000 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15386 21:47:06.000 0.01391447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15387 21:47:06.000 0.00003556 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15388 21:47:06.016 0.00031328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15389 21:47:06.016 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15390 21:47:06.016 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15391 21:47:06.016 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15392 21:47:06.016 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15393 21:47:06.016 0.00057600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15394 21:47:06.016 0.00043457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15395 21:47:06.016 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 15396 21:47:06.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15397 21:47:06.016 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15398 21:47:06.016 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15399 21:47:06.016 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15400 21:47:06.016 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15401 21:47:06.016 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15402 21:47:06.016 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15403 21:47:06.016 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15404 21:47:06.016 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15405 21:47:06.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15406 21:47:06.016 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15407 21:47:06.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15408 21:47:06.016 0.00028681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15409 21:47:06.016 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15410 21:47:06.016 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15411 21:47:06.016 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15412 21:47:06.016 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15413 21:47:06.016 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15414 21:47:06.016 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15415 21:47:06.016 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15416 21:47:06.016 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15417 21:47:06.016 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15418 21:47:06.016 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15419 21:47:06.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15420 21:47:06.016 0.00034489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15421 21:47:06.016 0.00034212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15422 21:47:06.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15423 21:47:06.016 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15424 21:47:06.016 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15425 21:47:06.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15426 21:47:06.016 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15427 21:47:06.016 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15428 21:47:06.016 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15429 21:47:06.016 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15430 21:47:06.016 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15431 21:47:06.016 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15432 21:47:06.016 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15433 21:47:06.016 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15434 21:47:06.016 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15435 21:47:06.016 0.00030499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15436 21:47:06.016 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15437 21:47:06.016 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15438 21:47:06.016 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15439 21:47:06.016 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15440 21:47:06.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15441 21:47:06.016 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15442 21:47:06.016 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15443 21:47:06.016 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15444 21:47:06.016 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15445 21:47:06.016 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15446 21:47:06.016 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15447 21:47:06.016 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15448 21:47:06.016 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15449 21:47:06.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15450 21:47:06.016 0.02424653 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15451 21:47:06.047 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15452 21:47:06.047 0.01397926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15453 21:47:06.047 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15454 21:47:06.063 0.00047526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15455 21:47:06.063 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15456 21:47:06.063 0.00035674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15457 21:47:06.063 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15458 21:47:06.063 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15459 21:47:06.063 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15460 21:47:06.063 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15461 21:47:06.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15462 21:47:06.063 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15463 21:47:06.063 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 15464 21:47:06.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15467 21:47:06.063 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15468 21:47:06.063 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15469 21:47:06.063 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15470 21:47:06.063 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15471 21:47:06.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15472 21:47:06.063 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15473 21:47:06.063 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15474 21:47:06.063 0.00037649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15475 21:47:06.063 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15476 21:47:06.063 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15477 21:47:06.063 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15478 21:47:06.063 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15479 21:47:06.063 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15480 21:47:06.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15481 21:47:06.063 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15482 21:47:06.063 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15483 21:47:06.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15484 21:47:06.063 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15485 21:47:06.063 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15486 21:47:06.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15487 21:47:06.063 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15488 21:47:06.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15489 21:47:06.063 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15490 21:47:06.063 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15491 21:47:06.063 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15492 21:47:06.063 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15493 21:47:06.063 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15494 21:47:06.063 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15495 21:47:06.063 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15496 21:47:06.063 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15497 21:47:06.063 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15498 21:47:06.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15499 21:47:06.063 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15500 21:47:06.063 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15501 21:47:06.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15502 21:47:06.063 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15503 21:47:06.063 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15504 21:47:06.063 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15505 21:47:06.063 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15506 21:47:06.063 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15507 21:47:06.063 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15508 21:47:06.063 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15509 21:47:06.063 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15510 21:47:06.063 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15511 21:47:06.063 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15512 21:47:06.063 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15513 21:47:06.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15514 21:47:06.063 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15515 21:47:06.063 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15516 21:47:06.063 0.02657621 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15517 21:47:06.094 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15518 21:47:06.094 0.01330055 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15519 21:47:06.094 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15520 21:47:06.109 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15521 21:47:06.109 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15522 21:47:06.109 0.00030183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15523 21:47:06.109 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15524 21:47:06.109 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15525 21:47:06.109 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15526 21:47:06.109 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15527 21:47:06.109 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 15528 21:47:06.109 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15529 21:47:06.109 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15530 21:47:06.109 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15531 21:47:06.109 0.00031565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15532 21:47:06.109 0.00033778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15533 21:47:06.109 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15534 21:47:06.109 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15535 21:47:06.109 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15536 21:47:06.109 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15537 21:47:06.109 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15538 21:47:06.109 0.00024138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15539 21:47:06.109 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15540 21:47:06.109 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15541 21:47:06.109 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15542 21:47:06.109 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15543 21:47:06.109 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15544 21:47:06.109 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15545 21:47:06.109 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15546 21:47:06.109 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15547 21:47:06.109 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15548 21:47:06.109 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15549 21:47:06.109 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15550 21:47:06.109 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15551 21:47:06.109 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15552 21:47:06.109 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15553 21:47:06.109 0.00028365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15554 21:47:06.109 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15555 21:47:06.109 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15556 21:47:06.109 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15557 21:47:06.109 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15558 21:47:06.109 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15559 21:47:06.109 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15560 21:47:06.109 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15561 21:47:06.109 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15562 21:47:06.109 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15563 21:47:06.109 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15564 21:47:06.109 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15565 21:47:06.109 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15566 21:47:06.109 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15567 21:47:06.109 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15568 21:47:06.109 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15569 21:47:06.109 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15570 21:47:06.109 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15571 21:47:06.109 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15572 21:47:06.109 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15573 21:47:06.109 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15574 21:47:06.109 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15575 21:47:06.109 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15576 21:47:06.109 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15577 21:47:06.109 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15578 21:47:06.109 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15579 21:47:06.109 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15580 21:47:06.109 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15581 21:47:06.109 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15582 21:47:06.109 0.02596544 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15583 21:47:06.141 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15584 21:47:06.141 0.01384692 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15585 21:47:06.141 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15586 21:47:06.156 0.00031881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15587 21:47:06.156 0.00027931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15588 21:47:06.156 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15589 21:47:06.156 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15590 21:47:06.156 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15591 21:47:06.156 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15592 21:47:06.156 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15593 21:47:06.156 0.00035279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 15594 21:47:06.156 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15595 21:47:06.156 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15596 21:47:06.156 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15597 21:47:06.156 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15598 21:47:06.156 0.00023348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15599 21:47:06.156 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15600 21:47:06.156 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15601 21:47:06.156 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15602 21:47:06.156 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15603 21:47:06.156 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15604 21:47:06.156 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15605 21:47:06.156 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15606 21:47:06.156 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15607 21:47:06.156 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15608 21:47:06.156 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15609 21:47:06.156 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15610 21:47:06.156 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15611 21:47:06.156 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15612 21:47:06.156 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15613 21:47:06.156 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15614 21:47:06.156 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15615 21:47:06.156 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15616 21:47:06.156 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15617 21:47:06.156 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15618 21:47:06.156 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15619 21:47:06.156 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15620 21:47:06.156 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15621 21:47:06.156 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15622 21:47:06.156 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15623 21:47:06.156 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15624 21:47:06.156 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15625 21:47:06.156 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15626 21:47:06.156 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15627 21:47:06.156 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15628 21:47:06.156 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15629 21:47:06.156 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15630 21:47:06.156 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15631 21:47:06.156 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15632 21:47:06.156 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15633 21:47:06.156 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15634 21:47:06.156 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15635 21:47:06.156 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15636 21:47:06.156 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15637 21:47:06.156 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15638 21:47:06.156 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15639 21:47:06.156 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15640 21:47:06.156 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15641 21:47:06.156 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15642 21:47:06.156 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15643 21:47:06.156 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15644 21:47:06.156 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 15645 21:47:06.156 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15646 21:47:06.156 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 15648 21:47:06.156 0.02794233 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15649 21:47:06.187 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15650 21:47:06.187 0.01329936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15651 21:47:06.187 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15652 21:47:06.203 0.00035319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15653 21:47:06.203 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15654 21:47:06.203 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15655 21:47:06.203 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15656 21:47:06.203 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15657 21:47:06.203 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15658 21:47:06.203 0.00031684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15659 21:47:06.203 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15660 21:47:06.203 0.00029669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15661 21:47:06.203 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 15662 21:47:06.203 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15663 21:47:06.203 0.00027022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15664 21:47:06.203 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15666 21:47:06.203 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 15667 21:47:06.203 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 15670 21:47:06.203 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15671 21:47:06.203 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15672 21:47:06.203 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15673 21:47:06.203 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15674 21:47:06.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15675 21:47:06.203 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15676 21:47:06.203 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15677 21:47:06.203 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15678 21:47:06.203 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15679 21:47:06.203 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15680 21:47:06.203 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15681 21:47:06.203 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15682 21:47:06.203 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15683 21:47:06.203 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15684 21:47:06.203 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15685 21:47:06.203 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15686 21:47:06.203 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15687 21:47:06.203 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15688 21:47:06.203 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15689 21:47:06.203 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15690 21:47:06.203 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15691 21:47:06.203 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15692 21:47:06.203 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15693 21:47:06.203 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15694 21:47:06.203 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15695 21:47:06.203 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15696 21:47:06.203 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15697 21:47:06.203 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15698 21:47:06.203 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15699 21:47:06.203 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15700 21:47:06.203 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15701 21:47:06.203 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15702 21:47:06.203 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15703 21:47:06.203 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15704 21:47:06.203 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15705 21:47:06.203 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15706 21:47:06.203 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15707 21:47:06.203 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15708 21:47:06.203 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15709 21:47:06.203 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15710 21:47:06.203 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15712 21:47:06.203 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15713 21:47:06.203 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15714 21:47:06.203 0.02663744 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15715 21:47:06.234 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15716 21:47:06.234 0.01420643 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15717 21:47:06.234 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15718 21:47:06.250 0.00032553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15719 21:47:06.250 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15720 21:47:06.250 0.00042035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15721 21:47:06.250 0.00032316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15722 21:47:06.250 0.00026983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15723 21:47:06.250 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15724 21:47:06.250 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15725 21:47:06.250 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 15726 21:47:06.250 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15727 21:47:06.250 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15728 21:47:06.250 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15729 21:47:06.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15730 21:47:06.250 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15731 21:47:06.250 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15732 21:47:06.250 0.00028919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15733 21:47:06.250 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15734 21:47:06.250 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15735 21:47:06.250 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15736 21:47:06.250 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15737 21:47:06.250 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15738 21:47:06.250 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15739 21:47:06.250 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15740 21:47:06.250 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15741 21:47:06.250 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15742 21:47:06.250 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15743 21:47:06.250 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15744 21:47:06.250 0.00025521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15746 21:47:06.250 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15747 21:47:06.250 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15748 21:47:06.250 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15749 21:47:06.250 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15750 21:47:06.250 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15751 21:47:06.250 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15752 21:47:06.250 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15753 21:47:06.250 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15754 21:47:06.250 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15755 21:47:06.250 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15756 21:47:06.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15757 21:47:06.250 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15758 21:47:06.250 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15759 21:47:06.250 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15760 21:47:06.250 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15761 21:47:06.250 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15762 21:47:06.250 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15763 21:47:06.250 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15764 21:47:06.250 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15765 21:47:06.250 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15766 21:47:06.250 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15767 21:47:06.250 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15768 21:47:06.250 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15769 21:47:06.250 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15770 21:47:06.250 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15771 21:47:06.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15772 21:47:06.250 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15773 21:47:06.250 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15774 21:47:06.250 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15775 21:47:06.250 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15776 21:47:06.250 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15777 21:47:06.250 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15778 21:47:06.250 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15779 21:47:06.250 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15780 21:47:06.250 0.02617206 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15781 21:47:06.282 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15782 21:47:06.282 0.01438025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15783 21:47:06.282 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15784 21:47:06.297 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15785 21:47:06.297 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15786 21:47:06.297 0.00028523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15787 21:47:06.297 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15788 21:47:06.297 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15789 21:47:06.297 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15790 21:47:06.297 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15791 21:47:06.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15792 21:47:06.297 0.00027338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15793 21:47:06.297 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 15794 21:47:06.297 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15795 21:47:06.297 0.00030183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15796 21:47:06.297 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15797 21:47:06.297 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15798 21:47:06.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15799 21:47:06.297 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15800 21:47:06.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15801 21:47:06.297 0.00031565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15802 21:47:06.297 0.00034568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15803 21:47:06.297 0.00026864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15804 21:47:06.297 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15805 21:47:06.297 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15806 21:47:06.297 0.00035279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15807 21:47:06.297 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15808 21:47:06.297 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15809 21:47:06.297 0.00049620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15810 21:47:06.297 0.00030262 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15811 21:47:06.297 0.00016869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15812 21:47:06.297 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15813 21:47:06.297 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15814 21:47:06.297 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15815 21:47:06.297 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15816 21:47:06.297 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15817 21:47:06.297 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15818 21:47:06.297 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15819 21:47:06.297 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15820 21:47:06.297 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15821 21:47:06.297 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15822 21:47:06.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15823 21:47:06.297 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15824 21:47:06.297 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15825 21:47:06.297 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15826 21:47:06.297 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15827 21:47:06.297 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15828 21:47:06.297 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15829 21:47:06.297 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15830 21:47:06.297 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15831 21:47:06.297 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15832 21:47:06.297 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15833 21:47:06.297 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15834 21:47:06.297 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15835 21:47:06.297 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15836 21:47:06.297 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15837 21:47:06.297 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15838 21:47:06.297 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15839 21:47:06.297 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15840 21:47:06.297 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15841 21:47:06.297 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15842 21:47:06.297 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15843 21:47:06.297 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15844 21:47:06.297 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15845 21:47:06.297 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15846 21:47:06.297 0.02625937 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15847 21:47:06.329 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15848 21:47:06.329 0.01357709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15849 21:47:06.329 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15850 21:47:06.344 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15851 21:47:06.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15852 21:47:06.344 0.00034094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15853 21:47:06.344 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15854 21:47:06.344 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15855 21:47:06.344 0.00029906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15856 21:47:06.344 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15857 21:47:06.344 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15858 21:47:06.344 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 15859 21:47:06.344 0.00026193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15860 21:47:06.344 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15861 21:47:06.344 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15862 21:47:06.344 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15863 21:47:06.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15864 21:47:06.344 0.00047842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15865 21:47:06.344 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15866 21:47:06.344 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15867 21:47:06.344 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15868 21:47:06.344 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15869 21:47:06.344 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15870 21:47:06.344 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15871 21:47:06.344 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15872 21:47:06.344 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15873 21:47:06.344 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15874 21:47:06.344 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15875 21:47:06.344 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15876 21:47:06.344 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15877 21:47:06.344 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15878 21:47:06.344 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15879 21:47:06.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15880 21:47:06.344 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15881 21:47:06.344 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15882 21:47:06.344 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15883 21:47:06.344 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15884 21:47:06.344 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15885 21:47:06.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15886 21:47:06.344 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15887 21:47:06.344 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15888 21:47:06.344 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15889 21:47:06.344 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15890 21:47:06.344 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15891 21:47:06.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15892 21:47:06.344 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15893 21:47:06.344 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15894 21:47:06.344 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15895 21:47:06.344 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15896 21:47:06.344 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15897 21:47:06.344 0.00031961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15899 21:47:06.344 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15900 21:47:06.344 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15901 21:47:06.344 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15902 21:47:06.344 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15903 21:47:06.344 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15904 21:47:06.344 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15905 21:47:06.344 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15906 21:47:06.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15907 21:47:06.344 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15908 21:47:06.344 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15909 21:47:06.344 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15910 21:47:06.344 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15911 21:47:06.344 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15912 21:47:06.344 0.02779892 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15913 21:47:06.375 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15914 21:47:06.375 0.01178154 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15915 21:47:06.375 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15916 21:47:06.391 0.00031723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15917 21:47:06.391 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15918 21:47:06.391 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15919 21:47:06.391 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15920 21:47:06.391 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15921 21:47:06.391 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 15922 21:47:06.391 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15923 21:47:06.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15924 21:47:06.391 0.00046617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15925 21:47:06.391 0.00032751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 15926 21:47:06.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15927 21:47:06.391 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15928 21:47:06.391 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15929 21:47:06.391 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15930 21:47:06.391 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15931 21:47:06.391 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15932 21:47:06.391 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15933 21:47:06.391 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15934 21:47:06.391 0.00029116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15935 21:47:06.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15936 21:47:06.391 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15937 21:47:06.391 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15938 21:47:06.391 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15939 21:47:06.391 0.00128158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15940 21:47:06.391 0.00117175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15941 21:47:06.391 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15942 21:47:06.391 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15943 21:47:06.391 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15944 21:47:06.391 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15945 21:47:06.391 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15946 21:47:06.391 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15947 21:47:06.391 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15948 21:47:06.391 0.00033857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15949 21:47:06.391 0.00023664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15950 21:47:06.391 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15952 21:47:06.391 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15953 21:47:06.391 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15954 21:47:06.391 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15955 21:47:06.391 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15956 21:47:06.391 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15957 21:47:06.391 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15958 21:47:06.391 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15959 21:47:06.391 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15960 21:47:06.391 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15961 21:47:06.391 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15962 21:47:06.391 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 15963 21:47:06.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15964 21:47:06.391 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 15967 21:47:06.391 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15968 21:47:06.391 0.00008138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15969 21:47:06.391 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15970 21:47:06.391 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15971 21:47:06.391 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15972 21:47:06.391 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15973 21:47:06.391 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15974 21:47:06.391 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15975 21:47:06.391 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15976 21:47:06.391 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15977 21:47:06.391 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15978 21:47:06.391 0.02419240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15979 21:47:06.422 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15980 21:47:06.422 0.01466391 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15981 21:47:06.422 0.00000356 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 15982 21:47:06.438 0.00040415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 15983 21:47:06.438 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15984 21:47:06.438 0.00024573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15985 21:47:06.438 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 15986 21:47:06.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15987 21:47:06.438 0.00072494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15988 21:47:06.438 0.00034568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 15989 21:47:06.438 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15990 21:47:06.438 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 15991 21:47:06.438 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15992 21:47:06.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15993 21:47:06.438 0.00033738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15994 21:47:06.438 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 15995 21:47:06.438 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 15996 21:47:06.438 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15997 21:47:06.438 0.00015605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 15998 21:47:06.438 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 15999 21:47:06.438 0.00029946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16000 21:47:06.438 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16001 21:47:06.438 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16002 21:47:06.438 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16003 21:47:06.438 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16004 21:47:06.438 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16005 21:47:06.438 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16006 21:47:06.438 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16007 21:47:06.438 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16008 21:47:06.438 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16009 21:47:06.438 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16010 21:47:06.438 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16011 21:47:06.438 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16012 21:47:06.438 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16013 21:47:06.438 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16014 21:47:06.438 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16015 21:47:06.438 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16016 21:47:06.438 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16017 21:47:06.438 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16018 21:47:06.438 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16019 21:47:06.438 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16020 21:47:06.438 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16021 21:47:06.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16022 21:47:06.438 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16023 21:47:06.438 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16024 21:47:06.438 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16025 21:47:06.438 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16026 21:47:06.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16027 21:47:06.438 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16028 21:47:06.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16029 21:47:06.438 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16030 21:47:06.438 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16031 21:47:06.438 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16032 21:47:06.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16033 21:47:06.438 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16034 21:47:06.438 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16035 21:47:06.438 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16036 21:47:06.438 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16037 21:47:06.438 0.00008217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16038 21:47:06.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16039 21:47:06.438 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16040 21:47:06.438 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16041 21:47:06.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16042 21:47:06.438 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16043 21:47:06.438 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16044 21:47:06.438 0.02738332 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16045 21:47:06.469 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16046 21:47:06.469 0.01388287 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16047 21:47:06.469 0.00002094 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16048 21:47:06.485 0.00034370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16049 21:47:06.485 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16050 21:47:06.485 0.00096790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16051 21:47:06.485 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16052 21:47:06.485 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16053 21:47:06.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16054 21:47:06.485 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16055 21:47:06.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16056 21:47:06.485 0.00041956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16057 21:47:06.485 0.00028168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 16058 21:47:06.485 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16059 21:47:06.485 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16061 21:47:06.485 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16062 21:47:06.485 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16063 21:47:06.485 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16064 21:47:06.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16065 21:47:06.485 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16066 21:47:06.485 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16067 21:47:06.485 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16068 21:47:06.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16069 21:47:06.485 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16070 21:47:06.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16071 21:47:06.485 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16072 21:47:06.485 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16073 21:47:06.485 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16074 21:47:06.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16075 21:47:06.485 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16076 21:47:06.485 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16077 21:47:06.485 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16078 21:47:06.485 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16079 21:47:06.485 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16080 21:47:06.485 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16081 21:47:06.485 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16082 21:47:06.485 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16083 21:47:06.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16084 21:47:06.485 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16085 21:47:06.485 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16086 21:47:06.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16087 21:47:06.485 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16088 21:47:06.485 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16089 21:47:06.485 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16090 21:47:06.485 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16091 21:47:06.485 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16092 21:47:06.485 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16093 21:47:06.485 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16094 21:47:06.485 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16095 21:47:06.485 0.00026351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16096 21:47:06.485 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16097 21:47:06.485 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16098 21:47:06.485 0.00030538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16099 21:47:06.485 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16100 21:47:06.485 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16101 21:47:06.485 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16102 21:47:06.485 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16103 21:47:06.485 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16104 21:47:06.485 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16105 21:47:06.485 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16106 21:47:06.485 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16107 21:47:06.485 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16108 21:47:06.485 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16109 21:47:06.485 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16110 21:47:06.485 0.02740070 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16111 21:47:06.516 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16112 21:47:06.516 0.01269571 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16113 21:47:06.516 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16114 21:47:06.532 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16115 21:47:06.532 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16116 21:47:06.532 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16117 21:47:06.532 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16118 21:47:06.532 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16119 21:47:06.532 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16120 21:47:06.532 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16121 21:47:06.532 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 16122 21:47:06.532 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16123 21:47:06.532 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16124 21:47:06.532 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16125 21:47:06.532 0.00050133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16126 21:47:06.532 0.00038084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16127 21:47:06.532 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16128 21:47:06.532 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16129 21:47:06.532 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16130 21:47:06.532 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16131 21:47:06.532 0.00045985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16132 21:47:06.532 0.00036701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16133 21:47:06.532 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16134 21:47:06.532 0.00031486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16135 21:47:06.532 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16136 21:47:06.532 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16137 21:47:06.532 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16138 21:47:06.532 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16139 21:47:06.532 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16140 21:47:06.532 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16141 21:47:06.532 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16142 21:47:06.532 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16143 21:47:06.532 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16144 21:47:06.532 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16145 21:47:06.532 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16146 21:47:06.532 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16147 21:47:06.532 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16148 21:47:06.532 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16149 21:47:06.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16150 21:47:06.532 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16151 21:47:06.532 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16152 21:47:06.532 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16153 21:47:06.532 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16154 21:47:06.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16155 21:47:06.532 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16156 21:47:06.532 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16157 21:47:06.532 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16158 21:47:06.532 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16159 21:47:06.532 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16160 21:47:06.532 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16161 21:47:06.532 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16162 21:47:06.532 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16163 21:47:06.532 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16164 21:47:06.532 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16165 21:47:06.532 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16166 21:47:06.532 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16167 21:47:06.532 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16168 21:47:06.532 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16169 21:47:06.532 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16170 21:47:06.532 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16171 21:47:06.532 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16172 21:47:06.532 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16173 21:47:06.532 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16174 21:47:06.532 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16175 21:47:06.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16176 21:47:06.532 0.02597374 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16177 21:47:06.563 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16178 21:47:06.563 0.01461413 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16179 21:47:06.563 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16180 21:47:06.579 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16181 21:47:06.579 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16182 21:47:06.579 0.00027575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16183 21:47:06.579 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16184 21:47:06.579 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16185 21:47:06.579 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16186 21:47:06.579 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16187 21:47:06.579 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 16188 21:47:06.579 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16189 21:47:06.579 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16190 21:47:06.579 0.00015605 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16191 21:47:06.579 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16192 21:47:06.579 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16193 21:47:06.579 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16194 21:47:06.579 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 16195 21:47:06.579 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16196 21:47:06.579 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16197 21:47:06.579 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16198 21:47:06.579 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16199 21:47:06.579 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16200 21:47:06.579 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16201 21:47:06.579 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16202 21:47:06.579 0.00047565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16203 21:47:06.579 0.00037926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16204 21:47:06.579 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16205 21:47:06.579 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16206 21:47:06.579 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16207 21:47:06.579 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16208 21:47:06.579 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16209 21:47:06.579 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16210 21:47:06.579 0.00041284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16211 21:47:06.579 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16212 21:47:06.579 0.00035081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16213 21:47:06.579 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16214 21:47:06.579 0.00033264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16215 21:47:06.579 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16216 21:47:06.579 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16217 21:47:06.579 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16218 21:47:06.579 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16219 21:47:06.579 0.00026864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16220 21:47:06.579 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16221 21:47:06.579 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16222 21:47:06.579 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16223 21:47:06.579 0.00030617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16224 21:47:06.579 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16225 21:47:06.579 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16226 21:47:06.579 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16227 21:47:06.579 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16228 21:47:06.579 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16229 21:47:06.579 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16231 21:47:06.579 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16232 21:47:06.579 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16233 21:47:06.579 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16234 21:47:06.579 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16235 21:47:06.579 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16236 21:47:06.579 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16237 21:47:06.579 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16238 21:47:06.579 0.02596742 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16239 21:47:06.610 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16240 21:47:06.610 0.01373077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16241 21:47:06.610 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16242 21:47:06.625 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16243 21:47:06.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16244 21:47:06.625 0.00038874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16245 21:47:06.625 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16246 21:47:06.625 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16247 21:47:06.625 0.00041758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16248 21:47:06.625 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16249 21:47:06.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16250 21:47:06.625 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 16251 21:47:06.625 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16252 21:47:06.625 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16253 21:47:06.625 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16254 21:47:06.625 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16255 21:47:06.625 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16256 21:47:06.625 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16257 21:47:06.625 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16258 21:47:06.625 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16259 21:47:06.625 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16260 21:47:06.625 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16261 21:47:06.625 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16262 21:47:06.625 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16263 21:47:06.625 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16264 21:47:06.625 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16265 21:47:06.625 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16266 21:47:06.625 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16267 21:47:06.625 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16268 21:47:06.625 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16269 21:47:06.625 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16270 21:47:06.625 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16271 21:47:06.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16272 21:47:06.625 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16273 21:47:06.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16274 21:47:06.625 0.00320909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16275 21:47:06.625 0.00316603 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16276 21:47:06.625 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16277 21:47:06.625 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16278 21:47:06.625 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16279 21:47:06.625 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16280 21:47:06.625 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16281 21:47:06.625 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16282 21:47:06.625 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16283 21:47:06.625 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16284 21:47:06.625 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16285 21:47:06.625 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16286 21:47:06.625 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16287 21:47:06.625 0.00031486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16288 21:47:06.625 0.00026825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16289 21:47:06.625 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16290 21:47:06.625 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16291 21:47:06.625 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16292 21:47:06.625 0.00035240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16293 21:47:06.625 0.00030894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16294 21:47:06.625 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16295 21:47:06.625 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16296 21:47:06.625 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16297 21:47:06.625 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16298 21:47:06.625 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16299 21:47:06.625 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16302 21:47:06.625 0.00029432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16303 21:47:06.625 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16304 21:47:06.625 0.02381670 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16305 21:47:06.657 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16306 21:47:06.657 0.01290075 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16307 21:47:06.657 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16308 21:47:06.672 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16309 21:47:06.672 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16310 21:47:06.672 0.00136099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16311 21:47:06.672 0.00125314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16312 21:47:06.672 0.00049896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16313 21:47:06.672 0.00026351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16314 21:47:06.672 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16315 21:47:06.672 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 16316 21:47:06.672 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16317 21:47:06.672 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16318 21:47:06.672 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16319 21:47:06.672 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 16320 21:47:06.672 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 16324 21:47:06.672 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16325 21:47:06.672 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16326 21:47:06.672 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16327 21:47:06.672 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16328 21:47:06.672 0.00027654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16329 21:47:06.672 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16330 21:47:06.672 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16331 21:47:06.672 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16332 21:47:06.672 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16333 21:47:06.672 0.00032277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16334 21:47:06.672 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16335 21:47:06.672 0.00025047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16336 21:47:06.672 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16337 21:47:06.672 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16338 21:47:06.672 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16339 21:47:06.672 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16340 21:47:06.672 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16341 21:47:06.672 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16342 21:47:06.672 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16343 21:47:06.672 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16344 21:47:06.672 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16345 21:47:06.672 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16346 21:47:06.672 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16347 21:47:06.672 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16348 21:47:06.672 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16349 21:47:06.672 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16350 21:47:06.672 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16351 21:47:06.672 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16352 21:47:06.672 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16353 21:47:06.672 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16354 21:47:06.672 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16355 21:47:06.672 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16356 21:47:06.672 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16357 21:47:06.672 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16358 21:47:06.672 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16359 21:47:06.672 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16360 21:47:06.672 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16361 21:47:06.672 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16362 21:47:06.672 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16363 21:47:06.672 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16364 21:47:06.672 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16365 21:47:06.672 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16366 21:47:06.672 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16367 21:47:06.672 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16368 21:47:06.672 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16369 21:47:06.672 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16370 21:47:06.672 0.02635339 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16371 21:47:06.706 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16372 21:47:06.706 0.02836584 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16373 21:47:06.706 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16374 21:47:06.735 0.00032237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16375 21:47:06.735 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16376 21:47:06.735 0.00040178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16377 21:47:06.735 0.00033343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16378 21:47:06.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16379 21:47:06.735 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16380 21:47:06.735 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16381 21:47:06.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16382 21:47:06.735 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 16383 21:47:06.735 0.00024099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16384 21:47:06.735 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16385 21:47:06.735 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16386 21:47:06.735 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16387 21:47:06.735 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16388 21:47:06.735 0.00042548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16389 21:47:06.735 0.00039309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16390 21:47:06.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16391 21:47:06.735 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16392 21:47:06.735 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16393 21:47:06.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16394 21:47:06.735 0.00029551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16395 21:47:06.735 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16396 21:47:06.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16397 21:47:06.735 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16398 21:47:06.735 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16399 21:47:06.735 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16400 21:47:06.735 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16401 21:47:06.735 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16402 21:47:06.735 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16403 21:47:06.735 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16404 21:47:06.735 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16405 21:47:06.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16406 21:47:06.735 0.00031526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16407 21:47:06.735 0.00035832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16408 21:47:06.735 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16409 21:47:06.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16410 21:47:06.735 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16411 21:47:06.735 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16412 21:47:06.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16413 21:47:06.735 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16414 21:47:06.735 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16415 21:47:06.735 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16416 21:47:06.735 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16417 21:47:06.735 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16418 21:47:06.735 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16419 21:47:06.735 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16422 21:47:06.735 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16423 21:47:06.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16424 21:47:06.735 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16425 21:47:06.735 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16426 21:47:06.735 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16427 21:47:06.735 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16428 21:47:06.735 0.00008336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16429 21:47:06.735 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16430 21:47:06.735 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16431 21:47:06.735 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16432 21:47:06.735 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16433 21:47:06.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16434 21:47:06.735 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16435 21:47:06.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16436 21:47:06.735 0.02890352 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16437 21:47:06.766 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16438 21:47:06.766 0.01173808 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16439 21:47:06.766 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16440 21:47:06.781 0.00033896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16441 21:47:06.781 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16444 21:47:06.781 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16445 21:47:06.781 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16446 21:47:06.781 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16447 21:47:06.781 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 16448 21:47:06.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16449 21:47:06.781 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16450 21:47:06.781 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16451 21:47:06.781 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16452 21:47:06.781 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16453 21:47:06.781 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16454 21:47:06.781 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16455 21:47:06.781 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16456 21:47:06.781 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16457 21:47:06.781 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16458 21:47:06.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16459 21:47:06.781 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16460 21:47:06.781 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16461 21:47:06.781 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16462 21:47:06.781 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16463 21:47:06.781 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 16466 21:47:06.781 0.00024138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16467 21:47:06.781 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16468 21:47:06.781 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16469 21:47:06.781 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16470 21:47:06.781 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16471 21:47:06.781 0.00024770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16472 21:47:06.781 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16473 21:47:06.781 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16474 21:47:06.781 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16475 21:47:06.781 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16476 21:47:06.781 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16477 21:47:06.781 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16478 21:47:06.781 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16479 21:47:06.781 0.00027299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16480 21:47:06.781 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16481 21:47:06.781 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 16482 21:47:06.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16483 21:47:06.781 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16484 21:47:06.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16485 21:47:06.781 0.00025165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16486 21:47:06.781 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16487 21:47:06.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16488 21:47:06.781 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16489 21:47:06.781 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16490 21:47:06.781 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16491 21:47:06.781 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16492 21:47:06.781 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16493 21:47:06.781 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16494 21:47:06.781 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16495 21:47:06.781 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16496 21:47:06.781 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16497 21:47:06.781 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16498 21:47:06.781 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16499 21:47:06.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16500 21:47:06.781 0.02655764 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16501 21:47:06.813 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16502 21:47:06.813 0.01407566 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16503 21:47:06.813 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16504 21:47:06.829 0.00034963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16505 21:47:06.829 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16506 21:47:06.829 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16507 21:47:06.829 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16508 21:47:06.829 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16509 21:47:06.829 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16510 21:47:06.829 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16511 21:47:06.829 0.00028207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 16512 21:47:06.829 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16513 21:47:06.829 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16514 21:47:06.829 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16515 21:47:06.829 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16516 21:47:06.829 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16517 21:47:06.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16518 21:47:06.829 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16519 21:47:06.829 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16520 21:47:06.829 0.00033106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16521 21:47:06.829 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16522 21:47:06.829 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16523 21:47:06.829 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 16524 21:47:06.829 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16525 21:47:06.829 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 16528 21:47:06.829 0.00029709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16529 21:47:06.829 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16530 21:47:06.829 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16531 21:47:06.829 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16532 21:47:06.829 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16533 21:47:06.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16534 21:47:06.829 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16535 21:47:06.829 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16536 21:47:06.829 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16537 21:47:06.829 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16538 21:47:06.829 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16539 21:47:06.829 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16540 21:47:06.829 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16541 21:47:06.829 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16542 21:47:06.829 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16543 21:47:06.829 0.00022400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16544 21:47:06.829 0.00029827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16545 21:47:06.829 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16546 21:47:06.829 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16547 21:47:06.829 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16548 21:47:06.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16549 21:47:06.829 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16550 21:47:06.829 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16551 21:47:06.829 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16552 21:47:06.829 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16553 21:47:06.829 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16554 21:47:06.829 0.00038716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16555 21:47:06.829 0.00031289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16556 21:47:06.829 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16557 21:47:06.829 0.00028602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16559 21:47:06.829 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16560 21:47:06.829 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16561 21:47:06.829 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16562 21:47:06.829 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16563 21:47:06.829 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16564 21:47:06.829 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16565 21:47:06.829 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16566 21:47:06.829 0.02618470 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16567 21:47:06.860 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16568 21:47:06.860 0.01308959 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16569 21:47:06.860 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16570 21:47:06.875 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16571 21:47:06.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16572 21:47:06.875 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16573 21:47:06.875 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16574 21:47:06.875 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16575 21:47:06.875 0.00058983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16576 21:47:06.875 0.00048395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16577 21:47:06.875 0.00039072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 16578 21:47:06.875 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16579 21:47:06.875 0.00032672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16580 21:47:06.875 0.00040454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16581 21:47:06.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16582 21:47:06.875 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16583 21:47:06.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16584 21:47:06.875 0.00038716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16585 21:47:06.875 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16586 21:47:06.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16587 21:47:06.875 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16588 21:47:06.875 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16589 21:47:06.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16590 21:47:06.875 0.00045116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16591 21:47:06.875 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16592 21:47:06.875 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16593 21:47:06.875 0.00035319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16594 21:47:06.875 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16595 21:47:06.875 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16596 21:47:06.875 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16597 21:47:06.875 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16598 21:47:06.875 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16599 21:47:06.875 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16600 21:47:06.875 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16601 21:47:06.875 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16602 21:47:06.875 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16603 21:47:06.875 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16604 21:47:06.875 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16605 21:47:06.875 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16606 21:47:06.875 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16607 21:47:06.875 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16608 21:47:06.875 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16609 21:47:06.875 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16610 21:47:06.875 0.00031052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16611 21:47:06.875 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16612 21:47:06.875 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16613 21:47:06.875 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16614 21:47:06.875 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16615 21:47:06.875 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16616 21:47:06.875 0.00023585 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16617 21:47:06.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16618 21:47:06.875 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16619 21:47:06.875 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16620 21:47:06.875 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16621 21:47:06.875 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16622 21:47:06.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16623 21:47:06.875 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16624 21:47:06.875 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16625 21:47:06.875 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16626 21:47:06.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16627 21:47:06.875 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16628 21:47:06.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16629 21:47:06.875 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16630 21:47:06.875 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16631 21:47:06.875 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16632 21:47:06.875 0.02593384 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16633 21:47:06.907 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16634 21:47:06.907 0.01217581 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16635 21:47:06.907 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16636 21:47:06.922 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16637 21:47:06.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16638 21:47:06.922 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16639 21:47:06.922 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16640 21:47:06.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16641 21:47:06.922 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16642 21:47:06.922 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16643 21:47:06.922 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 16644 21:47:06.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16645 21:47:06.922 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16646 21:47:06.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16647 21:47:06.922 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16648 21:47:06.922 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16649 21:47:06.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16650 21:47:06.922 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16651 21:47:06.922 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16652 21:47:06.922 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16653 21:47:06.922 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16654 21:47:06.922 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16655 21:47:06.922 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16656 21:47:06.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16657 21:47:06.922 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16658 21:47:06.922 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16659 21:47:06.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16660 21:47:06.922 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16661 21:47:06.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16662 21:47:06.922 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16663 21:47:06.922 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16664 21:47:06.922 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16665 21:47:06.922 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16666 21:47:06.922 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16667 21:47:06.922 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16668 21:47:06.922 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16669 21:47:06.922 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16670 21:47:06.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16671 21:47:06.922 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16672 21:47:06.922 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16673 21:47:06.922 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16674 21:47:06.922 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16675 21:47:06.922 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16676 21:47:06.922 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16677 21:47:06.922 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16678 21:47:06.922 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16679 21:47:06.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16680 21:47:06.922 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16681 21:47:06.922 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16682 21:47:06.922 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16683 21:47:06.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16684 21:47:06.922 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16685 21:47:06.922 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16686 21:47:06.922 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16687 21:47:06.922 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16688 21:47:06.922 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16689 21:47:06.922 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16690 21:47:06.922 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16691 21:47:06.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16692 21:47:06.922 0.00021096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16693 21:47:06.922 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16694 21:47:06.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16695 21:47:06.922 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16696 21:47:06.922 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16697 21:47:06.922 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16698 21:47:06.922 0.02692189 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16699 21:47:06.954 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16700 21:47:06.954 0.01441936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16701 21:47:06.954 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16702 21:47:06.969 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16703 21:47:06.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16704 21:47:06.969 0.00028840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16705 21:47:06.969 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16706 21:47:06.969 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16707 21:47:06.969 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16708 21:47:06.969 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16709 21:47:06.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16710 21:47:06.969 0.00033580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16711 21:47:06.969 0.00029156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 16712 21:47:06.969 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 16713 21:47:06.969 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16714 21:47:06.969 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 16716 21:47:06.969 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16717 21:47:06.969 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16718 21:47:06.969 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16719 21:47:06.969 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16720 21:47:06.969 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16721 21:47:06.969 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16722 21:47:06.969 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16723 21:47:06.969 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16724 21:47:06.969 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16725 21:47:06.969 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16726 21:47:06.969 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16727 21:47:06.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16728 21:47:06.969 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16729 21:47:06.969 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16730 21:47:06.969 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16731 21:47:06.969 0.00033738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16732 21:47:06.969 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16733 21:47:06.969 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16734 21:47:06.969 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16735 21:47:06.969 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16736 21:47:06.969 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16737 21:47:06.969 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16738 21:47:06.969 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16739 21:47:06.969 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16740 21:47:06.969 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16741 21:47:06.969 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16742 21:47:06.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16743 21:47:06.969 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16744 21:47:06.969 0.00023901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16745 21:47:06.969 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16746 21:47:06.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16747 21:47:06.969 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16748 21:47:06.969 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16749 21:47:06.969 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16750 21:47:06.969 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16751 21:47:06.969 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16752 21:47:06.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16753 21:47:06.969 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16754 21:47:06.969 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16755 21:47:06.969 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16756 21:47:06.969 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16757 21:47:06.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16758 21:47:06.969 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16759 21:47:06.969 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16760 21:47:06.969 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16761 21:47:06.969 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16762 21:47:06.969 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16763 21:47:06.969 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16764 21:47:06.969 0.02697562 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16765 21:47:07.000 0.00001699 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16766 21:47:07.000 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16768 21:47:07.016 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16769 21:47:07.016 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16770 21:47:07.016 0.00044998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16771 21:47:07.016 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16772 21:47:07.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16773 21:47:07.016 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16774 21:47:07.016 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16775 21:47:07.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16776 21:47:07.016 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16777 21:47:07.016 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 16778 21:47:07.016 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16779 21:47:07.016 0.00048040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16780 21:47:07.016 0.00041877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16781 21:47:07.016 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16782 21:47:07.016 0.00044681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16783 21:47:07.016 0.00033501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16784 21:47:07.016 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16785 21:47:07.016 0.00042193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16786 21:47:07.016 0.00034647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16787 21:47:07.016 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16788 21:47:07.016 0.00038321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16789 21:47:07.016 0.00033264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16790 21:47:07.016 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16791 21:47:07.016 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16792 21:47:07.016 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16793 21:47:07.016 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16794 21:47:07.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16795 21:47:07.016 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16796 21:47:07.016 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16797 21:47:07.016 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16798 21:47:07.016 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16799 21:47:07.016 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 16800 21:47:07.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16801 21:47:07.016 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 16804 21:47:07.016 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16805 21:47:07.016 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16806 21:47:07.016 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16807 21:47:07.016 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16808 21:47:07.016 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16809 21:47:07.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16810 21:47:07.016 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16811 21:47:07.016 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16812 21:47:07.016 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16813 21:47:07.016 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16814 21:47:07.016 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16815 21:47:07.016 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16816 21:47:07.016 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16817 21:47:07.016 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16818 21:47:07.016 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16819 21:47:07.016 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16820 21:47:07.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16821 21:47:07.016 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16822 21:47:07.016 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16823 21:47:07.016 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16824 21:47:07.016 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16825 21:47:07.016 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16826 21:47:07.016 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16827 21:47:07.016 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16828 21:47:07.016 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16829 21:47:07.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16830 21:47:07.016 0.02804663 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16831 21:47:07.047 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16832 21:47:07.047 0.01162904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16833 21:47:07.047 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16834 21:47:07.063 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16835 21:47:07.063 0.00024138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16836 21:47:07.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16837 21:47:07.063 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16838 21:47:07.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16839 21:47:07.063 0.00031407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16840 21:47:07.063 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16841 21:47:07.063 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16842 21:47:07.063 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 16843 21:47:07.063 0.00028998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16844 21:47:07.063 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16845 21:47:07.063 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16846 21:47:07.063 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16847 21:47:07.063 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16848 21:47:07.063 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16849 21:47:07.063 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16850 21:47:07.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16851 21:47:07.063 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16852 21:47:07.063 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16853 21:47:07.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16854 21:47:07.063 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16855 21:47:07.063 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16856 21:47:07.063 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16857 21:47:07.063 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16858 21:47:07.063 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16859 21:47:07.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16860 21:47:07.063 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16861 21:47:07.063 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16862 21:47:07.063 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16863 21:47:07.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16864 21:47:07.063 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16865 21:47:07.063 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16866 21:47:07.063 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16867 21:47:07.063 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16868 21:47:07.063 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16869 21:47:07.063 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16870 21:47:07.063 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16871 21:47:07.063 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16872 21:47:07.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16873 21:47:07.063 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16874 21:47:07.063 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16875 21:47:07.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16876 21:47:07.063 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16877 21:47:07.063 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16878 21:47:07.063 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16879 21:47:07.063 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16880 21:47:07.063 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16881 21:47:07.063 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16882 21:47:07.063 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16883 21:47:07.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16884 21:47:07.063 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16885 21:47:07.063 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16886 21:47:07.063 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16887 21:47:07.063 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16888 21:47:07.063 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16889 21:47:07.063 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16890 21:47:07.063 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16891 21:47:07.063 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16892 21:47:07.063 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16893 21:47:07.063 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16894 21:47:07.063 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16895 21:47:07.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16896 21:47:07.063 0.02687883 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16897 21:47:07.094 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16898 21:47:07.094 0.01428070 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16899 21:47:07.094 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16900 21:47:07.110 0.00032356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16901 21:47:07.110 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16902 21:47:07.110 0.00043615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16903 21:47:07.110 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16904 21:47:07.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16905 21:47:07.110 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 16906 21:47:07.110 0.00024099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16907 21:47:07.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16908 21:47:07.110 0.00044484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16909 21:47:07.110 0.00040415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 16910 21:47:07.110 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16911 21:47:07.110 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16912 21:47:07.110 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16913 21:47:07.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16914 21:47:07.110 0.00028523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16915 21:47:07.110 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16916 21:47:07.110 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16917 21:47:07.110 0.00036385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16918 21:47:07.110 0.00031842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16919 21:47:07.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16920 21:47:07.110 0.00034489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16921 21:47:07.110 0.00031723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16922 21:47:07.110 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16923 21:47:07.110 0.00029748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16924 21:47:07.110 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16925 21:47:07.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16926 21:47:07.110 0.00026193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16927 21:47:07.110 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16928 21:47:07.110 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16929 21:47:07.110 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16930 21:47:07.110 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16931 21:47:07.110 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16932 21:47:07.110 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16933 21:47:07.110 0.00029946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16934 21:47:07.110 0.00033975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16935 21:47:07.110 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16936 21:47:07.110 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16938 21:47:07.110 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16939 21:47:07.110 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16940 21:47:07.110 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16941 21:47:07.110 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16942 21:47:07.110 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16943 21:47:07.110 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16944 21:47:07.110 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16945 21:47:07.110 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16946 21:47:07.110 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16947 21:47:07.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16948 21:47:07.110 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16949 21:47:07.110 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16950 21:47:07.110 0.00023901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16951 21:47:07.110 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16952 21:47:07.110 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16953 21:47:07.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16954 21:47:07.110 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16955 21:47:07.110 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16956 21:47:07.110 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16957 21:47:07.110 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16958 21:47:07.110 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16959 21:47:07.110 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16960 21:47:07.110 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16961 21:47:07.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16962 21:47:07.110 0.02609463 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16963 21:47:07.141 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16964 21:47:07.141 0.01371102 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16965 21:47:07.141 0.00001541 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 16966 21:47:07.157 0.00041521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 16967 21:47:07.157 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16968 21:47:07.157 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16969 21:47:07.157 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 16970 21:47:07.157 0.00029827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 16971 21:47:07.157 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16972 21:47:07.157 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16973 21:47:07.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16974 21:47:07.157 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16975 21:47:07.157 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 16976 21:47:07.157 0.00031249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 16977 21:47:07.157 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16978 21:47:07.157 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16979 21:47:07.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16980 21:47:07.157 0.00028879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16981 21:47:07.157 0.00029906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16982 21:47:07.157 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16983 21:47:07.157 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16984 21:47:07.157 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16985 21:47:07.157 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16986 21:47:07.157 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16987 21:47:07.157 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16988 21:47:07.157 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16989 21:47:07.157 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16990 21:47:07.157 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16991 21:47:07.157 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16992 21:47:07.157 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16993 21:47:07.157 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16994 21:47:07.157 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16995 21:47:07.157 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16996 21:47:07.157 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 16997 21:47:07.157 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 16998 21:47:07.157 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 16999 21:47:07.157 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17000 21:47:07.157 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17001 21:47:07.157 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17002 21:47:07.157 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17003 21:47:07.157 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17004 21:47:07.157 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17005 21:47:07.157 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17006 21:47:07.157 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17007 21:47:07.157 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17008 21:47:07.157 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17009 21:47:07.157 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17010 21:47:07.157 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17011 21:47:07.157 0.00026983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17012 21:47:07.157 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17013 21:47:07.157 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17014 21:47:07.157 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17015 21:47:07.157 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17016 21:47:07.157 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17017 21:47:07.157 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17018 21:47:07.157 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17019 21:47:07.157 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17020 21:47:07.157 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17021 21:47:07.157 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17022 21:47:07.157 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17023 21:47:07.157 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17024 21:47:07.157 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17025 21:47:07.157 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17026 21:47:07.157 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17027 21:47:07.157 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17028 21:47:07.157 0.02755201 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17029 21:47:07.188 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17030 21:47:07.188 0.01215684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17031 21:47:07.188 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17032 21:47:07.204 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17033 21:47:07.204 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17034 21:47:07.204 0.00027299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17035 21:47:07.204 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17036 21:47:07.204 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17037 21:47:07.204 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 17 17038 21:47:07.204 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17039 21:47:07.204 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17040 21:47:07.204 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17041 21:47:07.204 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 17042 21:47:07.204 0.00030657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17043 21:47:07.204 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17044 21:47:07.204 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17045 21:47:07.204 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17046 21:47:07.204 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17047 21:47:07.204 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17048 21:47:07.204 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17049 21:47:07.204 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17050 21:47:07.204 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17051 21:47:07.204 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17052 21:47:07.204 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17053 21:47:07.204 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17054 21:47:07.204 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17055 21:47:07.204 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17056 21:47:07.204 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17057 21:47:07.204 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17058 21:47:07.204 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17059 21:47:07.204 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17060 21:47:07.204 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17061 21:47:07.204 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17062 21:47:07.204 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17063 21:47:07.204 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17064 21:47:07.204 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17065 21:47:07.204 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17066 21:47:07.204 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17067 21:47:07.204 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17068 21:47:07.204 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17069 21:47:07.204 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17070 21:47:07.204 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17071 21:47:07.204 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17072 21:47:07.204 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17073 21:47:07.204 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17074 21:47:07.204 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17075 21:47:07.204 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17076 21:47:07.204 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17077 21:47:07.204 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17078 21:47:07.204 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17079 21:47:07.204 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17080 21:47:07.204 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17081 21:47:07.204 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17082 21:47:07.204 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 17083 21:47:07.204 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 17087 21:47:07.204 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17088 21:47:07.204 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17089 21:47:07.204 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17090 21:47:07.204 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17091 21:47:07.204 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17092 21:47:07.204 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17093 21:47:07.204 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17094 21:47:07.204 0.02701315 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17095 21:47:07.235 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17096 21:47:07.235 0.01464613 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17097 21:47:07.235 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17098 21:47:07.251 0.00032553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17099 21:47:07.251 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17100 21:47:07.251 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17101 21:47:07.251 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17102 21:47:07.251 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17103 21:47:07.251 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17104 21:47:07.251 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17105 21:47:07.251 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17106 21:47:07.251 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17107 21:47:07.251 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 17108 21:47:07.251 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17109 21:47:07.251 0.00033462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17110 21:47:07.251 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17111 21:47:07.251 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17112 21:47:07.251 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17113 21:47:07.251 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17114 21:47:07.251 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17115 21:47:07.251 0.00043220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17116 21:47:07.251 0.00024454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17117 21:47:07.251 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17118 21:47:07.251 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17119 21:47:07.251 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17120 21:47:07.251 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17121 21:47:07.251 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17122 21:47:07.251 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17123 21:47:07.251 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17124 21:47:07.251 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17125 21:47:07.251 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17126 21:47:07.251 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17127 21:47:07.251 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17128 21:47:07.251 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17129 21:47:07.251 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17130 21:47:07.251 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17131 21:47:07.251 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17132 21:47:07.251 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17133 21:47:07.251 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17134 21:47:07.251 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17135 21:47:07.251 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17136 21:47:07.251 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17137 21:47:07.251 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17138 21:47:07.251 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17139 21:47:07.251 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17140 21:47:07.251 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17141 21:47:07.251 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17142 21:47:07.251 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17143 21:47:07.251 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17144 21:47:07.251 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17145 21:47:07.251 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17146 21:47:07.251 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17147 21:47:07.251 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17148 21:47:07.251 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17149 21:47:07.251 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17150 21:47:07.251 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17151 21:47:07.251 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17152 21:47:07.251 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17153 21:47:07.251 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17154 21:47:07.251 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17155 21:47:07.251 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17156 21:47:07.251 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17157 21:47:07.251 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17158 21:47:07.251 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17159 21:47:07.251 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17160 21:47:07.251 0.02658766 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17161 21:47:07.282 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17162 21:47:07.282 0.02865147 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17163 21:47:07.282 0.00001422 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17164 21:47:07.313 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17165 21:47:07.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17166 21:47:07.313 0.00034133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17167 21:47:07.313 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17168 21:47:07.313 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17169 21:47:07.313 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17170 21:47:07.313 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17171 21:47:07.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17172 21:47:07.313 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17173 21:47:07.313 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 17174 21:47:07.313 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17175 21:47:07.313 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17176 21:47:07.313 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17177 21:47:07.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17178 21:47:07.313 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17179 21:47:07.313 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17180 21:47:07.313 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17181 21:47:07.313 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17182 21:47:07.313 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17183 21:47:07.313 0.00027101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17184 21:47:07.313 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17185 21:47:07.313 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17186 21:47:07.313 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17187 21:47:07.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17188 21:47:07.313 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17189 21:47:07.313 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17191 21:47:07.313 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17192 21:47:07.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17193 21:47:07.313 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17194 21:47:07.313 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17195 21:47:07.313 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17196 21:47:07.313 0.00025719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17197 21:47:07.313 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17198 21:47:07.313 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17199 21:47:07.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17200 21:47:07.313 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17201 21:47:07.313 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17202 21:47:07.313 0.00029116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17203 21:47:07.313 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17204 21:47:07.313 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17205 21:47:07.313 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17206 21:47:07.313 0.00030578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17207 21:47:07.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17208 21:47:07.313 0.00038242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17209 21:47:07.313 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17210 21:47:07.313 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17211 21:47:07.313 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17212 21:47:07.313 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17213 21:47:07.313 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17214 21:47:07.313 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17215 21:47:07.313 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17216 21:47:07.313 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17217 21:47:07.313 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17218 21:47:07.313 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17219 21:47:07.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17220 21:47:07.313 0.00024652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17221 21:47:07.313 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17222 21:47:07.313 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17223 21:47:07.313 0.00018726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17224 21:47:07.313 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17225 21:47:07.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17226 21:47:07.313 0.02608475 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17227 21:47:07.344 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17228 21:47:07.344 0.01346963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17229 21:47:07.344 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17230 21:47:07.359 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17231 21:47:07.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17232 21:47:07.359 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17233 21:47:07.359 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17234 21:47:07.359 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17235 21:47:07.359 0.00117254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17236 21:47:07.359 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17237 21:47:07.359 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17238 21:47:07.359 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17239 21:47:07.359 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17240 21:47:07.359 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17241 21:47:07.359 0.00029669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17242 21:47:07.359 0.00043694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17243 21:47:07.359 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17244 21:47:07.359 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17245 21:47:07.359 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17246 21:47:07.359 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17247 21:47:07.359 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17248 21:47:07.359 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17249 21:47:07.359 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17250 21:47:07.359 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17251 21:47:07.359 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17252 21:47:07.359 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 17253 21:47:07.359 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17254 21:47:07.359 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 17255 21:47:07.359 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17256 21:47:07.359 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17257 21:47:07.359 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17258 21:47:07.359 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17259 21:47:07.359 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17260 21:47:07.359 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17261 21:47:07.359 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 17262 21:47:07.359 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17263 21:47:07.359 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 17270 21:47:07.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17271 21:47:07.359 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17272 21:47:07.359 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17273 21:47:07.359 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17274 21:47:07.359 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17275 21:47:07.359 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17276 21:47:07.359 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17277 21:47:07.359 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17278 21:47:07.359 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17279 21:47:07.359 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17280 21:47:07.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17281 21:47:07.359 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17282 21:47:07.359 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17283 21:47:07.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17284 21:47:07.359 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17285 21:47:07.359 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17286 21:47:07.359 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17287 21:47:07.359 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17288 21:47:07.359 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17289 21:47:07.359 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17290 21:47:07.359 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17291 21:47:07.359 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17292 21:47:07.359 0.02658450 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17293 21:47:07.391 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17294 21:47:07.391 0.01419615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17295 21:47:07.391 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17296 21:47:07.406 0.00032198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17297 21:47:07.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17298 21:47:07.406 0.00027101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17299 21:47:07.406 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17300 21:47:07.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17301 21:47:07.406 0.00030104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17302 21:47:07.406 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17303 21:47:07.406 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17304 21:47:07.406 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17305 21:47:07.406 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17306 21:47:07.406 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17307 21:47:07.406 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17308 21:47:07.406 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17309 21:47:07.406 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17310 21:47:07.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17311 21:47:07.406 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17312 21:47:07.406 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17313 21:47:07.406 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17314 21:47:07.406 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17315 21:47:07.406 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17316 21:47:07.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17317 21:47:07.406 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17318 21:47:07.406 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17319 21:47:07.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17320 21:47:07.406 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17321 21:47:07.406 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17322 21:47:07.406 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17323 21:47:07.406 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17324 21:47:07.406 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17325 21:47:07.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17326 21:47:07.406 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17327 21:47:07.406 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17328 21:47:07.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17329 21:47:07.406 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17330 21:47:07.406 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17331 21:47:07.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17332 21:47:07.406 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17333 21:47:07.406 0.00008533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17334 21:47:07.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17335 21:47:07.406 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17336 21:47:07.406 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17337 21:47:07.406 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17338 21:47:07.406 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17339 21:47:07.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17340 21:47:07.406 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17341 21:47:07.406 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17342 21:47:07.406 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17343 21:47:07.406 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17344 21:47:07.406 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17345 21:47:07.406 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17346 21:47:07.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17347 21:47:07.406 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17348 21:47:07.406 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17349 21:47:07.406 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17350 21:47:07.406 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17351 21:47:07.406 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17352 21:47:07.406 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17353 21:47:07.406 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17354 21:47:07.406 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17355 21:47:07.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17356 21:47:07.406 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17357 21:47:07.406 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17358 21:47:07.406 0.02891300 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17359 21:47:07.438 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17360 21:47:07.438 0.01320099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17361 21:47:07.438 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17362 21:47:07.453 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17363 21:47:07.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17364 21:47:07.453 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17365 21:47:07.453 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17366 21:47:07.453 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17367 21:47:07.453 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17368 21:47:07.453 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17369 21:47:07.453 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 17370 21:47:07.453 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17371 21:47:07.453 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17372 21:47:07.453 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17373 21:47:07.453 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17374 21:47:07.453 0.00030499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17375 21:47:07.453 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17376 21:47:07.453 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17377 21:47:07.453 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17378 21:47:07.453 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17379 21:47:07.453 0.00021412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17380 21:47:07.453 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17381 21:47:07.453 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17382 21:47:07.453 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17383 21:47:07.453 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17384 21:47:07.453 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17385 21:47:07.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17386 21:47:07.453 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17387 21:47:07.453 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17388 21:47:07.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17389 21:47:07.453 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17390 21:47:07.453 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17391 21:47:07.453 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17392 21:47:07.453 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17393 21:47:07.453 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17394 21:47:07.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17395 21:47:07.453 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17396 21:47:07.453 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17397 21:47:07.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17398 21:47:07.453 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17399 21:47:07.453 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17400 21:47:07.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17401 21:47:07.453 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17402 21:47:07.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17403 21:47:07.453 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17404 21:47:07.453 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17405 21:47:07.453 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17406 21:47:07.453 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17407 21:47:07.453 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17408 21:47:07.453 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17409 21:47:07.453 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17410 21:47:07.453 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17411 21:47:07.453 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17412 21:47:07.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17413 21:47:07.453 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17414 21:47:07.453 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17415 21:47:07.453 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17416 21:47:07.453 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17417 21:47:07.453 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17418 21:47:07.453 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17419 21:47:07.453 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17420 21:47:07.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17421 21:47:07.453 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17422 21:47:07.453 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17423 21:47:07.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17424 21:47:07.453 0.02729641 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17425 21:47:07.485 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17426 21:47:07.485 0.01382124 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17427 21:47:07.485 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17428 21:47:07.500 0.00041007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17429 21:47:07.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17430 21:47:07.500 0.00034331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17431 21:47:07.500 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17432 21:47:07.500 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17433 21:47:07.500 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17434 21:47:07.500 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17435 21:47:07.500 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17436 21:47:07.500 0.00025007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17437 21:47:07.500 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 17438 21:47:07.500 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17439 21:47:07.500 0.00027694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17440 21:47:07.500 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17441 21:47:07.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17442 21:47:07.500 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17443 21:47:07.500 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17444 21:47:07.500 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17445 21:47:07.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17446 21:47:07.500 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17447 21:47:07.500 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17448 21:47:07.500 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17449 21:47:07.500 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17450 21:47:07.500 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17451 21:47:07.500 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17452 21:47:07.500 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17453 21:47:07.500 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17454 21:47:07.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17455 21:47:07.500 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17456 21:47:07.500 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17457 21:47:07.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17458 21:47:07.500 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17459 21:47:07.500 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17460 21:47:07.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17461 21:47:07.500 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17462 21:47:07.500 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17463 21:47:07.500 0.00023111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17464 21:47:07.500 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17465 21:47:07.500 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17466 21:47:07.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17467 21:47:07.500 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17468 21:47:07.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17469 21:47:07.500 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17470 21:47:07.500 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17471 21:47:07.500 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17472 21:47:07.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17473 21:47:07.500 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17474 21:47:07.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17475 21:47:07.500 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17476 21:47:07.500 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17477 21:47:07.500 0.00008810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17478 21:47:07.500 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17479 21:47:07.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17480 21:47:07.500 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17481 21:47:07.500 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17482 21:47:07.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17483 21:47:07.500 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17484 21:47:07.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17485 21:47:07.500 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17486 21:47:07.500 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17487 21:47:07.500 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17488 21:47:07.500 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17489 21:47:07.500 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17490 21:47:07.500 0.02792653 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17491 21:47:07.531 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17492 21:47:07.531 0.01252149 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17493 21:47:07.531 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17494 21:47:07.547 0.00037491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17495 21:47:07.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17496 21:47:07.547 0.00042351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17497 21:47:07.547 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17498 21:47:07.547 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17499 21:47:07.547 0.00049817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17500 21:47:07.547 0.00042706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17501 21:47:07.547 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 17502 21:47:07.547 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17503 21:47:07.547 0.00024889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17504 21:47:07.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17505 21:47:07.547 0.00034410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17506 21:47:07.547 0.00030933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17507 21:47:07.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17508 21:47:07.547 0.00030933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17509 21:47:07.547 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17510 21:47:07.547 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17511 21:47:07.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17512 21:47:07.547 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17513 21:47:07.547 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17514 21:47:07.547 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17515 21:47:07.547 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17516 21:47:07.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17517 21:47:07.547 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17518 21:47:07.547 0.00027180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17519 21:47:07.547 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17520 21:47:07.547 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17521 21:47:07.547 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17522 21:47:07.547 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17523 21:47:07.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17524 21:47:07.547 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17525 21:47:07.547 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17526 21:47:07.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17527 21:47:07.547 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17528 21:47:07.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17529 21:47:07.547 0.00029116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17530 21:47:07.547 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17531 21:47:07.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17532 21:47:07.547 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17533 21:47:07.547 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17534 21:47:07.547 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17535 21:47:07.547 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17536 21:47:07.547 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17537 21:47:07.547 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17538 21:47:07.547 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17539 21:47:07.547 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17540 21:47:07.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17541 21:47:07.547 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17542 21:47:07.547 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17543 21:47:07.547 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17544 21:47:07.547 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17545 21:47:07.547 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17546 21:47:07.547 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17547 21:47:07.547 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17548 21:47:07.547 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17549 21:47:07.547 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17550 21:47:07.547 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17551 21:47:07.547 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17552 21:47:07.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17553 21:47:07.547 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17554 21:47:07.547 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17555 21:47:07.547 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17556 21:47:07.547 0.02598599 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17557 21:47:07.578 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17558 21:47:07.578 0.01343171 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17559 21:47:07.578 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17560 21:47:07.594 0.00040257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17561 21:47:07.594 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17562 21:47:07.594 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17563 21:47:07.594 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17564 21:47:07.594 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17565 21:47:07.594 0.00025363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17566 21:47:07.594 0.00031644 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17567 21:47:07.594 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17568 21:47:07.594 0.00025521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 17569 21:47:07.594 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17570 21:47:07.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17571 21:47:07.594 0.00032277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17572 21:47:07.594 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17573 21:47:07.594 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17574 21:47:07.594 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17575 21:47:07.594 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17576 21:47:07.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17577 21:47:07.594 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17578 21:47:07.594 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17579 21:47:07.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17580 21:47:07.594 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17581 21:47:07.594 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17582 21:47:07.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17583 21:47:07.594 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17584 21:47:07.594 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17585 21:47:07.594 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17586 21:47:07.594 0.00034094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17587 21:47:07.594 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17588 21:47:07.594 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17589 21:47:07.594 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17590 21:47:07.594 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17591 21:47:07.594 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17592 21:47:07.594 0.00033027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17593 21:47:07.594 0.00035793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17594 21:47:07.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17595 21:47:07.594 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17596 21:47:07.594 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17597 21:47:07.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17598 21:47:07.594 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17599 21:47:07.594 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17600 21:47:07.594 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17601 21:47:07.594 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17602 21:47:07.594 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17603 21:47:07.594 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17604 21:47:07.594 0.00029669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17605 21:47:07.594 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17606 21:47:07.594 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17607 21:47:07.594 0.00039072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17608 21:47:07.594 0.00034291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17609 21:47:07.594 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17610 21:47:07.594 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17611 21:47:07.594 0.00028800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17612 21:47:07.594 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17613 21:47:07.594 0.00031407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17614 21:47:07.594 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17615 21:47:07.594 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17616 21:47:07.594 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17617 21:47:07.594 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17618 21:47:07.594 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17619 21:47:07.594 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17620 21:47:07.594 0.00026390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17621 21:47:07.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17622 21:47:07.594 0.02549334 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17623 21:47:07.625 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17624 21:47:07.625 0.01375052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17625 21:47:07.625 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17626 21:47:07.641 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17627 21:47:07.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17628 21:47:07.641 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17629 21:47:07.641 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17630 21:47:07.641 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17631 21:47:07.641 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17632 21:47:07.641 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17633 21:47:07.641 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17634 21:47:07.641 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17635 21:47:07.641 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 17636 21:47:07.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17637 21:47:07.641 0.00031407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17638 21:47:07.641 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17639 21:47:07.641 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17640 21:47:07.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17641 21:47:07.641 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17642 21:47:07.641 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17643 21:47:07.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17644 21:47:07.641 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17645 21:47:07.641 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17646 21:47:07.641 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17647 21:47:07.641 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17648 21:47:07.641 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17649 21:47:07.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17650 21:47:07.641 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17651 21:47:07.641 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17652 21:47:07.641 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17653 21:47:07.641 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17654 21:47:07.641 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17655 21:47:07.641 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17656 21:47:07.641 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17660 21:47:07.641 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17661 21:47:07.641 0.00025047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17662 21:47:07.641 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17663 21:47:07.641 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17664 21:47:07.641 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17665 21:47:07.641 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17666 21:47:07.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17667 21:47:07.641 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17668 21:47:07.641 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17669 21:47:07.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17670 21:47:07.641 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17671 21:47:07.641 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17672 21:47:07.641 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17673 21:47:07.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17674 21:47:07.641 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17675 21:47:07.641 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17676 21:47:07.641 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17677 21:47:07.641 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17678 21:47:07.641 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17679 21:47:07.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17680 21:47:07.641 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17681 21:47:07.641 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17682 21:47:07.641 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17683 21:47:07.641 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17684 21:47:07.641 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17685 21:47:07.641 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17686 21:47:07.641 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17687 21:47:07.641 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17688 21:47:07.641 0.02690806 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17689 21:47:07.672 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17690 21:47:07.672 0.01439724 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17691 21:47:07.672 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17692 21:47:07.688 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17693 21:47:07.688 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17694 21:47:07.688 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17695 21:47:07.688 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17696 21:47:07.688 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17697 21:47:07.688 0.00030815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17698 21:47:07.688 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17699 21:47:07.688 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 17700 21:47:07.688 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17701 21:47:07.688 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17702 21:47:07.688 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17703 21:47:07.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17704 21:47:07.688 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17705 21:47:07.688 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17706 21:47:07.688 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17707 21:47:07.688 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17708 21:47:07.688 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17709 21:47:07.688 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17710 21:47:07.688 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17711 21:47:07.688 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17712 21:47:07.688 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17713 21:47:07.688 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17714 21:47:07.688 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17715 21:47:07.688 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17716 21:47:07.688 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17717 21:47:07.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17718 21:47:07.688 0.00028365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17719 21:47:07.688 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17720 21:47:07.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17721 21:47:07.688 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17722 21:47:07.688 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17723 21:47:07.688 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17724 21:47:07.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17725 21:47:07.688 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17726 21:47:07.688 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17727 21:47:07.688 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17728 21:47:07.688 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17729 21:47:07.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17730 21:47:07.688 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17731 21:47:07.688 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17732 21:47:07.688 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17733 21:47:07.688 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17734 21:47:07.688 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17735 21:47:07.688 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17736 21:47:07.688 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17737 21:47:07.688 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17738 21:47:07.688 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17739 21:47:07.688 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17740 21:47:07.688 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17741 21:47:07.688 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17742 21:47:07.688 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17743 21:47:07.688 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17744 21:47:07.688 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17745 21:47:07.688 0.00031368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17746 21:47:07.688 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17747 21:47:07.688 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17748 21:47:07.688 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17749 21:47:07.688 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17750 21:47:07.688 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17751 21:47:07.688 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17752 21:47:07.688 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17753 21:47:07.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17754 21:47:07.688 0.02741137 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17755 21:47:07.719 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17756 21:47:07.719 0.01345541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17757 21:47:07.719 0.00001659 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17758 21:47:07.735 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17759 21:47:07.735 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17760 21:47:07.735 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17761 21:47:07.735 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17762 21:47:07.735 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17763 21:47:07.735 0.00095526 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17764 21:47:07.735 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17765 21:47:07.735 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 17766 21:47:07.735 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17767 21:47:07.735 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17768 21:47:07.735 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17769 21:47:07.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17770 21:47:07.735 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17771 21:47:07.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17772 21:47:07.735 0.00027773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17773 21:47:07.735 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17774 21:47:07.735 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17775 21:47:07.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17776 21:47:07.735 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17777 21:47:07.735 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17778 21:47:07.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17779 21:47:07.735 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17780 21:47:07.735 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17781 21:47:07.735 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17782 21:47:07.735 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17783 21:47:07.735 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 17788 21:47:07.735 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17789 21:47:07.735 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17790 21:47:07.735 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17791 21:47:07.735 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17792 21:47:07.735 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17793 21:47:07.735 0.00031881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17794 21:47:07.735 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17795 21:47:07.735 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17796 21:47:07.735 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17797 21:47:07.735 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17798 21:47:07.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17799 21:47:07.735 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17800 21:47:07.735 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17801 21:47:07.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17802 21:47:07.735 0.00024731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17803 21:47:07.735 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17804 21:47:07.735 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17805 21:47:07.735 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17806 21:47:07.735 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17807 21:47:07.735 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17808 21:47:07.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17809 21:47:07.735 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17810 21:47:07.735 0.00024138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17811 21:47:07.735 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17812 21:47:07.735 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17813 21:47:07.735 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17814 21:47:07.735 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17815 21:47:07.735 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17816 21:47:07.735 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17817 21:47:07.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17818 21:47:07.735 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17819 21:47:07.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17820 21:47:07.735 0.02621591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17821 21:47:07.766 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17822 21:47:07.766 0.01370983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17823 21:47:07.766 0.00002923 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17824 21:47:07.782 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17825 21:47:07.782 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17826 21:47:07.782 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17827 21:47:07.782 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17828 21:47:07.782 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17829 21:47:07.782 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17830 21:47:07.782 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17831 21:47:07.782 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 17832 21:47:07.782 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17833 21:47:07.782 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17834 21:47:07.782 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17835 21:47:07.782 0.00041916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17836 21:47:07.782 0.00036741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17837 21:47:07.782 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17838 21:47:07.782 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17839 21:47:07.782 0.00028247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17840 21:47:07.782 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17841 21:47:07.782 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17842 21:47:07.782 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17843 21:47:07.782 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17844 21:47:07.782 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17845 21:47:07.782 0.00028444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17846 21:47:07.782 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17847 21:47:07.782 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17848 21:47:07.782 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17849 21:47:07.782 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17850 21:47:07.782 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17851 21:47:07.782 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17852 21:47:07.782 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17853 21:47:07.782 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17854 21:47:07.782 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17855 21:47:07.782 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17856 21:47:07.782 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17857 21:47:07.782 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17858 21:47:07.782 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17859 21:47:07.782 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17860 21:47:07.782 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17861 21:47:07.782 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17862 21:47:07.782 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17863 21:47:07.782 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17864 21:47:07.782 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17865 21:47:07.782 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17866 21:47:07.782 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17867 21:47:07.782 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17868 21:47:07.782 0.00029274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17869 21:47:07.782 0.00035279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17870 21:47:07.782 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17871 21:47:07.782 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17872 21:47:07.782 0.00024770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17873 21:47:07.782 0.00030459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17874 21:47:07.782 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17875 21:47:07.782 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17876 21:47:07.782 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17877 21:47:07.782 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17878 21:47:07.782 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17879 21:47:07.782 0.00034607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17880 21:47:07.782 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17881 21:47:07.782 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17882 21:47:07.782 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17883 21:47:07.782 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17884 21:47:07.782 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17885 21:47:07.782 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17886 21:47:07.782 0.02623290 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17887 21:47:07.813 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17888 21:47:07.813 0.01340840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17889 21:47:07.813 0.00003240 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17890 21:47:07.829 0.00032869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17891 21:47:07.829 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17892 21:47:07.829 0.00025995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17893 21:47:07.829 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17894 21:47:07.829 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 17895 21:47:07.829 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17896 21:47:07.829 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17897 21:47:07.829 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17898 21:47:07.829 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17899 21:47:07.829 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 17900 21:47:07.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17901 21:47:07.829 0.00027338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17902 21:47:07.829 0.00030815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17903 21:47:07.829 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17904 21:47:07.829 0.00026153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17905 21:47:07.829 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 17906 21:47:07.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17907 21:47:07.829 0.00045867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17908 21:47:07.829 0.00034923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17909 21:47:07.829 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17910 21:47:07.829 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17911 21:47:07.829 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17912 21:47:07.829 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17913 21:47:07.829 0.00033857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17914 21:47:07.829 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17915 21:47:07.829 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17916 21:47:07.829 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17917 21:47:07.829 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17918 21:47:07.829 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17919 21:47:07.829 0.00032356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17920 21:47:07.829 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17921 21:47:07.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17922 21:47:07.829 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17923 21:47:07.829 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17924 21:47:07.829 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17925 21:47:07.829 0.00027338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17926 21:47:07.829 0.00034489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17927 21:47:07.829 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17928 21:47:07.829 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17929 21:47:07.829 0.00022716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17930 21:47:07.829 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17931 21:47:07.829 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17932 21:47:07.829 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17933 21:47:07.829 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17934 21:47:07.829 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17935 21:47:07.829 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17936 21:47:07.829 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17937 21:47:07.829 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17938 21:47:07.829 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17939 21:47:07.829 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17940 21:47:07.829 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17941 21:47:07.829 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17942 21:47:07.829 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17943 21:47:07.829 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17944 21:47:07.829 0.00025877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17945 21:47:07.829 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17946 21:47:07.829 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17947 21:47:07.829 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17948 21:47:07.829 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17949 21:47:07.829 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17950 21:47:07.829 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17951 21:47:07.829 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17952 21:47:07.829 0.02542974 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17953 21:47:07.860 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17954 21:47:07.860 0.01385126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17955 21:47:07.860 0.00003042 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 17956 21:47:07.875 0.00027180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 17957 21:47:07.875 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17958 21:47:07.875 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17959 21:47:07.875 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 17960 21:47:07.875 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17961 21:47:07.875 0.00028919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17962 21:47:07.875 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 17963 21:47:07.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17964 21:47:07.875 0.00033343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17965 21:47:07.875 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 17966 21:47:07.875 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17967 21:47:07.875 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 17968 21:47:07.875 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17969 21:47:07.875 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17970 21:47:07.875 0.00033383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17971 21:47:07.875 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17972 21:47:07.875 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17973 21:47:07.875 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17974 21:47:07.875 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17975 21:47:07.875 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17976 21:47:07.875 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17977 21:47:07.875 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17978 21:47:07.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17979 21:47:07.875 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17980 21:47:07.875 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17981 21:47:07.875 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17982 21:47:07.875 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17983 21:47:07.875 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17984 21:47:07.875 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17985 21:47:07.875 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17986 21:47:07.875 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17987 21:47:07.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17988 21:47:07.875 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17989 21:47:07.875 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17990 21:47:07.875 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17991 21:47:07.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17992 21:47:07.875 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17993 21:47:07.875 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17994 21:47:07.875 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17995 21:47:07.875 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17996 21:47:07.875 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 17997 21:47:07.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 17998 21:47:07.875 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 17999 21:47:07.875 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18000 21:47:07.875 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18001 21:47:07.875 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18002 21:47:07.875 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18003 21:47:07.875 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18004 21:47:07.875 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18005 21:47:07.875 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18006 21:47:07.875 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18007 21:47:07.875 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18008 21:47:07.875 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18009 21:47:07.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18010 21:47:07.875 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18011 21:47:07.875 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18012 21:47:07.875 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18013 21:47:07.875 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18014 21:47:07.875 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18015 21:47:07.875 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18016 21:47:07.875 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18017 21:47:07.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18018 21:47:07.875 0.02765394 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18019 21:47:07.907 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18020 21:47:07.907 0.01389354 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18021 21:47:07.907 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18022 21:47:07.922 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18023 21:47:07.922 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18024 21:47:07.922 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18025 21:47:07.922 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18026 21:47:07.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18027 21:47:07.922 0.00108998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18028 21:47:07.922 0.00104928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18029 21:47:07.922 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 18030 21:47:07.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18031 21:47:07.922 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18032 21:47:07.922 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18033 21:47:07.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18034 21:47:07.922 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18035 21:47:07.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18036 21:47:07.922 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18037 21:47:07.922 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18038 21:47:07.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18039 21:47:07.922 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18040 21:47:07.922 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18041 21:47:07.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18042 21:47:07.922 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18043 21:47:07.922 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18044 21:47:07.922 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18045 21:47:07.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18046 21:47:07.922 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18047 21:47:07.922 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18048 21:47:07.922 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18049 21:47:07.922 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18050 21:47:07.922 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18051 21:47:07.922 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18052 21:47:07.922 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18053 21:47:07.922 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18054 21:47:07.922 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18055 21:47:07.922 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18056 21:47:07.922 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18057 21:47:07.922 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18058 21:47:07.922 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18059 21:47:07.922 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18060 21:47:07.922 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18061 21:47:07.922 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18062 21:47:07.922 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18063 21:47:07.922 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18064 21:47:07.922 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18065 21:47:07.922 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18066 21:47:07.922 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18067 21:47:07.922 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18068 21:47:07.922 0.00046854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18069 21:47:07.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18070 21:47:07.922 0.00036899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18071 21:47:07.922 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18072 21:47:07.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18073 21:47:07.922 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18074 21:47:07.922 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18075 21:47:07.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18076 21:47:07.922 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18077 21:47:07.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18078 21:47:07.922 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18079 21:47:07.922 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18080 21:47:07.922 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18081 21:47:07.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18082 21:47:07.922 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18083 21:47:07.922 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18084 21:47:07.922 0.02728376 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18085 21:47:07.954 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18086 21:47:07.954 0.01295803 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18087 21:47:07.954 0.00008494 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18088 21:47:07.969 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18089 21:47:07.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18090 21:47:07.969 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18091 21:47:07.969 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18092 21:47:07.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18093 21:47:07.969 0.00031605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18094 21:47:07.969 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18095 21:47:07.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18096 21:47:07.969 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18097 21:47:07.969 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 18098 21:47:07.969 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18099 21:47:07.969 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18100 21:47:07.969 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18101 21:47:07.969 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18102 21:47:07.969 0.00029274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18103 21:47:07.969 0.00024533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18104 21:47:07.969 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18105 21:47:07.969 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18106 21:47:07.969 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18107 21:47:07.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18108 21:47:07.969 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18109 21:47:07.969 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18110 21:47:07.969 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18111 21:47:07.969 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18112 21:47:07.969 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18113 21:47:07.969 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18114 21:47:07.969 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18115 21:47:07.969 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18116 21:47:07.969 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18117 21:47:07.969 0.00036662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18118 21:47:07.969 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18119 21:47:07.969 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18120 21:47:07.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18121 21:47:07.969 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18122 21:47:07.969 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18123 21:47:07.969 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18124 21:47:07.969 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18125 21:47:07.969 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18126 21:47:07.969 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18127 21:47:07.969 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18128 21:47:07.969 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18129 21:47:07.969 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18130 21:47:07.969 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18131 21:47:07.969 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18132 21:47:07.969 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18133 21:47:07.969 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18134 21:47:07.969 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18135 21:47:07.969 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18136 21:47:07.969 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18137 21:47:07.969 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18138 21:47:07.969 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18139 21:47:07.969 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18140 21:47:07.969 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18141 21:47:07.969 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18142 21:47:07.969 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18143 21:47:07.969 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18144 21:47:07.969 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18145 21:47:07.969 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18146 21:47:07.969 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18147 21:47:07.969 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18148 21:47:07.969 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18149 21:47:07.969 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18150 21:47:07.969 0.02808732 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18151 21:47:08.000 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18152 21:47:08.000 0.01433798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18153 21:47:08.000 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18154 21:47:08.016 0.00061235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18155 21:47:08.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18156 21:47:08.016 0.00051240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18157 21:47:08.016 0.00039348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18158 21:47:08.016 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18159 21:47:08.016 0.00039862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18160 21:47:08.016 0.00031407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18161 21:47:08.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18162 21:47:08.016 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18163 21:47:08.016 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 18164 21:47:08.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18165 21:47:08.016 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18166 21:47:08.016 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18167 21:47:08.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18168 21:47:08.016 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18169 21:47:08.016 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18170 21:47:08.016 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18171 21:47:08.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18172 21:47:08.016 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18173 21:47:08.016 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18174 21:47:08.016 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18175 21:47:08.016 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18176 21:47:08.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18177 21:47:08.016 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18178 21:47:08.016 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18179 21:47:08.016 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18180 21:47:08.016 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18181 21:47:08.016 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18182 21:47:08.016 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18183 21:47:08.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18184 21:47:08.016 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18185 21:47:08.016 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18186 21:47:08.016 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18187 21:47:08.016 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18188 21:47:08.016 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18189 21:47:08.016 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18190 21:47:08.016 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18191 21:47:08.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18192 21:47:08.016 0.00026430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18193 21:47:08.016 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18194 21:47:08.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18195 21:47:08.016 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18196 21:47:08.016 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18197 21:47:08.016 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18198 21:47:08.016 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18199 21:47:08.016 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18200 21:47:08.016 0.00027654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18201 21:47:08.016 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18202 21:47:08.016 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18203 21:47:08.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18204 21:47:08.016 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18205 21:47:08.016 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18206 21:47:08.016 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18207 21:47:08.016 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18208 21:47:08.016 0.00026825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18209 21:47:08.016 0.00027180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18210 21:47:08.016 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18211 21:47:08.016 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18212 21:47:08.016 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18213 21:47:08.016 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18214 21:47:08.016 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18215 21:47:08.016 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18216 21:47:08.016 0.02453650 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18217 21:47:08.047 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18218 21:47:08.047 0.01430440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18219 21:47:08.047 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18220 21:47:08.063 0.00030578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18221 21:47:08.063 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18222 21:47:08.063 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18223 21:47:08.063 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18224 21:47:08.063 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18225 21:47:08.063 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18226 21:47:08.063 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18227 21:47:08.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18228 21:47:08.063 0.00043496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18229 21:47:08.063 0.00034173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 18230 21:47:08.063 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18231 21:47:08.063 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18232 21:47:08.063 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18233 21:47:08.063 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18234 21:47:08.063 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18235 21:47:08.063 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18236 21:47:08.063 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18237 21:47:08.063 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18238 21:47:08.063 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18239 21:47:08.063 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18240 21:47:08.063 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18241 21:47:08.063 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18242 21:47:08.063 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18243 21:47:08.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18244 21:47:08.063 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18245 21:47:08.063 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18246 21:47:08.063 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18247 21:47:08.063 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18248 21:47:08.063 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18249 21:47:08.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18250 21:47:08.063 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18251 21:47:08.063 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18252 21:47:08.063 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18253 21:47:08.063 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18254 21:47:08.063 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18255 21:47:08.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18256 21:47:08.063 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18257 21:47:08.063 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18258 21:47:08.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18259 21:47:08.063 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18260 21:47:08.063 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18261 21:47:08.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18262 21:47:08.063 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18263 21:47:08.063 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18264 21:47:08.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18265 21:47:08.063 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18266 21:47:08.063 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18267 21:47:08.063 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18268 21:47:08.063 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18269 21:47:08.063 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18270 21:47:08.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18271 21:47:08.063 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18272 21:47:08.063 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18273 21:47:08.063 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18274 21:47:08.063 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18275 21:47:08.063 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18276 21:47:08.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18277 21:47:08.063 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18278 21:47:08.063 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18280 21:47:08.063 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18281 21:47:08.063 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18282 21:47:08.063 0.02803794 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18283 21:47:08.094 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18284 21:47:08.094 0.01357038 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18285 21:47:08.094 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18286 21:47:08.110 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18287 21:47:08.110 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18288 21:47:08.110 0.00037807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18289 21:47:08.110 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18290 21:47:08.110 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18291 21:47:08.110 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18292 21:47:08.110 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18293 21:47:08.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18294 21:47:08.110 0.00036109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18295 21:47:08.110 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 18296 21:47:08.110 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18297 21:47:08.110 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18298 21:47:08.110 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18299 21:47:08.110 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18300 21:47:08.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18301 21:47:08.110 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18302 21:47:08.110 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18303 21:47:08.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18304 21:47:08.110 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18305 21:47:08.110 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18306 21:47:08.110 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18308 21:47:08.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18309 21:47:08.110 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18310 21:47:08.110 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18311 21:47:08.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18312 21:47:08.110 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18313 21:47:08.110 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18314 21:47:08.110 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18315 21:47:08.110 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 18316 21:47:08.110 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 18320 21:47:08.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18321 21:47:08.110 0.00045156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18322 21:47:08.110 0.00038598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18323 21:47:08.110 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18324 21:47:08.110 0.00038440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18325 21:47:08.110 0.00028919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18326 21:47:08.110 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18327 21:47:08.110 0.00028247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18328 21:47:08.110 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18329 21:47:08.110 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18330 21:47:08.110 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18331 21:47:08.110 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18332 21:47:08.110 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18333 21:47:08.110 0.00036346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18334 21:47:08.110 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18335 21:47:08.110 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18336 21:47:08.110 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18337 21:47:08.110 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18338 21:47:08.110 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18339 21:47:08.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18340 21:47:08.110 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18341 21:47:08.110 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18342 21:47:08.110 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18343 21:47:08.110 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18344 21:47:08.110 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18345 21:47:08.110 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18346 21:47:08.110 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18347 21:47:08.110 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18348 21:47:08.110 0.02375547 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18349 21:47:08.141 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18350 21:47:08.141 0.02905996 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18351 21:47:08.141 0.00000672 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18352 21:47:08.172 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18353 21:47:08.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18354 21:47:08.172 0.00035595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18355 21:47:08.172 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18356 21:47:08.172 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18357 21:47:08.172 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18358 21:47:08.172 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18359 21:47:08.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18360 21:47:08.172 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18361 21:47:08.172 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 18362 21:47:08.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18363 21:47:08.172 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18364 21:47:08.172 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18365 21:47:08.172 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18366 21:47:08.172 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18367 21:47:08.172 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18368 21:47:08.172 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18369 21:47:08.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18370 21:47:08.172 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18371 21:47:08.172 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18372 21:47:08.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18373 21:47:08.172 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18374 21:47:08.172 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18375 21:47:08.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18376 21:47:08.172 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18377 21:47:08.172 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18378 21:47:08.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18379 21:47:08.172 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18380 21:47:08.172 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18381 21:47:08.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18382 21:47:08.172 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18383 21:47:08.172 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18384 21:47:08.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18385 21:47:08.172 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18386 21:47:08.172 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18387 21:47:08.172 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18388 21:47:08.172 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18389 21:47:08.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18390 21:47:08.172 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18391 21:47:08.172 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18392 21:47:08.172 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18393 21:47:08.172 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18394 21:47:08.172 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18395 21:47:08.172 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18396 21:47:08.172 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18397 21:47:08.172 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18398 21:47:08.172 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18399 21:47:08.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18400 21:47:08.172 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18401 21:47:08.172 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18402 21:47:08.172 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18403 21:47:08.172 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18404 21:47:08.172 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18405 21:47:08.172 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18406 21:47:08.172 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18407 21:47:08.172 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18408 21:47:08.172 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18409 21:47:08.172 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18410 21:47:08.172 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18411 21:47:08.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18412 21:47:08.172 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18413 21:47:08.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18414 21:47:08.172 0.02844367 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18415 21:47:08.203 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18416 21:47:08.203 0.01376317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18417 21:47:08.203 0.00002805 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18418 21:47:08.219 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18419 21:47:08.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18420 21:47:08.219 0.00030380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18421 21:47:08.219 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18422 21:47:08.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18423 21:47:08.219 0.00039309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18424 21:47:08.219 0.00030854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18425 21:47:08.219 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 18426 21:47:08.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18427 21:47:08.219 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18428 21:47:08.219 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18429 21:47:08.219 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18430 21:47:08.219 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18431 21:47:08.219 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18432 21:47:08.219 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18433 21:47:08.219 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18434 21:47:08.219 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18435 21:47:08.219 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18436 21:47:08.219 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18437 21:47:08.219 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18438 21:47:08.219 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18439 21:47:08.219 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18440 21:47:08.219 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18441 21:47:08.219 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18442 21:47:08.219 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18443 21:47:08.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18444 21:47:08.219 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18445 21:47:08.219 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18446 21:47:08.219 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18447 21:47:08.219 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18448 21:47:08.219 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18449 21:47:08.219 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18450 21:47:08.219 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18451 21:47:08.219 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18452 21:47:08.219 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18453 21:47:08.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18454 21:47:08.219 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18455 21:47:08.219 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18456 21:47:08.219 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18457 21:47:08.219 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18458 21:47:08.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18459 21:47:08.219 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18460 21:47:08.219 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18461 21:47:08.219 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18462 21:47:08.219 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18463 21:47:08.219 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18464 21:47:08.219 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18465 21:47:08.219 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18466 21:47:08.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18467 21:47:08.219 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18468 21:47:08.219 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18469 21:47:08.219 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18470 21:47:08.219 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18471 21:47:08.219 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18472 21:47:08.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18473 21:47:08.219 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18474 21:47:08.219 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18475 21:47:08.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18476 21:47:08.219 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18477 21:47:08.219 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18478 21:47:08.219 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18479 21:47:08.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18480 21:47:08.219 0.02762747 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18481 21:47:08.250 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18482 21:47:08.250 0.01346647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18483 21:47:08.250 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18484 21:47:08.266 0.00031961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18485 21:47:08.266 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18486 21:47:08.266 0.00045630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18487 21:47:08.266 0.00028444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18488 21:47:08.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18489 21:47:08.266 0.00028998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18490 21:47:08.266 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18491 21:47:08.266 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18492 21:47:08.266 0.00041402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 18493 21:47:08.266 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18494 21:47:08.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18495 21:47:08.266 0.00038874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18496 21:47:08.266 0.00032237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18497 21:47:08.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18498 21:47:08.266 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18499 21:47:08.266 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18500 21:47:08.266 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18501 21:47:08.266 0.00031091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18502 21:47:08.266 0.00023980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18503 21:47:08.266 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18504 21:47:08.266 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18505 21:47:08.266 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18506 21:47:08.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18507 21:47:08.266 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18508 21:47:08.266 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18509 21:47:08.266 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18510 21:47:08.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18511 21:47:08.266 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18512 21:47:08.266 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18513 21:47:08.266 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18514 21:47:08.266 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18515 21:47:08.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18516 21:47:08.266 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18517 21:47:08.266 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18518 21:47:08.266 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18519 21:47:08.266 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18520 21:47:08.266 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18521 21:47:08.266 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18522 21:47:08.266 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18523 21:47:08.266 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18524 21:47:08.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18525 21:47:08.266 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18526 21:47:08.266 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18527 21:47:08.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18528 21:47:08.266 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18529 21:47:08.266 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18530 21:47:08.266 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18531 21:47:08.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18532 21:47:08.266 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18533 21:47:08.266 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18534 21:47:08.266 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18535 21:47:08.266 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18536 21:47:08.266 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18537 21:47:08.266 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18538 21:47:08.266 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18539 21:47:08.266 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18540 21:47:08.266 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18541 21:47:08.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18542 21:47:08.266 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18543 21:47:08.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18544 21:47:08.266 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18545 21:47:08.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18546 21:47:08.266 0.02655369 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18547 21:47:08.297 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18548 21:47:08.297 0.01348386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18549 21:47:08.297 0.00003398 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18550 21:47:08.313 0.00028721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18551 21:47:08.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18552 21:47:08.313 0.00037333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18553 21:47:08.313 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18554 21:47:08.313 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18555 21:47:08.313 0.00115358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18556 21:47:08.313 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18557 21:47:08.313 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 18558 21:47:08.313 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18559 21:47:08.313 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18560 21:47:08.313 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18561 21:47:08.313 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18562 21:47:08.313 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18563 21:47:08.313 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18564 21:47:08.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18565 21:47:08.313 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18566 21:47:08.313 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18567 21:47:08.313 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18568 21:47:08.313 0.00020425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18569 21:47:08.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18570 21:47:08.313 0.00028523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18571 21:47:08.313 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18572 21:47:08.313 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18573 21:47:08.313 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18574 21:47:08.313 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18575 21:47:08.313 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18576 21:47:08.313 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18577 21:47:08.313 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18578 21:47:08.313 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18579 21:47:08.313 0.00052662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18580 21:47:08.313 0.00040059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18581 21:47:08.313 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18582 21:47:08.313 0.00032316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18583 21:47:08.313 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18584 21:47:08.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18585 21:47:08.313 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18586 21:47:08.313 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18587 21:47:08.313 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18588 21:47:08.313 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18589 21:47:08.313 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18590 21:47:08.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18591 21:47:08.313 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18592 21:47:08.313 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18593 21:47:08.313 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18594 21:47:08.313 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18595 21:47:08.313 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18596 21:47:08.313 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18597 21:47:08.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18598 21:47:08.313 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18599 21:47:08.313 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18600 21:47:08.313 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18601 21:47:08.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18602 21:47:08.313 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18603 21:47:08.313 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18604 21:47:08.313 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18605 21:47:08.313 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18606 21:47:08.313 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18607 21:47:08.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18608 21:47:08.313 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18609 21:47:08.313 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18610 21:47:08.313 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18611 21:47:08.313 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18612 21:47:08.313 0.02509354 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18613 21:47:08.344 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18614 21:47:08.344 0.01416534 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18615 21:47:08.344 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18616 21:47:08.360 0.00028405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18617 21:47:08.360 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18618 21:47:08.360 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18619 21:47:08.360 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18620 21:47:08.360 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18621 21:47:08.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18622 21:47:08.360 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18623 21:47:08.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18624 21:47:08.360 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 18625 21:47:08.360 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18626 21:47:08.360 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18627 21:47:08.360 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18628 21:47:08.360 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18629 21:47:08.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18630 21:47:08.360 0.00016869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18631 21:47:08.360 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18632 21:47:08.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18633 21:47:08.360 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18634 21:47:08.360 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18635 21:47:08.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18636 21:47:08.360 0.00023269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18637 21:47:08.360 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18638 21:47:08.360 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18639 21:47:08.360 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18640 21:47:08.360 0.00016435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18641 21:47:08.360 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18642 21:47:08.360 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18643 21:47:08.360 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18644 21:47:08.360 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18645 21:47:08.360 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18646 21:47:08.360 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18647 21:47:08.360 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18648 21:47:08.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18649 21:47:08.360 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18650 21:47:08.360 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18651 21:47:08.360 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18652 21:47:08.360 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18653 21:47:08.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18654 21:47:08.360 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18655 21:47:08.360 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18656 21:47:08.360 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18657 21:47:08.360 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18658 21:47:08.360 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18659 21:47:08.360 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 18660 21:47:08.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18661 21:47:08.360 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 18665 21:47:08.360 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18666 21:47:08.360 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18667 21:47:08.360 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18668 21:47:08.360 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18669 21:47:08.360 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18670 21:47:08.360 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18671 21:47:08.360 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18672 21:47:08.360 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18673 21:47:08.360 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18674 21:47:08.360 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18675 21:47:08.360 0.00041047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18676 21:47:08.360 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18677 21:47:08.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18678 21:47:08.360 0.02793957 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18679 21:47:08.391 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18680 21:47:08.391 0.00006558 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18681 21:47:08.391 0.01341749 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18682 21:47:08.407 0.00033225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18683 21:47:08.407 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18684 21:47:08.407 0.00045551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18685 21:47:08.407 0.00039862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18686 21:47:08.407 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18687 21:47:08.407 0.00026193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18688 21:47:08.407 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18689 21:47:08.407 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18690 21:47:08.407 0.00031526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18691 21:47:08.407 0.00034923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 18692 21:47:08.407 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18693 21:47:08.407 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18694 21:47:08.407 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18695 21:47:08.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18696 21:47:08.407 0.00024889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18697 21:47:08.407 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18698 21:47:08.407 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18699 21:47:08.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18700 21:47:08.407 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18701 21:47:08.407 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18702 21:47:08.407 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18703 21:47:08.407 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18704 21:47:08.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18705 21:47:08.407 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18706 21:47:08.407 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18707 21:47:08.407 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18708 21:47:08.407 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18709 21:47:08.407 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18710 21:47:08.407 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18711 21:47:08.407 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18712 21:47:08.407 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18713 21:47:08.407 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18714 21:47:08.407 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18715 21:47:08.407 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18716 21:47:08.407 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18717 21:47:08.407 0.00024731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18718 21:47:08.407 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18719 21:47:08.407 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18720 21:47:08.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18721 21:47:08.407 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18722 21:47:08.407 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18723 21:47:08.407 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18724 21:47:08.407 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18725 21:47:08.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18726 21:47:08.407 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18727 21:47:08.407 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18728 21:47:08.407 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18729 21:47:08.407 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18730 21:47:08.407 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18731 21:47:08.407 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 18732 21:47:08.407 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18733 21:47:08.407 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 18736 21:47:08.407 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18737 21:47:08.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18738 21:47:08.407 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18739 21:47:08.407 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18740 21:47:08.407 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18741 21:47:08.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18742 21:47:08.407 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18743 21:47:08.407 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18744 21:47:08.407 0.02734381 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18745 21:47:08.437 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18746 21:47:08.437 0.01179062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18748 21:47:08.453 0.00033027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18749 21:47:08.453 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18750 21:47:08.453 0.00028484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18751 21:47:08.453 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18752 21:47:08.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18753 21:47:08.453 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18754 21:47:08.453 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18755 21:47:08.453 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 18756 21:47:08.453 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18757 21:47:08.453 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18758 21:47:08.453 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18759 21:47:08.453 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18760 21:47:08.453 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18761 21:47:08.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18762 21:47:08.453 0.00031802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18763 21:47:08.453 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18764 21:47:08.453 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18765 21:47:08.453 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18766 21:47:08.453 0.00036504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18767 21:47:08.453 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18768 21:47:08.453 0.00037926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18769 21:47:08.453 0.00029314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18770 21:47:08.453 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18771 21:47:08.453 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18772 21:47:08.453 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18773 21:47:08.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18774 21:47:08.453 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18775 21:47:08.453 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18776 21:47:08.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18777 21:47:08.453 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18778 21:47:08.453 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18779 21:47:08.453 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18780 21:47:08.453 0.00031921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18781 21:47:08.453 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18782 21:47:08.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18783 21:47:08.453 0.00023230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18784 21:47:08.453 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18785 21:47:08.453 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18786 21:47:08.453 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18787 21:47:08.453 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18788 21:47:08.453 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18789 21:47:08.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18790 21:47:08.453 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18791 21:47:08.453 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18792 21:47:08.453 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18793 21:47:08.453 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18794 21:47:08.453 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18795 21:47:08.453 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18796 21:47:08.453 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18797 21:47:08.453 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 18798 21:47:08.453 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18799 21:47:08.453 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 18803 21:47:08.453 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18804 21:47:08.453 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18805 21:47:08.453 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18806 21:47:08.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18807 21:47:08.453 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18808 21:47:08.453 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18809 21:47:08.453 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18810 21:47:08.453 0.02602826 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18811 21:47:08.484 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18812 21:47:08.484 0.01433601 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18813 21:47:08.484 0.00002252 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18814 21:47:08.500 0.00035002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18815 21:47:08.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18816 21:47:08.500 0.00031447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18817 21:47:08.500 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18818 21:47:08.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18819 21:47:08.500 0.00018449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18820 21:47:08.500 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18821 21:47:08.500 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18822 21:47:08.500 0.00032672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18823 21:47:08.500 0.00026667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 18824 21:47:08.500 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18825 21:47:08.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18826 21:47:08.500 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18827 21:47:08.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18828 21:47:08.500 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18829 21:47:08.500 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18830 21:47:08.500 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18831 21:47:08.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18832 21:47:08.500 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18833 21:47:08.500 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18834 21:47:08.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18835 21:47:08.500 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18836 21:47:08.500 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18837 21:47:08.500 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18838 21:47:08.500 0.00027457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18839 21:47:08.500 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18840 21:47:08.500 0.00027338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18841 21:47:08.500 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18842 21:47:08.500 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18843 21:47:08.500 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18844 21:47:08.500 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18845 21:47:08.500 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18846 21:47:08.500 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 18847 21:47:08.500 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 18850 21:47:08.500 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18851 21:47:08.500 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18852 21:47:08.500 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18853 21:47:08.500 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18854 21:47:08.500 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18855 21:47:08.500 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18856 21:47:08.500 0.00008020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18857 21:47:08.500 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18858 21:47:08.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18859 21:47:08.500 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18860 21:47:08.500 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18861 21:47:08.500 0.00029235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18862 21:47:08.500 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18863 21:47:08.500 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18864 21:47:08.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18865 21:47:08.500 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18866 21:47:08.500 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18867 21:47:08.500 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18868 21:47:08.500 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18869 21:47:08.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18870 21:47:08.500 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18871 21:47:08.500 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18872 21:47:08.500 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 18875 21:47:08.500 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18876 21:47:08.500 0.02709808 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18877 21:47:08.531 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18878 21:47:08.531 0.01337403 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18879 21:47:08.531 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18880 21:47:08.547 0.00042627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18881 21:47:08.547 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18882 21:47:08.547 0.00032158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18883 21:47:08.547 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18884 21:47:08.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18885 21:47:08.547 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 18886 21:47:08.547 0.00032553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18887 21:47:08.547 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 18888 21:47:08.547 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18889 21:47:08.547 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18890 21:47:08.547 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18891 21:47:08.547 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18892 21:47:08.547 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18893 21:47:08.547 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18894 21:47:08.547 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18895 21:47:08.547 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18896 21:47:08.547 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18897 21:47:08.547 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18898 21:47:08.547 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18899 21:47:08.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18900 21:47:08.547 0.00027852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18901 21:47:08.547 0.00031961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18902 21:47:08.547 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18903 21:47:08.547 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18904 21:47:08.547 0.00030854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18905 21:47:08.547 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18906 21:47:08.547 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18907 21:47:08.547 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18908 21:47:08.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18909 21:47:08.547 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18910 21:47:08.547 0.00031170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18911 21:47:08.547 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18912 21:47:08.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18913 21:47:08.547 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18914 21:47:08.547 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18915 21:47:08.547 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18916 21:47:08.547 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18917 21:47:08.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18918 21:47:08.547 0.00027654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18919 21:47:08.547 0.00029393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18920 21:47:08.547 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18921 21:47:08.547 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18922 21:47:08.547 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18923 21:47:08.547 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18924 21:47:08.547 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18925 21:47:08.547 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18926 21:47:08.547 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18927 21:47:08.547 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18928 21:47:08.547 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18929 21:47:08.547 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18930 21:47:08.547 0.00030578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18931 21:47:08.547 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18932 21:47:08.547 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18933 21:47:08.547 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18934 21:47:08.547 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18935 21:47:08.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18936 21:47:08.547 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18937 21:47:08.547 0.00022598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18938 21:47:08.547 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18939 21:47:08.547 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18940 21:47:08.547 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18941 21:47:08.547 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18942 21:47:08.547 0.02766342 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18943 21:47:08.578 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18944 21:47:08.578 0.01235635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18945 21:47:08.578 0.00001185 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 18946 21:47:08.594 0.00032198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 18947 21:47:08.594 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 18948 21:47:08.594 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18949 21:47:08.594 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18950 21:47:08.594 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 18951 21:47:08.594 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18952 21:47:08.594 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18953 21:47:08.594 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 18954 21:47:08.594 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18955 21:47:08.594 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18956 21:47:08.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18957 21:47:08.594 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18958 21:47:08.594 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 18959 21:47:08.594 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18960 21:47:08.594 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18961 21:47:08.594 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18962 21:47:08.594 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18963 21:47:08.594 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18964 21:47:08.594 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 18965 21:47:08.594 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18966 21:47:08.594 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18967 21:47:08.594 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18968 21:47:08.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18969 21:47:08.594 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18970 21:47:08.594 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18971 21:47:08.594 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18972 21:47:08.594 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18973 21:47:08.594 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18974 21:47:08.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18975 21:47:08.594 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18976 21:47:08.594 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18977 21:47:08.594 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18978 21:47:08.594 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18979 21:47:08.594 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18980 21:47:08.594 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18981 21:47:08.594 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18982 21:47:08.594 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18983 21:47:08.594 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18984 21:47:08.594 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18985 21:47:08.594 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18986 21:47:08.594 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18987 21:47:08.594 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18988 21:47:08.594 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18989 21:47:08.594 0.00008336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18990 21:47:08.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18991 21:47:08.594 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18992 21:47:08.594 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18993 21:47:08.594 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18994 21:47:08.594 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18995 21:47:08.594 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18996 21:47:08.594 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 18997 21:47:08.594 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 18998 21:47:08.594 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 18999 21:47:08.594 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19000 21:47:08.594 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19001 21:47:08.594 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19002 21:47:08.594 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19003 21:47:08.594 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19004 21:47:08.594 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19005 21:47:08.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19006 21:47:08.594 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19007 21:47:08.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19008 21:47:08.594 0.02750539 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19009 21:47:08.625 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19010 21:47:08.625 0.01406420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19011 21:47:08.625 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19012 21:47:08.641 0.00031368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19013 21:47:08.641 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19014 21:47:08.641 0.00041995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19015 21:47:08.641 0.00035477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19016 21:47:08.641 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19017 21:47:08.641 0.00028800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19018 21:47:08.641 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 19019 21:47:08.641 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19020 21:47:08.641 0.00034528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19021 21:47:08.641 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 19022 21:47:08.641 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19023 21:47:08.641 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19024 21:47:08.641 0.00027654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19025 21:47:08.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19026 21:47:08.641 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19027 21:47:08.641 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19031 21:47:08.641 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19032 21:47:08.641 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19033 21:47:08.641 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19034 21:47:08.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19035 21:47:08.641 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19036 21:47:08.641 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19037 21:47:08.641 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19038 21:47:08.641 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19039 21:47:08.641 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19040 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19041 21:47:08.641 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19042 21:47:08.641 0.00008138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19043 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19044 21:47:08.641 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19045 21:47:08.641 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19046 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19047 21:47:08.641 0.00026114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19048 21:47:08.641 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19049 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19050 21:47:08.641 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19051 21:47:08.641 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19052 21:47:08.641 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19053 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19054 21:47:08.641 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19055 21:47:08.641 0.00030578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19056 21:47:08.641 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19057 21:47:08.641 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19058 21:47:08.641 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19059 21:47:08.641 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19060 21:47:08.641 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19061 21:47:08.641 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19062 21:47:08.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19063 21:47:08.641 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19064 21:47:08.641 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19065 21:47:08.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19066 21:47:08.641 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19067 21:47:08.641 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19068 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19069 21:47:08.641 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19070 21:47:08.641 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19071 21:47:08.641 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19072 21:47:08.641 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19073 21:47:08.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19074 21:47:08.641 0.02696218 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19075 21:47:08.672 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19076 21:47:08.672 0.01402707 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19077 21:47:08.672 0.00001975 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19078 21:47:08.688 0.00039506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19079 21:47:08.688 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19080 21:47:08.688 0.00037649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19081 21:47:08.688 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19082 21:47:08.688 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19083 21:47:08.688 0.00034805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19084 21:47:08.688 0.00032158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 19085 21:47:08.688 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 19086 21:47:08.688 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19087 21:47:08.688 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19088 21:47:08.688 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 19089 21:47:08.688 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19090 21:47:08.688 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19092 21:47:08.688 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19093 21:47:08.688 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19094 21:47:08.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19095 21:47:08.688 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19096 21:47:08.688 0.00025521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19097 21:47:08.688 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19098 21:47:08.688 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19099 21:47:08.688 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19100 21:47:08.688 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19101 21:47:08.688 0.00033620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19102 21:47:08.688 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19103 21:47:08.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19104 21:47:08.688 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19105 21:47:08.688 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19106 21:47:08.688 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19107 21:47:08.688 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19108 21:47:08.688 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19109 21:47:08.688 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19110 21:47:08.688 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19111 21:47:08.688 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19112 21:47:08.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19113 21:47:08.688 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19114 21:47:08.688 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19115 21:47:08.688 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19116 21:47:08.688 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19117 21:47:08.688 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19118 21:47:08.688 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19119 21:47:08.688 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19120 21:47:08.688 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19123 21:47:08.688 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19124 21:47:08.688 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19125 21:47:08.688 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19126 21:47:08.688 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19127 21:47:08.688 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19128 21:47:08.688 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19129 21:47:08.688 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19130 21:47:08.688 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19131 21:47:08.688 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19132 21:47:08.688 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19133 21:47:08.688 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19134 21:47:08.688 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19135 21:47:08.688 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19136 21:47:08.688 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19138 21:47:08.688 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19139 21:47:08.688 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19140 21:47:08.688 0.02759863 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19141 21:47:08.719 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19142 21:47:08.719 0.01277512 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19143 21:47:08.719 0.00003635 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19144 21:47:08.735 0.00032553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19145 21:47:08.735 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19146 21:47:08.735 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19147 21:47:08.735 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19148 21:47:08.735 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 18 19149 21:47:08.735 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19150 21:47:08.735 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19151 21:47:08.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19152 21:47:08.735 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 19153 21:47:08.735 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19154 21:47:08.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19155 21:47:08.735 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19156 21:47:08.735 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19157 21:47:08.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19158 21:47:08.735 0.00036464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19159 21:47:08.735 0.00028247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19160 21:47:08.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19161 21:47:08.735 0.00030973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19162 21:47:08.735 0.00033304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19163 21:47:08.735 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19164 21:47:08.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19165 21:47:08.735 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19166 21:47:08.735 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19167 21:47:08.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19168 21:47:08.735 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19169 21:47:08.735 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19170 21:47:08.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19171 21:47:08.735 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19172 21:47:08.735 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19173 21:47:08.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19174 21:47:08.735 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19175 21:47:08.735 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19176 21:47:08.735 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19177 21:47:08.735 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19178 21:47:08.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19179 21:47:08.735 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19180 21:47:08.735 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19181 21:47:08.735 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19182 21:47:08.735 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19183 21:47:08.735 0.00023506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19184 21:47:08.735 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19185 21:47:08.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19186 21:47:08.735 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19187 21:47:08.735 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19188 21:47:08.735 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19189 21:47:08.735 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19190 21:47:08.735 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19191 21:47:08.735 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19192 21:47:08.735 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19193 21:47:08.735 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19194 21:47:08.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19195 21:47:08.735 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19196 21:47:08.735 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19197 21:47:08.735 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19198 21:47:08.735 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19199 21:47:08.735 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19200 21:47:08.735 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19201 21:47:08.735 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19202 21:47:08.735 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19203 21:47:08.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19204 21:47:08.735 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19205 21:47:08.735 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19206 21:47:08.735 0.02826194 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19207 21:47:08.766 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19208 21:47:08.766 0.02814381 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19209 21:47:08.766 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19210 21:47:08.797 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19211 21:47:08.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19212 21:47:08.797 0.00034252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19213 21:47:08.797 0.00030538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19214 21:47:08.797 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19215 21:47:08.797 0.00027536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19216 21:47:08.797 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 19217 21:47:08.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19218 21:47:08.797 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19219 21:47:08.797 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 19220 21:47:08.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19221 21:47:08.797 0.00026311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19222 21:47:08.797 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19223 21:47:08.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19224 21:47:08.797 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19225 21:47:08.797 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19226 21:47:08.797 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19227 21:47:08.797 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19228 21:47:08.797 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19229 21:47:08.797 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19230 21:47:08.797 0.00030617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19231 21:47:08.797 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19232 21:47:08.797 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19233 21:47:08.797 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19234 21:47:08.797 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19235 21:47:08.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19236 21:47:08.797 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19237 21:47:08.797 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19238 21:47:08.797 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19239 21:47:08.797 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19240 21:47:08.797 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19241 21:47:08.797 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19242 21:47:08.797 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19243 21:47:08.797 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19244 21:47:08.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19245 21:47:08.797 0.00045116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19246 21:47:08.797 0.00035714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19247 21:47:08.797 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19248 21:47:08.797 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19249 21:47:08.797 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19250 21:47:08.797 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19251 21:47:08.797 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19252 21:47:08.797 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19253 21:47:08.797 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19254 21:47:08.797 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19255 21:47:08.797 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19256 21:47:08.797 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19257 21:47:08.797 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19258 21:47:08.797 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19259 21:47:08.797 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19260 21:47:08.797 0.00024691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19261 21:47:08.797 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19262 21:47:08.797 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19263 21:47:08.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19264 21:47:08.797 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19265 21:47:08.797 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19266 21:47:08.797 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19267 21:47:08.797 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19268 21:47:08.797 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19269 21:47:08.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19270 21:47:08.797 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19271 21:47:08.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19272 21:47:08.797 0.02481700 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19273 21:47:08.828 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19274 21:47:08.828 0.01484682 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19275 21:47:08.828 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19276 21:47:08.844 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19277 21:47:08.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19278 21:47:08.844 0.00026706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19279 21:47:08.844 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19280 21:47:08.844 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19281 21:47:08.844 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 19282 21:47:08.844 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19283 21:47:08.844 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 19284 21:47:08.844 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19285 21:47:08.844 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19286 21:47:08.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19287 21:47:08.844 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19288 21:47:08.844 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19289 21:47:08.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19290 21:47:08.844 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19291 21:47:08.844 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19292 21:47:08.844 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19293 21:47:08.844 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19294 21:47:08.844 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19295 21:47:08.844 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19296 21:47:08.844 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19297 21:47:08.844 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19298 21:47:08.844 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19299 21:47:08.844 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19300 21:47:08.844 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19301 21:47:08.844 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19302 21:47:08.844 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19303 21:47:08.844 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19304 21:47:08.844 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19305 21:47:08.844 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19306 21:47:08.844 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19307 21:47:08.844 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19308 21:47:08.844 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19309 21:47:08.844 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19310 21:47:08.844 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19311 21:47:08.844 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19312 21:47:08.844 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19313 21:47:08.844 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19314 21:47:08.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19315 21:47:08.844 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19316 21:47:08.844 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19317 21:47:08.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19318 21:47:08.844 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19319 21:47:08.844 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19320 21:47:08.844 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19321 21:47:08.844 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19322 21:47:08.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19323 21:47:08.844 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19324 21:47:08.844 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19325 21:47:08.844 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19326 21:47:08.844 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19327 21:47:08.844 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19328 21:47:08.844 0.00075694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19329 21:47:08.844 0.00059931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19330 21:47:08.844 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19331 21:47:08.844 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19332 21:47:08.844 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19334 21:47:08.844 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19335 21:47:08.844 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19336 21:47:08.844 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19337 21:47:08.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19338 21:47:08.844 0.02742441 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19339 21:47:08.875 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19340 21:47:08.875 0.01366203 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19341 21:47:08.875 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19342 21:47:08.891 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19343 21:47:08.891 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19344 21:47:08.891 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19345 21:47:08.891 0.00029788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19346 21:47:08.891 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19347 21:47:08.891 0.00027536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19348 21:47:08.891 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 19349 21:47:08.891 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19350 21:47:08.891 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19351 21:47:08.891 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19352 21:47:08.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19353 21:47:08.891 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19354 21:47:08.891 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19355 21:47:08.891 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19356 21:47:08.891 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19357 21:47:08.891 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19358 21:47:08.891 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19359 21:47:08.891 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19360 21:47:08.891 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19361 21:47:08.891 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19362 21:47:08.891 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19363 21:47:08.891 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19364 21:47:08.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19365 21:47:08.891 0.00027970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19366 21:47:08.891 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19367 21:47:08.891 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19368 21:47:08.891 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19369 21:47:08.891 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19370 21:47:08.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19371 21:47:08.891 0.00030578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19372 21:47:08.891 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19373 21:47:08.891 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19374 21:47:08.891 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19375 21:47:08.891 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19376 21:47:08.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19377 21:47:08.891 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19378 21:47:08.891 0.00023111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19379 21:47:08.891 0.00031170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19380 21:47:08.891 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19381 21:47:08.891 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19382 21:47:08.891 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19385 21:47:08.891 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19386 21:47:08.891 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19387 21:47:08.891 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19388 21:47:08.891 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19389 21:47:08.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19390 21:47:08.891 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19391 21:47:08.891 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19392 21:47:08.891 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19393 21:47:08.891 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19396 21:47:08.891 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19397 21:47:08.891 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19398 21:47:08.891 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19399 21:47:08.891 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19400 21:47:08.891 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19401 21:47:08.891 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19402 21:47:08.891 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19403 21:47:08.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19404 21:47:08.891 0.02528989 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19405 21:47:08.922 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19406 21:47:08.922 0.01436840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19407 21:47:08.922 0.00001462 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19408 21:47:08.938 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19409 21:47:08.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19410 21:47:08.938 0.00044484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19411 21:47:08.938 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19412 21:47:08.938 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 19413 21:47:08.938 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19414 21:47:08.938 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19415 21:47:08.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19416 21:47:08.938 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19417 21:47:08.938 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19418 21:47:08.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19419 21:47:08.938 0.00031605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19420 21:47:08.938 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19421 21:47:08.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19422 21:47:08.938 0.00031802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19423 21:47:08.938 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19424 21:47:08.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19425 21:47:08.938 0.00034133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19426 21:47:08.938 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19427 21:47:08.938 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19428 21:47:08.938 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19429 21:47:08.938 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19430 21:47:08.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19431 21:47:08.938 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19432 21:47:08.938 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19433 21:47:08.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19434 21:47:08.938 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19435 21:47:08.938 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19436 21:47:08.938 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19437 21:47:08.938 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19438 21:47:08.938 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19439 21:47:08.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19440 21:47:08.938 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19441 21:47:08.938 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19442 21:47:08.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19443 21:47:08.938 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19444 21:47:08.938 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19445 21:47:08.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19446 21:47:08.938 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19447 21:47:08.938 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19448 21:47:08.938 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19449 21:47:08.938 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19450 21:47:08.938 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19451 21:47:08.938 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19452 21:47:08.938 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19453 21:47:08.938 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19454 21:47:08.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19455 21:47:08.938 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19456 21:47:08.938 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19457 21:47:08.938 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19458 21:47:08.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19459 21:47:08.938 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19460 21:47:08.938 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19461 21:47:08.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19462 21:47:08.938 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19463 21:47:08.938 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19464 21:47:08.938 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19465 21:47:08.938 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19466 21:47:08.938 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19467 21:47:08.938 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19468 21:47:08.938 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19469 21:47:08.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19470 21:47:08.938 0.02618589 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19471 21:47:08.969 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19472 21:47:08.969 0.01486025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19473 21:47:08.969 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19474 21:47:08.985 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19475 21:47:08.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19476 21:47:08.985 0.00027536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19477 21:47:08.985 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19478 21:47:08.985 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 19479 21:47:08.985 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19480 21:47:08.985 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19481 21:47:08.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19482 21:47:08.985 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19483 21:47:08.985 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 19484 21:47:08.985 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19485 21:47:08.985 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19486 21:47:08.985 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19487 21:47:08.985 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19488 21:47:08.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19489 21:47:08.985 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19490 21:47:08.985 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19491 21:47:08.985 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19492 21:47:08.985 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19493 21:47:08.985 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19494 21:47:08.985 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19495 21:47:08.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19496 21:47:08.985 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19497 21:47:08.985 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19498 21:47:08.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19499 21:47:08.985 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19500 21:47:08.985 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19501 21:47:08.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19502 21:47:08.985 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19505 21:47:08.985 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19506 21:47:08.985 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19507 21:47:08.985 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19508 21:47:08.985 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19509 21:47:08.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19510 21:47:08.985 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19511 21:47:08.985 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19512 21:47:08.985 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19513 21:47:08.985 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19514 21:47:08.985 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19515 21:47:08.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19516 21:47:08.985 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19517 21:47:08.985 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19518 21:47:08.985 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19519 21:47:08.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19520 21:47:08.985 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19521 21:47:08.985 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19522 21:47:08.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19523 21:47:08.985 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19524 21:47:08.985 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19525 21:47:08.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19526 21:47:08.985 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19527 21:47:08.985 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19528 21:47:08.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19529 21:47:08.985 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19530 21:47:08.985 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19531 21:47:08.985 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19532 21:47:08.985 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19533 21:47:08.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19534 21:47:08.985 0.02713799 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19535 21:47:09.016 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19536 21:47:09.016 0.01440119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19537 21:47:09.016 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19538 21:47:09.032 0.00027022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19539 21:47:09.032 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19540 21:47:09.032 0.00038400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19541 21:47:09.032 0.00032711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19542 21:47:09.032 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19543 21:47:09.032 0.00030538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19544 21:47:09.032 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 19545 21:47:09.032 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19546 21:47:09.032 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 19547 21:47:09.032 0.00025995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19548 21:47:09.032 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19549 21:47:09.032 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19550 21:47:09.032 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19551 21:47:09.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19552 21:47:09.032 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19553 21:47:09.032 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19554 21:47:09.032 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19555 21:47:09.032 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19558 21:47:09.032 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19559 21:47:09.032 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19560 21:47:09.032 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19561 21:47:09.032 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19562 21:47:09.032 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19563 21:47:09.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19564 21:47:09.032 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19565 21:47:09.032 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19566 21:47:09.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19567 21:47:09.032 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19568 21:47:09.032 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19569 21:47:09.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19570 21:47:09.032 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19571 21:47:09.032 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19572 21:47:09.032 0.00031526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19573 21:47:09.032 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19574 21:47:09.032 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19575 21:47:09.032 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19576 21:47:09.032 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19578 21:47:09.032 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19579 21:47:09.032 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19580 21:47:09.032 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19581 21:47:09.032 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19582 21:47:09.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19583 21:47:09.032 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19584 21:47:09.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19585 21:47:09.032 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19586 21:47:09.032 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19587 21:47:09.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19588 21:47:09.032 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19589 21:47:09.032 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19590 21:47:09.032 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19591 21:47:09.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19592 21:47:09.032 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19593 21:47:09.032 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19594 21:47:09.032 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19595 21:47:09.032 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19596 21:47:09.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19597 21:47:09.032 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19598 21:47:09.032 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19599 21:47:09.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19600 21:47:09.032 0.02819636 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19601 21:47:09.063 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19602 21:47:09.063 0.01272968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19603 21:47:09.063 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19604 21:47:09.078 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19605 21:47:09.078 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19606 21:47:09.078 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19607 21:47:09.078 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19608 21:47:09.078 0.00090706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19609 21:47:09.078 0.00122351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 19610 21:47:09.078 0.00036701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19611 21:47:09.078 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19612 21:47:09.078 0.00028128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19613 21:47:09.078 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 19614 21:47:09.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19615 21:47:09.078 0.00038835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19616 21:47:09.078 0.00034726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19617 21:47:09.078 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19618 21:47:09.078 0.00042904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19619 21:47:09.078 0.00047131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19620 21:47:09.078 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19621 21:47:09.078 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19622 21:47:09.078 0.00047605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19623 21:47:09.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19624 21:47:09.078 0.00037096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19625 21:47:09.078 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19626 21:47:09.078 0.00029235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19627 21:47:09.078 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19628 21:47:09.078 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19629 21:47:09.078 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19630 21:47:09.078 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19631 21:47:09.078 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19632 21:47:09.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19633 21:47:09.078 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19634 21:47:09.078 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19635 21:47:09.078 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19637 21:47:09.078 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19638 21:47:09.078 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19639 21:47:09.078 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19640 21:47:09.078 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19641 21:47:09.078 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19642 21:47:09.078 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19643 21:47:09.078 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19647 21:47:09.078 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19648 21:47:09.078 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19649 21:47:09.078 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19650 21:47:09.078 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19651 21:47:09.078 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19652 21:47:09.078 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19653 21:47:09.078 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19654 21:47:09.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19655 21:47:09.078 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19656 21:47:09.078 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19657 21:47:09.078 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19658 21:47:09.078 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19659 21:47:09.078 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19660 21:47:09.078 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19661 21:47:09.078 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19662 21:47:09.078 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19663 21:47:09.078 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19664 21:47:09.078 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19665 21:47:09.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19666 21:47:09.078 0.02395181 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19667 21:47:09.110 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19668 21:47:09.110 0.01511349 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19669 21:47:09.110 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19670 21:47:09.125 0.00028207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19671 21:47:09.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19672 21:47:09.125 0.00029432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19673 21:47:09.125 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19674 21:47:09.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19675 21:47:09.125 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 19676 21:47:09.125 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19677 21:47:09.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19678 21:47:09.125 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19679 21:47:09.125 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 19680 21:47:09.125 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19681 21:47:09.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19682 21:47:09.125 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19683 21:47:09.125 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19684 21:47:09.125 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19685 21:47:09.125 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19686 21:47:09.125 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19687 21:47:09.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19688 21:47:09.125 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19689 21:47:09.125 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19690 21:47:09.125 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19691 21:47:09.125 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19692 21:47:09.125 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19693 21:47:09.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19694 21:47:09.125 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19695 21:47:09.125 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19696 21:47:09.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19697 21:47:09.125 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19698 21:47:09.125 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19699 21:47:09.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19700 21:47:09.125 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19701 21:47:09.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19702 21:47:09.125 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19703 21:47:09.125 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19704 21:47:09.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19705 21:47:09.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19708 21:47:09.125 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19709 21:47:09.125 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19710 21:47:09.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19711 21:47:09.125 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19712 21:47:09.125 0.00009560 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19713 21:47:09.125 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19714 21:47:09.125 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19715 21:47:09.125 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19716 21:47:09.125 0.00008138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19717 21:47:09.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19718 21:47:09.125 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19719 21:47:09.125 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19720 21:47:09.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19721 21:47:09.125 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19722 21:47:09.125 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19723 21:47:09.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19724 21:47:09.125 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19725 21:47:09.125 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19726 21:47:09.125 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19727 21:47:09.125 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19728 21:47:09.125 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19729 21:47:09.125 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19730 21:47:09.125 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19731 21:47:09.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19732 21:47:09.125 0.02759547 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19733 21:47:09.156 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19734 21:47:09.156 0.01433206 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19735 21:47:09.156 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19736 21:47:09.172 0.00032474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19737 21:47:09.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19738 21:47:09.172 0.00024770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19739 21:47:09.172 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19740 21:47:09.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19741 21:47:09.172 0.00026430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19742 21:47:09.172 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 19743 21:47:09.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19744 21:47:09.172 0.00037175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19745 21:47:09.172 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 19746 21:47:09.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19747 21:47:09.172 0.00038993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19748 21:47:09.172 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19749 21:47:09.172 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19750 21:47:09.172 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19751 21:47:09.172 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19752 21:47:09.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19753 21:47:09.172 0.00033343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19754 21:47:09.172 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19755 21:47:09.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19756 21:47:09.172 0.00037254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19757 21:47:09.172 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19758 21:47:09.172 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19759 21:47:09.172 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19760 21:47:09.172 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19761 21:47:09.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19762 21:47:09.172 0.00063012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19763 21:47:09.172 0.00053807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19764 21:47:09.172 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19765 21:47:09.172 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19766 21:47:09.172 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19767 21:47:09.172 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19768 21:47:09.172 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19769 21:47:09.172 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19770 21:47:09.172 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19771 21:47:09.172 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19772 21:47:09.172 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19773 21:47:09.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19774 21:47:09.172 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19775 21:47:09.172 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19776 21:47:09.172 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19777 21:47:09.172 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19778 21:47:09.172 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19779 21:47:09.172 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19780 21:47:09.172 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19781 21:47:09.172 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19782 21:47:09.172 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19783 21:47:09.172 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19784 21:47:09.172 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19785 21:47:09.172 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19786 21:47:09.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19787 21:47:09.172 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19788 21:47:09.172 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19789 21:47:09.172 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19790 21:47:09.172 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19791 21:47:09.172 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19792 21:47:09.172 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19793 21:47:09.172 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19794 21:47:09.172 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19795 21:47:09.172 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19797 21:47:09.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19798 21:47:09.172 0.02577265 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19799 21:47:09.203 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19800 21:47:09.203 0.01320810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19801 21:47:09.203 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19802 21:47:09.219 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19803 21:47:09.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19804 21:47:09.219 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19805 21:47:09.219 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19806 21:47:09.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19807 21:47:09.219 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19808 21:47:09.219 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 19809 21:47:09.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19810 21:47:09.219 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19811 21:47:09.219 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 19812 21:47:09.219 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19813 21:47:09.219 0.00021096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19814 21:47:09.219 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19815 21:47:09.219 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19816 21:47:09.219 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19817 21:47:09.219 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19818 21:47:09.219 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19819 21:47:09.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19820 21:47:09.219 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19821 21:47:09.219 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19822 21:47:09.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19823 21:47:09.219 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19824 21:47:09.219 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19825 21:47:09.219 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19826 21:47:09.219 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19827 21:47:09.219 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19828 21:47:09.219 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19829 21:47:09.219 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19830 21:47:09.219 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19831 21:47:09.219 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19832 21:47:09.219 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19833 21:47:09.219 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19834 21:47:09.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19835 21:47:09.219 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19836 21:47:09.219 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19837 21:47:09.219 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19838 21:47:09.219 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19839 21:47:09.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19840 21:47:09.219 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19841 21:47:09.219 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19842 21:47:09.219 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19843 21:47:09.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19844 21:47:09.219 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19845 21:47:09.219 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19846 21:47:09.219 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19847 21:47:09.219 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19848 21:47:09.219 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19849 21:47:09.219 0.00040573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19850 21:47:09.219 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19851 21:47:09.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19852 21:47:09.219 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19853 21:47:09.219 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19854 21:47:09.219 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19855 21:47:09.219 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19856 21:47:09.219 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19857 21:47:09.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19858 21:47:09.219 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19859 21:47:09.219 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19860 21:47:09.219 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19861 21:47:09.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19862 21:47:09.219 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19863 21:47:09.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19864 21:47:09.219 0.02881818 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19865 21:47:09.251 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19866 21:47:09.251 0.02776139 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19867 21:47:09.251 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19868 21:47:09.281 0.00037728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19869 21:47:09.281 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19870 21:47:09.281 0.00034528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19871 21:47:09.281 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19872 21:47:09.281 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 19873 21:47:09.281 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19874 21:47:09.281 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19875 21:47:09.281 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 19876 21:47:09.281 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19877 21:47:09.281 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19878 21:47:09.281 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19879 21:47:09.281 0.00032198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19880 21:47:09.281 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19881 21:47:09.281 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19882 21:47:09.281 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19883 21:47:09.281 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19884 21:47:09.281 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19885 21:47:09.281 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19886 21:47:09.281 0.00021294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19887 21:47:09.281 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19888 21:47:09.281 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19889 21:47:09.281 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19890 21:47:09.281 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19891 21:47:09.281 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19892 21:47:09.281 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19893 21:47:09.281 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19894 21:47:09.281 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19895 21:47:09.281 0.00016435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19896 21:47:09.281 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19897 21:47:09.281 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19898 21:47:09.281 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19899 21:47:09.281 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19900 21:47:09.281 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19901 21:47:09.281 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19902 21:47:09.281 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19903 21:47:09.281 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19904 21:47:09.281 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19905 21:47:09.281 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19906 21:47:09.281 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19907 21:47:09.281 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19908 21:47:09.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19909 21:47:09.281 0.00017738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19910 21:47:09.281 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19911 21:47:09.281 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19912 21:47:09.281 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19913 21:47:09.281 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19914 21:47:09.281 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19915 21:47:09.281 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19916 21:47:09.281 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19917 21:47:09.281 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19918 21:47:09.281 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19919 21:47:09.281 0.00009126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19920 21:47:09.281 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19921 21:47:09.281 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19922 21:47:09.281 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19923 21:47:09.281 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19924 21:47:09.281 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19925 21:47:09.281 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19926 21:47:09.281 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19927 21:47:09.281 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19928 21:47:09.281 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19929 21:47:09.281 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19930 21:47:09.281 0.02639211 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19931 21:47:09.313 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19932 21:47:09.313 0.01324445 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19933 21:47:09.313 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 19934 21:47:09.328 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 19935 21:47:09.328 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19936 21:47:09.328 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19937 21:47:09.328 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 19938 21:47:09.328 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 19939 21:47:09.328 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19940 21:47:09.328 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19941 21:47:09.328 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19942 21:47:09.328 0.00027299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19943 21:47:09.328 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 19944 21:47:09.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19945 21:47:09.328 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 19946 21:47:09.328 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19947 21:47:09.328 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 19948 21:47:09.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19949 21:47:09.328 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 19953 21:47:09.328 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19954 21:47:09.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19955 21:47:09.328 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19956 21:47:09.328 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19957 21:47:09.328 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19958 21:47:09.328 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19959 21:47:09.328 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19960 21:47:09.328 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19961 21:47:09.328 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19962 21:47:09.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19963 21:47:09.328 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19964 21:47:09.328 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19966 21:47:09.328 0.00067042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19967 21:47:09.328 0.00052425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19968 21:47:09.328 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19969 21:47:09.328 0.00031012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19970 21:47:09.328 0.00043773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19971 21:47:09.328 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19972 21:47:09.328 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19973 21:47:09.328 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19974 21:47:09.328 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19975 21:47:09.328 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19976 21:47:09.328 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19977 21:47:09.328 0.00035793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19978 21:47:09.328 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19979 21:47:09.328 0.00028247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19980 21:47:09.328 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19981 21:47:09.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19982 21:47:09.328 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19983 21:47:09.328 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19984 21:47:09.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19985 21:47:09.328 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19986 21:47:09.328 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19987 21:47:09.328 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19988 21:47:09.328 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19989 21:47:09.328 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19990 21:47:09.328 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 19991 21:47:09.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19992 21:47:09.328 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19993 21:47:09.328 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19994 21:47:09.328 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19995 21:47:09.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19996 21:47:09.328 0.02608238 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19997 21:47:09.360 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 19998 21:47:09.360 0.01434628 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 19999 21:47:09.360 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20000 21:47:09.375 0.00031881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20001 21:47:09.375 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20002 21:47:09.375 0.00029077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20003 21:47:09.375 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20004 21:47:09.375 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20005 21:47:09.375 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20006 21:47:09.375 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20007 21:47:09.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20008 21:47:09.375 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20009 21:47:09.375 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 20010 21:47:09.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20011 21:47:09.375 0.00036899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20012 21:47:09.375 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20013 21:47:09.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20014 21:47:09.375 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20015 21:47:09.375 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20016 21:47:09.375 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20017 21:47:09.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20018 21:47:09.375 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20019 21:47:09.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20020 21:47:09.375 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20021 21:47:09.375 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20022 21:47:09.375 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20023 21:47:09.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20024 21:47:09.375 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20025 21:47:09.375 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20026 21:47:09.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20027 21:47:09.375 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20028 21:47:09.375 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20029 21:47:09.375 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20030 21:47:09.375 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20031 21:47:09.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20032 21:47:09.375 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20033 21:47:09.375 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20034 21:47:09.375 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20035 21:47:09.375 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20036 21:47:09.375 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20037 21:47:09.375 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20038 21:47:09.375 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20040 21:47:09.375 0.00008612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20041 21:47:09.375 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20042 21:47:09.375 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20043 21:47:09.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20044 21:47:09.375 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20045 21:47:09.375 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20046 21:47:09.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20047 21:47:09.375 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20048 21:47:09.375 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20049 21:47:09.375 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20050 21:47:09.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20051 21:47:09.375 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20052 21:47:09.375 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20053 21:47:09.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20054 21:47:09.375 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20055 21:47:09.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20056 21:47:09.375 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20057 21:47:09.375 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20058 21:47:09.375 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20059 21:47:09.375 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20060 21:47:09.375 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20061 21:47:09.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20062 21:47:09.375 0.02672317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20063 21:47:09.407 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20064 21:47:09.407 0.01400297 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20065 21:47:09.407 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20066 21:47:09.422 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20067 21:47:09.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20068 21:47:09.422 0.00022756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20069 21:47:09.422 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20070 21:47:09.422 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20071 21:47:09.422 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20072 21:47:09.422 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20073 21:47:09.422 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20074 21:47:09.422 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20075 21:47:09.422 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 20076 21:47:09.422 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20077 21:47:09.422 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20078 21:47:09.422 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20079 21:47:09.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20080 21:47:09.422 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20081 21:47:09.422 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20082 21:47:09.422 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20083 21:47:09.422 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20084 21:47:09.422 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20085 21:47:09.422 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20086 21:47:09.422 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20087 21:47:09.422 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20088 21:47:09.422 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20089 21:47:09.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20090 21:47:09.422 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20091 21:47:09.422 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20092 21:47:09.422 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20093 21:47:09.422 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20094 21:47:09.422 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20095 21:47:09.422 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20096 21:47:09.422 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20097 21:47:09.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20098 21:47:09.422 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20099 21:47:09.422 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20100 21:47:09.422 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20101 21:47:09.422 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20102 21:47:09.422 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20103 21:47:09.422 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20104 21:47:09.422 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20105 21:47:09.422 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20106 21:47:09.422 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20107 21:47:09.422 0.00026785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20108 21:47:09.422 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20109 21:47:09.422 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20110 21:47:09.422 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20111 21:47:09.422 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20112 21:47:09.422 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20113 21:47:09.422 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20114 21:47:09.422 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20115 21:47:09.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20116 21:47:09.422 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20117 21:47:09.422 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20118 21:47:09.422 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20119 21:47:09.422 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20120 21:47:09.422 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20121 21:47:09.422 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20122 21:47:09.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20123 21:47:09.422 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20124 21:47:09.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20125 21:47:09.422 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20126 21:47:09.422 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20127 21:47:09.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20128 21:47:09.422 0.02770095 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20129 21:47:09.453 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20130 21:47:09.453 0.01377265 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20131 21:47:09.453 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20132 21:47:09.469 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20133 21:47:09.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20134 21:47:09.469 0.00030578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20135 21:47:09.469 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20136 21:47:09.469 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20137 21:47:09.469 0.00020385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20138 21:47:09.469 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20139 21:47:09.469 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 20140 21:47:09.469 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20141 21:47:09.469 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20142 21:47:09.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20143 21:47:09.469 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20144 21:47:09.469 0.00024217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20145 21:47:09.469 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20146 21:47:09.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20147 21:47:09.469 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20148 21:47:09.469 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20149 21:47:09.469 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20150 21:47:09.469 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20151 21:47:09.469 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20152 21:47:09.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20153 21:47:09.469 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20154 21:47:09.469 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20155 21:47:09.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20156 21:47:09.469 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20157 21:47:09.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20158 21:47:09.469 0.00025086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20159 21:47:09.469 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20160 21:47:09.469 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20161 21:47:09.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20162 21:47:09.469 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20163 21:47:09.469 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20164 21:47:09.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20165 21:47:09.469 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20166 21:47:09.469 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20167 21:47:09.469 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20168 21:47:09.469 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20169 21:47:09.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20170 21:47:09.469 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20171 21:47:09.469 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20172 21:47:09.469 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20173 21:47:09.469 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20174 21:47:09.469 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20175 21:47:09.469 0.00031684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20176 21:47:09.469 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20177 21:47:09.469 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20178 21:47:09.469 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20179 21:47:09.469 0.00029195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20181 21:47:09.469 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20182 21:47:09.469 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20183 21:47:09.469 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20184 21:47:09.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20185 21:47:09.469 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20186 21:47:09.469 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20187 21:47:09.469 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20188 21:47:09.469 0.00017817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20189 21:47:09.469 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20190 21:47:09.469 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20191 21:47:09.469 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20192 21:47:09.469 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20193 21:47:09.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20194 21:47:09.469 0.02791942 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20195 21:47:09.500 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20196 21:47:09.500 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20197 21:47:09.500 0.01309986 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20198 21:47:09.516 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20199 21:47:09.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20200 21:47:09.516 0.00027931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20201 21:47:09.516 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20202 21:47:09.516 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20203 21:47:09.516 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20204 21:47:09.516 0.00023032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20205 21:47:09.516 0.00034252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20206 21:47:09.516 0.00029867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 20207 21:47:09.516 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20208 21:47:09.516 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20209 21:47:09.516 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20210 21:47:09.516 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20211 21:47:09.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20212 21:47:09.516 0.00032040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20213 21:47:09.516 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20214 21:47:09.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20215 21:47:09.516 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20216 21:47:09.516 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20217 21:47:09.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20218 21:47:09.516 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20219 21:47:09.516 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20220 21:47:09.516 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20221 21:47:09.516 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20222 21:47:09.516 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20223 21:47:09.516 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20224 21:47:09.516 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20225 21:47:09.516 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20226 21:47:09.516 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20227 21:47:09.516 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20228 21:47:09.516 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20229 21:47:09.516 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20230 21:47:09.516 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20231 21:47:09.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20232 21:47:09.516 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20233 21:47:09.516 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20234 21:47:09.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20235 21:47:09.516 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20236 21:47:09.516 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20237 21:47:09.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20238 21:47:09.516 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20239 21:47:09.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20240 21:47:09.516 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20241 21:47:09.516 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20242 21:47:09.516 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20243 21:47:09.516 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20244 21:47:09.516 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20245 21:47:09.516 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20246 21:47:09.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20247 21:47:09.516 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20248 21:47:09.516 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20249 21:47:09.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20250 21:47:09.516 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20251 21:47:09.516 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20252 21:47:09.516 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20253 21:47:09.516 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20254 21:47:09.516 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20255 21:47:09.516 0.00024454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20256 21:47:09.516 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20257 21:47:09.516 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20258 21:47:09.516 0.02713443 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20259 21:47:09.548 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20260 21:47:09.548 0.01350163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20261 21:47:09.548 0.00000593 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20262 21:47:09.563 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20263 21:47:09.563 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20264 21:47:09.563 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 20265 21:47:09.563 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 58 20268 21:47:09.563 0.00031961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20269 21:47:09.563 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 20270 21:47:09.563 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20271 21:47:09.563 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20272 21:47:09.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20273 21:47:09.563 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20274 21:47:09.563 0.00030064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20275 21:47:09.563 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20276 21:47:09.563 0.00066884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20277 21:47:09.563 0.00059536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20278 21:47:09.563 0.00049896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20279 21:47:09.563 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20280 21:47:09.563 0.00042469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20281 21:47:09.563 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20282 21:47:09.563 0.00030736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20283 21:47:09.563 0.00040415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20284 21:47:09.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20285 21:47:09.563 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20286 21:47:09.563 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20287 21:47:09.563 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20288 21:47:09.563 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20289 21:47:09.563 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20290 21:47:09.563 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20291 21:47:09.563 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20292 21:47:09.563 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20293 21:47:09.563 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20294 21:47:09.563 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20295 21:47:09.563 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20296 21:47:09.563 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20297 21:47:09.563 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20298 21:47:09.563 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20299 21:47:09.563 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20300 21:47:09.563 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20301 21:47:09.563 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20302 21:47:09.563 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20303 21:47:09.563 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20304 21:47:09.563 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20305 21:47:09.563 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20306 21:47:09.563 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20307 21:47:09.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20308 21:47:09.563 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20309 21:47:09.563 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20310 21:47:09.563 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20311 21:47:09.563 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20312 21:47:09.563 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20313 21:47:09.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20314 21:47:09.563 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20315 21:47:09.563 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20316 21:47:09.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20317 21:47:09.563 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20318 21:47:09.563 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20319 21:47:09.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20320 21:47:09.563 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20321 21:47:09.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20322 21:47:09.563 0.02613492 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20323 21:47:09.594 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20324 21:47:09.594 0.01229275 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20325 21:47:09.594 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20326 21:47:09.609 0.00030104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20327 21:47:09.609 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20328 21:47:09.609 0.00027536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20329 21:47:09.609 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20330 21:47:09.609 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20331 21:47:09.609 0.00044286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20332 21:47:09.609 0.00038637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20333 21:47:09.609 0.00033936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 20334 21:47:09.609 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20335 21:47:09.609 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20336 21:47:09.609 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20337 21:47:09.609 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20338 21:47:09.609 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20339 21:47:09.609 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20340 21:47:09.609 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20341 21:47:09.609 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20342 21:47:09.609 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20343 21:47:09.609 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20344 21:47:09.609 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20345 21:47:09.609 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20346 21:47:09.609 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20347 21:47:09.609 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20348 21:47:09.609 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20349 21:47:09.609 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20350 21:47:09.609 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20351 21:47:09.609 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20352 21:47:09.609 0.00046696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20353 21:47:09.609 0.00029906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20354 21:47:09.609 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20355 21:47:09.609 0.00021373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20356 21:47:09.609 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20357 21:47:09.609 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20358 21:47:09.609 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20359 21:47:09.609 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20360 21:47:09.609 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20361 21:47:09.609 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20362 21:47:09.609 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20363 21:47:09.609 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20364 21:47:09.609 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20365 21:47:09.609 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20366 21:47:09.609 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20367 21:47:09.609 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20368 21:47:09.609 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20369 21:47:09.609 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20370 21:47:09.609 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20371 21:47:09.609 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20372 21:47:09.609 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20373 21:47:09.609 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20374 21:47:09.609 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20375 21:47:09.609 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20376 21:47:09.609 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20377 21:47:09.609 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20378 21:47:09.609 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20379 21:47:09.609 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20381 21:47:09.609 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20382 21:47:09.609 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20383 21:47:09.609 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20384 21:47:09.609 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20385 21:47:09.609 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20386 21:47:09.609 0.02714470 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20387 21:47:09.641 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20388 21:47:09.641 0.01324603 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20389 21:47:09.641 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20390 21:47:09.656 0.00036227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20391 21:47:09.656 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20392 21:47:09.656 0.00035477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20393 21:47:09.656 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20394 21:47:09.656 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20395 21:47:09.656 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20396 21:47:09.656 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20397 21:47:09.656 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 20398 21:47:09.656 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20399 21:47:09.656 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20400 21:47:09.656 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20401 21:47:09.656 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20402 21:47:09.656 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20403 21:47:09.656 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20404 21:47:09.656 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20405 21:47:09.656 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20406 21:47:09.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20407 21:47:09.656 0.00021294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20408 21:47:09.656 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20409 21:47:09.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20410 21:47:09.656 0.00030104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20411 21:47:09.656 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20412 21:47:09.656 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20413 21:47:09.656 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20414 21:47:09.656 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20415 21:47:09.656 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20416 21:47:09.656 0.00029116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20417 21:47:09.656 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20418 21:47:09.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20419 21:47:09.656 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20420 21:47:09.656 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20421 21:47:09.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20422 21:47:09.656 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20423 21:47:09.656 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20424 21:47:09.656 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20425 21:47:09.656 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20426 21:47:09.656 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20427 21:47:09.656 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20428 21:47:09.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20429 21:47:09.656 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20430 21:47:09.656 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20431 21:47:09.656 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20432 21:47:09.656 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20433 21:47:09.656 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20434 21:47:09.656 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20435 21:47:09.656 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20436 21:47:09.656 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20437 21:47:09.656 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20438 21:47:09.656 0.00011141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20439 21:47:09.656 0.00016830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20440 21:47:09.656 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20441 21:47:09.656 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20442 21:47:09.656 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20443 21:47:09.656 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20444 21:47:09.656 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20445 21:47:09.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20446 21:47:09.656 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20447 21:47:09.656 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20448 21:47:09.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20449 21:47:09.656 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20450 21:47:09.656 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20451 21:47:09.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20452 21:47:09.656 0.02608317 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20453 21:47:09.688 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20454 21:47:09.688 0.01399033 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20455 21:47:09.688 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20456 21:47:09.703 0.00039546 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20457 21:47:09.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20458 21:47:09.703 0.00037057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20459 21:47:09.703 0.00028879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20460 21:47:09.703 0.00044642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20461 21:47:09.703 0.00029432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20462 21:47:09.703 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20463 21:47:09.703 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20464 21:47:09.703 0.00038677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20466 21:47:09.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20467 21:47:09.703 0.00036306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20468 21:47:09.703 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20469 21:47:09.703 0.00031012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20470 21:47:09.703 0.00060207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20471 21:47:09.703 0.00020622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20472 21:47:09.703 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20473 21:47:09.703 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20474 21:47:09.703 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20475 21:47:09.703 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20476 21:47:09.703 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20477 21:47:09.703 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20478 21:47:09.703 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20479 21:47:09.703 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20480 21:47:09.703 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20481 21:47:09.703 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20482 21:47:09.703 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20483 21:47:09.703 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20484 21:47:09.703 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20485 21:47:09.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20486 21:47:09.703 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20487 21:47:09.703 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20488 21:47:09.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20489 21:47:09.703 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20490 21:47:09.703 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20491 21:47:09.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20492 21:47:09.703 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20493 21:47:09.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20494 21:47:09.703 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20495 21:47:09.703 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20496 21:47:09.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20497 21:47:09.703 0.00031249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20498 21:47:09.703 0.00032119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20499 21:47:09.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20500 21:47:09.703 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20501 21:47:09.703 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20502 21:47:09.703 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20503 21:47:09.703 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20504 21:47:09.703 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20505 21:47:09.703 0.00026825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20506 21:47:09.703 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20507 21:47:09.703 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20508 21:47:09.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20509 21:47:09.703 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20510 21:47:09.703 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20511 21:47:09.703 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20512 21:47:09.703 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20513 21:47:09.703 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20514 21:47:09.703 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20515 21:47:09.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20516 21:47:09.703 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20517 21:47:09.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20518 21:47:09.703 0.02514529 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20519 21:47:09.735 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20520 21:47:09.735 0.01420603 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20521 21:47:09.735 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20522 21:47:09.750 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20523 21:47:09.750 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20524 21:47:09.750 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20525 21:47:09.750 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20526 21:47:09.750 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20527 21:47:09.750 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20528 21:47:09.750 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20529 21:47:09.750 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20530 21:47:09.750 0.00029630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 20531 21:47:09.750 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20532 21:47:09.750 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20533 21:47:09.750 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20534 21:47:09.750 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20535 21:47:09.750 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20536 21:47:09.750 0.00031565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20537 21:47:09.750 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20538 21:47:09.750 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20539 21:47:09.750 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20540 21:47:09.750 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20541 21:47:09.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20542 21:47:09.750 0.00024454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20543 21:47:09.750 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20544 21:47:09.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20545 21:47:09.750 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20546 21:47:09.750 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20547 21:47:09.750 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20548 21:47:09.750 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20549 21:47:09.750 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20550 21:47:09.750 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20551 21:47:09.750 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20552 21:47:09.750 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20553 21:47:09.750 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20554 21:47:09.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20555 21:47:09.750 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20556 21:47:09.750 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20557 21:47:09.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20558 21:47:09.750 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20559 21:47:09.750 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20560 21:47:09.750 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20561 21:47:09.750 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20562 21:47:09.750 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20563 21:47:09.750 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20564 21:47:09.750 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20565 21:47:09.750 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20566 21:47:09.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20567 21:47:09.750 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20568 21:47:09.750 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20569 21:47:09.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20570 21:47:09.750 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20574 21:47:09.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20575 21:47:09.750 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20576 21:47:09.750 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20577 21:47:09.750 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20578 21:47:09.750 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20579 21:47:09.750 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20580 21:47:09.750 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20581 21:47:09.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20582 21:47:09.750 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20583 21:47:09.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20584 21:47:09.750 0.02736080 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20585 21:47:09.782 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20586 21:47:09.782 0.01349294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20587 21:47:09.782 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20588 21:47:09.797 0.00031052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20589 21:47:09.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20590 21:47:09.797 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20591 21:47:09.797 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20592 21:47:09.797 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20593 21:47:09.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20594 21:47:09.797 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20595 21:47:09.797 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20596 21:47:09.797 0.00032672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20597 21:47:09.797 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 20598 21:47:09.797 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20599 21:47:09.797 0.00028958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20600 21:47:09.797 0.00037412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20601 21:47:09.797 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20602 21:47:09.797 0.00040533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20603 21:47:09.797 0.00044247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20604 21:47:09.797 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20605 21:47:09.797 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20606 21:47:09.797 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20607 21:47:09.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20608 21:47:09.797 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20609 21:47:09.797 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20610 21:47:09.797 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20611 21:47:09.797 0.00026548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20612 21:47:09.797 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20613 21:47:09.797 0.00032790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20614 21:47:09.797 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20615 21:47:09.797 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20616 21:47:09.797 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20617 21:47:09.797 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20618 21:47:09.797 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20619 21:47:09.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20620 21:47:09.797 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20621 21:47:09.797 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20622 21:47:09.797 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20623 21:47:09.797 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20624 21:47:09.797 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20625 21:47:09.797 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20626 21:47:09.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20627 21:47:09.797 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20628 21:47:09.797 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20629 21:47:09.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20630 21:47:09.797 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20631 21:47:09.797 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20632 21:47:09.797 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20633 21:47:09.797 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20634 21:47:09.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20635 21:47:09.797 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20636 21:47:09.797 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20637 21:47:09.797 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20638 21:47:09.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20639 21:47:09.797 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20640 21:47:09.797 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20641 21:47:09.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20642 21:47:09.797 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20643 21:47:09.797 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20644 21:47:09.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20645 21:47:09.797 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20646 21:47:09.797 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20647 21:47:09.797 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20648 21:47:09.797 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20649 21:47:09.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20650 21:47:09.797 0.02661374 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20651 21:47:09.828 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20652 21:47:09.828 0.01353482 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20653 21:47:09.828 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20654 21:47:09.844 0.00031526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20655 21:47:09.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20656 21:47:09.844 0.00032435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20657 21:47:09.844 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20658 21:47:09.844 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20659 21:47:09.844 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20660 21:47:09.844 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20661 21:47:09.844 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20662 21:47:09.844 0.00025521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20664 21:47:09.844 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20665 21:47:09.844 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20666 21:47:09.844 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20667 21:47:09.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20668 21:47:09.844 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20669 21:47:09.844 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20670 21:47:09.844 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20671 21:47:09.844 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20672 21:47:09.844 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20673 21:47:09.844 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20674 21:47:09.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20675 21:47:09.844 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20676 21:47:09.844 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20677 21:47:09.844 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20678 21:47:09.844 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20679 21:47:09.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20680 21:47:09.844 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20681 21:47:09.844 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20682 21:47:09.844 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20683 21:47:09.844 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20684 21:47:09.844 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20685 21:47:09.844 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20686 21:47:09.844 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20687 21:47:09.844 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20688 21:47:09.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20689 21:47:09.844 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20690 21:47:09.844 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20691 21:47:09.844 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20692 21:47:09.844 0.00027773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20693 21:47:09.844 0.00022123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20694 21:47:09.844 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20695 21:47:09.844 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20696 21:47:09.844 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20697 21:47:09.844 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20698 21:47:09.844 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20699 21:47:09.844 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20700 21:47:09.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20701 21:47:09.844 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20702 21:47:09.844 0.00010351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20703 21:47:09.844 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20704 21:47:09.844 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20705 21:47:09.844 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20706 21:47:09.844 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20707 21:47:09.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20708 21:47:09.844 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20710 21:47:09.844 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20711 21:47:09.844 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20712 21:47:09.844 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20713 21:47:09.844 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20714 21:47:09.844 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20715 21:47:09.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20716 21:47:09.844 0.02703764 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20717 21:47:09.875 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20718 21:47:09.875 0.00006637 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20719 21:47:09.875 0.01307813 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20720 21:47:09.891 0.00035951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20721 21:47:09.891 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20722 21:47:09.891 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20723 21:47:09.891 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20724 21:47:09.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20725 21:47:09.891 0.00028563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20726 21:47:09.891 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20727 21:47:09.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20728 21:47:09.891 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20729 21:47:09.891 0.00024138 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 20730 21:47:09.891 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20731 21:47:09.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20732 21:47:09.891 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20733 21:47:09.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20734 21:47:09.891 0.00043417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20735 21:47:09.891 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20736 21:47:09.891 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20737 21:47:09.891 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20738 21:47:09.891 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20739 21:47:09.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20740 21:47:09.891 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20741 21:47:09.891 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20742 21:47:09.891 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20743 21:47:09.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20744 21:47:09.891 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20745 21:47:09.891 0.00037294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20746 21:47:09.891 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20747 21:47:09.891 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20748 21:47:09.891 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20749 21:47:09.891 0.00032948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20750 21:47:09.891 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20751 21:47:09.891 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20752 21:47:09.891 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20753 21:47:09.891 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20754 21:47:09.891 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20755 21:47:09.891 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20756 21:47:09.891 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20757 21:47:09.891 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20758 21:47:09.891 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20759 21:47:09.891 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20760 21:47:09.891 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20761 21:47:09.891 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20762 21:47:09.891 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20763 21:47:09.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20764 21:47:09.891 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20765 21:47:09.891 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20766 21:47:09.891 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20767 21:47:09.891 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20768 21:47:09.891 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20769 21:47:09.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20770 21:47:09.891 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20771 21:47:09.891 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20772 21:47:09.891 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20773 21:47:09.891 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20774 21:47:09.891 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20775 21:47:09.891 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20776 21:47:09.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20777 21:47:09.891 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20778 21:47:09.891 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20779 21:47:09.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20780 21:47:09.891 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20781 21:47:09.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20782 21:47:09.891 0.02647033 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20783 21:47:09.922 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20784 21:47:09.922 0.01369601 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20785 21:47:09.922 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20786 21:47:09.938 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20787 21:47:09.938 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20788 21:47:09.938 0.00027101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20789 21:47:09.938 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20790 21:47:09.938 0.00082647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20791 21:47:09.938 0.00043891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20792 21:47:09.938 0.00030104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20793 21:47:09.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20794 21:47:09.938 0.00049501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 20796 21:47:09.938 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20797 21:47:09.938 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20798 21:47:09.938 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20799 21:47:09.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20800 21:47:09.938 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20801 21:47:09.938 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20802 21:47:09.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 20803 21:47:09.938 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20804 21:47:09.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 20808 21:47:09.938 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20809 21:47:09.938 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20810 21:47:09.938 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20811 21:47:09.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20812 21:47:09.938 0.00028563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20813 21:47:09.938 0.00020899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20814 21:47:09.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 20815 21:47:09.938 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20816 21:47:09.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 20819 21:47:09.938 0.00056138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20820 21:47:09.938 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20821 21:47:09.938 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20822 21:47:09.938 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20823 21:47:09.938 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20824 21:47:09.938 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20825 21:47:09.938 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20826 21:47:09.938 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20827 21:47:09.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20828 21:47:09.938 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20829 21:47:09.938 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20830 21:47:09.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20831 21:47:09.938 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20832 21:47:09.938 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20833 21:47:09.938 0.00030183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20834 21:47:09.938 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20835 21:47:09.938 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20836 21:47:09.938 0.00032435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20837 21:47:09.938 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20838 21:47:09.938 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20839 21:47:09.938 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20840 21:47:09.938 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20841 21:47:09.938 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20842 21:47:09.938 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20843 21:47:09.938 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20844 21:47:09.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20845 21:47:09.938 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20846 21:47:09.938 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20847 21:47:09.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20848 21:47:09.938 0.02470124 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20849 21:47:09.969 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20850 21:47:09.969 0.01437907 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20851 21:47:09.969 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20852 21:47:09.985 0.00037373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20853 21:47:09.985 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20854 21:47:09.985 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20855 21:47:09.985 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20856 21:47:09.985 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20857 21:47:09.985 0.00030973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20858 21:47:09.985 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20859 21:47:09.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20860 21:47:09.985 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20861 21:47:09.985 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 20862 21:47:09.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20863 21:47:09.985 0.00030538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20864 21:47:09.985 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20865 21:47:09.985 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20866 21:47:09.985 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20867 21:47:09.985 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20868 21:47:09.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20869 21:47:09.985 0.00040138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20870 21:47:09.985 0.00032395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20871 21:47:09.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20872 21:47:09.985 0.00027417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20873 21:47:09.985 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20874 21:47:09.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20875 21:47:09.985 0.00024454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20876 21:47:09.985 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20877 21:47:09.985 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20878 21:47:09.985 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20879 21:47:09.985 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20880 21:47:09.985 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20881 21:47:09.985 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20882 21:47:09.985 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20883 21:47:09.985 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20884 21:47:09.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20885 21:47:09.985 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20886 21:47:09.985 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20887 21:47:09.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20888 21:47:09.985 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20889 21:47:09.985 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20890 21:47:09.985 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20891 21:47:09.985 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20892 21:47:09.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20893 21:47:09.985 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20894 21:47:09.985 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20895 21:47:09.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20896 21:47:09.985 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20897 21:47:09.985 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20898 21:47:09.985 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20899 21:47:09.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20900 21:47:09.985 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20901 21:47:09.985 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20902 21:47:09.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20903 21:47:09.985 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20904 21:47:09.985 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20905 21:47:09.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20906 21:47:09.985 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20907 21:47:09.985 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20908 21:47:09.985 0.00037886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20909 21:47:09.985 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20910 21:47:09.985 0.00030262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20911 21:47:09.985 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20912 21:47:09.985 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20913 21:47:09.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20915 21:47:10.016 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20916 21:47:10.016 0.02849186 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20917 21:47:10.016 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20918 21:47:10.047 0.00033106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20919 21:47:10.047 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20920 21:47:10.047 0.00029748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20921 21:47:10.047 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20922 21:47:10.047 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20923 21:47:10.047 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 20924 21:47:10.047 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20925 21:47:10.047 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20926 21:47:10.047 0.00029867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20927 21:47:10.047 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 20928 21:47:10.047 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20929 21:47:10.047 0.00034252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20930 21:47:10.047 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20931 21:47:10.047 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20932 21:47:10.047 0.00034449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20933 21:47:10.047 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20934 21:47:10.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20935 21:47:10.047 0.00033620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20936 21:47:10.047 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20937 21:47:10.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20938 21:47:10.047 0.00033067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20939 21:47:10.047 0.00027773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20940 21:47:10.047 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20941 21:47:10.047 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20942 21:47:10.047 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20943 21:47:10.047 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20944 21:47:10.047 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20945 21:47:10.047 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20946 21:47:10.047 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20947 21:47:10.047 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20948 21:47:10.047 0.00023151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20949 21:47:10.047 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 20951 21:47:10.047 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20952 21:47:10.047 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20953 21:47:10.047 0.00026430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20954 21:47:10.047 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20955 21:47:10.047 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20956 21:47:10.047 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20957 21:47:10.047 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20958 21:47:10.047 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20959 21:47:10.047 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20960 21:47:10.047 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20961 21:47:10.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20962 21:47:10.047 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20963 21:47:10.047 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20964 21:47:10.047 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20965 21:47:10.047 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20966 21:47:10.047 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20967 21:47:10.047 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20968 21:47:10.047 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20969 21:47:10.047 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20970 21:47:10.047 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20971 21:47:10.047 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20972 21:47:10.047 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20973 21:47:10.047 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20974 21:47:10.047 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20975 21:47:10.047 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20976 21:47:10.047 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20977 21:47:10.047 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20978 21:47:10.047 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20979 21:47:10.047 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20980 21:47:10.047 0.02454401 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20981 21:47:10.078 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20982 21:47:10.078 0.01453472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20983 21:47:10.078 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 20984 21:47:10.094 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 20985 21:47:10.094 0.00036820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20986 21:47:10.094 0.00041007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 20987 21:47:10.094 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20988 21:47:10.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20989 21:47:10.094 0.00028484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20990 21:47:10.094 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 20991 21:47:10.094 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 20992 21:47:10.094 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20993 21:47:10.094 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20994 21:47:10.094 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 20995 21:47:10.094 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20996 21:47:10.094 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 20997 21:47:10.094 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 20998 21:47:10.094 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20999 21:47:10.094 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21000 21:47:10.094 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21001 21:47:10.094 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21002 21:47:10.094 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21003 21:47:10.094 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21004 21:47:10.094 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21005 21:47:10.094 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21006 21:47:10.094 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21007 21:47:10.094 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21008 21:47:10.094 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21009 21:47:10.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21010 21:47:10.094 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21011 21:47:10.094 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21012 21:47:10.094 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21013 21:47:10.094 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21014 21:47:10.094 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21015 21:47:10.094 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21016 21:47:10.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21017 21:47:10.094 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21018 21:47:10.094 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21019 21:47:10.094 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21020 21:47:10.094 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21021 21:47:10.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21022 21:47:10.094 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21023 21:47:10.094 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21024 21:47:10.094 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21025 21:47:10.094 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21026 21:47:10.094 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21027 21:47:10.094 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21028 21:47:10.094 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21029 21:47:10.094 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21030 21:47:10.094 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21031 21:47:10.094 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21032 21:47:10.094 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21033 21:47:10.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21034 21:47:10.094 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21035 21:47:10.094 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21036 21:47:10.094 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21037 21:47:10.094 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21038 21:47:10.094 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21039 21:47:10.094 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21040 21:47:10.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21041 21:47:10.094 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21042 21:47:10.094 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21043 21:47:10.094 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21044 21:47:10.094 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21045 21:47:10.094 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21046 21:47:10.094 0.02782342 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21047 21:47:10.125 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21048 21:47:10.125 0.01365018 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21049 21:47:10.125 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21050 21:47:10.141 0.00036899 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21051 21:47:10.141 0.00034054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21052 21:47:10.141 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21053 21:47:10.141 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21054 21:47:10.141 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21055 21:47:10.141 0.00042232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21056 21:47:10.141 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 21057 21:47:10.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21058 21:47:10.141 0.00032553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21059 21:47:10.141 0.00023151 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 21060 21:47:10.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21061 21:47:10.141 0.00033106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21062 21:47:10.141 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21063 21:47:10.141 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21064 21:47:10.141 0.00028879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21065 21:47:10.141 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21066 21:47:10.141 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21067 21:47:10.141 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21068 21:47:10.141 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21069 21:47:10.141 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21070 21:47:10.141 0.00036346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21071 21:47:10.141 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21072 21:47:10.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21073 21:47:10.141 0.00028998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21074 21:47:10.141 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21075 21:47:10.141 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21076 21:47:10.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21077 21:47:10.141 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21078 21:47:10.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21079 21:47:10.141 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21080 21:47:10.141 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21081 21:47:10.141 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21082 21:47:10.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21083 21:47:10.141 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21084 21:47:10.141 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21085 21:47:10.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21086 21:47:10.141 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21087 21:47:10.141 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21088 21:47:10.141 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21089 21:47:10.141 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21090 21:47:10.141 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21091 21:47:10.141 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21092 21:47:10.141 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21093 21:47:10.141 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21094 21:47:10.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21095 21:47:10.141 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21096 21:47:10.141 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21097 21:47:10.141 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21098 21:47:10.141 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21099 21:47:10.141 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21100 21:47:10.141 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21101 21:47:10.141 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21102 21:47:10.141 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21103 21:47:10.141 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21104 21:47:10.141 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21105 21:47:10.141 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21106 21:47:10.141 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21107 21:47:10.141 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21108 21:47:10.141 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21109 21:47:10.141 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21110 21:47:10.141 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21111 21:47:10.141 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21112 21:47:10.141 0.02620208 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21113 21:47:10.172 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21114 21:47:10.172 0.01290944 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21115 21:47:10.172 0.00000356 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21116 21:47:10.188 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21117 21:47:10.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21118 21:47:10.188 0.00030341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21119 21:47:10.188 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21120 21:47:10.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21121 21:47:10.188 0.00027417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21122 21:47:10.188 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 21123 21:47:10.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21124 21:47:10.188 0.00038281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21125 21:47:10.188 0.00029985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 21126 21:47:10.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21127 21:47:10.188 0.00028998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21128 21:47:10.188 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21129 21:47:10.188 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21130 21:47:10.188 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21131 21:47:10.188 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21132 21:47:10.188 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21133 21:47:10.188 0.00021412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21134 21:47:10.188 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21135 21:47:10.188 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21136 21:47:10.188 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21137 21:47:10.188 0.00030775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21138 21:47:10.188 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21139 21:47:10.188 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21140 21:47:10.188 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21141 21:47:10.188 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21142 21:47:10.188 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21143 21:47:10.188 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21144 21:47:10.188 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21145 21:47:10.188 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21146 21:47:10.188 0.00027536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21147 21:47:10.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21148 21:47:10.188 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21149 21:47:10.188 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21150 21:47:10.188 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21151 21:47:10.188 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21152 21:47:10.188 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21153 21:47:10.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21154 21:47:10.188 0.00027180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21155 21:47:10.188 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21156 21:47:10.188 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 21157 21:47:10.188 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21159 21:47:10.188 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21160 21:47:10.188 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21161 21:47:10.188 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21162 21:47:10.188 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21163 21:47:10.188 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21164 21:47:10.188 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21165 21:47:10.188 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21166 21:47:10.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21167 21:47:10.188 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21168 21:47:10.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21169 21:47:10.188 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21170 21:47:10.188 0.00019477 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21171 21:47:10.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21172 21:47:10.188 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21173 21:47:10.188 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21174 21:47:10.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21175 21:47:10.188 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21176 21:47:10.188 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21177 21:47:10.188 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21178 21:47:10.188 0.02718302 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21179 21:47:10.219 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21180 21:47:10.219 0.01293354 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21181 21:47:10.219 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21182 21:47:10.235 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21183 21:47:10.235 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21184 21:47:10.235 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21185 21:47:10.235 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21186 21:47:10.235 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 21187 21:47:10.235 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21188 21:47:10.235 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21189 21:47:10.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21190 21:47:10.235 0.00035358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21191 21:47:10.235 0.00026785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 21192 21:47:10.235 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21193 21:47:10.235 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21194 21:47:10.235 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21195 21:47:10.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21196 21:47:10.235 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21197 21:47:10.235 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21198 21:47:10.235 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21199 21:47:10.235 0.00011101 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21200 21:47:10.235 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21201 21:47:10.235 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21202 21:47:10.235 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21203 21:47:10.235 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21204 21:47:10.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21205 21:47:10.235 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21206 21:47:10.235 0.00027299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21207 21:47:10.235 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21208 21:47:10.235 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21209 21:47:10.235 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21210 21:47:10.235 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21211 21:47:10.235 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21212 21:47:10.235 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21213 21:47:10.235 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21214 21:47:10.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21215 21:47:10.235 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21216 21:47:10.235 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21217 21:47:10.235 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21218 21:47:10.235 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21219 21:47:10.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21220 21:47:10.235 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21221 21:47:10.235 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21222 21:47:10.235 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21223 21:47:10.235 0.00033383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21224 21:47:10.235 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21225 21:47:10.235 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21226 21:47:10.235 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21227 21:47:10.235 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21228 21:47:10.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21229 21:47:10.235 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21230 21:47:10.235 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21231 21:47:10.235 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21232 21:47:10.235 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21233 21:47:10.235 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21234 21:47:10.235 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21235 21:47:10.235 0.00032474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21236 21:47:10.235 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21237 21:47:10.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21238 21:47:10.235 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21239 21:47:10.235 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21240 21:47:10.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21241 21:47:10.235 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21242 21:47:10.235 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21243 21:47:10.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21244 21:47:10.235 0.02652485 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21245 21:47:10.266 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21246 21:47:10.266 0.01445294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21247 21:47:10.266 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21248 21:47:10.282 0.00043457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21249 21:47:10.282 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21250 21:47:10.282 0.00038716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21251 21:47:10.282 0.00028286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21252 21:47:10.282 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 19 21253 21:47:10.282 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21254 21:47:10.282 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21255 21:47:10.282 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21256 21:47:10.282 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21257 21:47:10.282 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 21258 21:47:10.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21259 21:47:10.282 0.00035674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21260 21:47:10.282 0.00029393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21261 21:47:10.282 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21262 21:47:10.282 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21263 21:47:10.282 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21264 21:47:10.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21265 21:47:10.282 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21266 21:47:10.282 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21267 21:47:10.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21268 21:47:10.282 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21269 21:47:10.282 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21270 21:47:10.282 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21271 21:47:10.282 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21272 21:47:10.282 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21273 21:47:10.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21274 21:47:10.282 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21275 21:47:10.282 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21276 21:47:10.282 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21277 21:47:10.282 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21278 21:47:10.282 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21279 21:47:10.282 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21280 21:47:10.282 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21281 21:47:10.282 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21282 21:47:10.282 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21283 21:47:10.282 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21284 21:47:10.282 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21285 21:47:10.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21286 21:47:10.282 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21287 21:47:10.282 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21288 21:47:10.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21289 21:47:10.282 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21290 21:47:10.282 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21291 21:47:10.282 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21292 21:47:10.282 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21293 21:47:10.282 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21294 21:47:10.282 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21295 21:47:10.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21296 21:47:10.282 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21297 21:47:10.282 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21298 21:47:10.282 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21299 21:47:10.282 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21300 21:47:10.282 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21301 21:47:10.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21302 21:47:10.282 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21303 21:47:10.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21304 21:47:10.282 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21305 21:47:10.282 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21306 21:47:10.282 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21307 21:47:10.282 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21308 21:47:10.282 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21309 21:47:10.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21310 21:47:10.282 0.02773492 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21311 21:47:10.313 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21312 21:47:10.313 0.01277907 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21313 21:47:10.313 0.00001857 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21314 21:47:10.329 0.00033264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21315 21:47:10.329 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21316 21:47:10.329 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21317 21:47:10.329 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21318 21:47:10.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21319 21:47:10.329 0.00113975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21320 21:47:10.329 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 21321 21:47:10.329 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21322 21:47:10.329 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21323 21:47:10.329 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 21324 21:47:10.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21325 21:47:10.329 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21326 21:47:10.329 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21327 21:47:10.329 0.00022993 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21328 21:47:10.329 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21329 21:47:10.329 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21330 21:47:10.329 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21331 21:47:10.329 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21332 21:47:10.329 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21333 21:47:10.329 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21334 21:47:10.329 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21335 21:47:10.329 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21336 21:47:10.329 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21337 21:47:10.329 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21338 21:47:10.329 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21339 21:47:10.329 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21340 21:47:10.329 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21341 21:47:10.329 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21342 21:47:10.329 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21343 21:47:10.329 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21344 21:47:10.329 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21345 21:47:10.329 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21346 21:47:10.329 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21347 21:47:10.329 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21348 21:47:10.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21349 21:47:10.329 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21350 21:47:10.329 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21351 21:47:10.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21352 21:47:10.329 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21353 21:47:10.329 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21354 21:47:10.329 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21355 21:47:10.329 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21356 21:47:10.329 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21357 21:47:10.329 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21358 21:47:10.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21359 21:47:10.329 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21360 21:47:10.329 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21361 21:47:10.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21362 21:47:10.329 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21363 21:47:10.329 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21364 21:47:10.329 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21365 21:47:10.329 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21366 21:47:10.329 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21367 21:47:10.329 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21368 21:47:10.329 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21369 21:47:10.329 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21370 21:47:10.329 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21371 21:47:10.329 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21372 21:47:10.329 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 21373 21:47:10.329 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21374 21:47:10.329 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 21377 21:47:10.360 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21378 21:47:10.360 0.01375526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21379 21:47:10.360 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21380 21:47:10.376 0.00028721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21381 21:47:10.376 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21382 21:47:10.376 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21383 21:47:10.376 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21384 21:47:10.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21385 21:47:10.376 0.00034568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21386 21:47:10.376 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 21387 21:47:10.376 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 21388 21:47:10.376 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21389 21:47:10.376 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21390 21:47:10.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21391 21:47:10.376 0.00032909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21392 21:47:10.376 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21393 21:47:10.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21394 21:47:10.376 0.00038163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21395 21:47:10.376 0.00032158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21396 21:47:10.376 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21397 21:47:10.376 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21398 21:47:10.376 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21399 21:47:10.376 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21400 21:47:10.376 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21401 21:47:10.376 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21402 21:47:10.376 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21403 21:47:10.376 0.00037452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21404 21:47:10.376 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21405 21:47:10.376 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21406 21:47:10.376 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21407 21:47:10.376 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21408 21:47:10.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21409 21:47:10.376 0.00030380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21410 21:47:10.376 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21411 21:47:10.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21412 21:47:10.376 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21413 21:47:10.376 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21414 21:47:10.376 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21415 21:47:10.376 0.00033896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21416 21:47:10.376 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21417 21:47:10.376 0.00008178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21418 21:47:10.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21419 21:47:10.376 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21420 21:47:10.376 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21421 21:47:10.376 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21422 21:47:10.376 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21423 21:47:10.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21424 21:47:10.376 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21425 21:47:10.376 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21426 21:47:10.376 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21427 21:47:10.376 0.00024217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21428 21:47:10.376 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21429 21:47:10.376 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21430 21:47:10.376 0.00027299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21431 21:47:10.376 0.00029788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21432 21:47:10.376 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21433 21:47:10.376 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21434 21:47:10.376 0.00026351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21435 21:47:10.376 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21436 21:47:10.376 0.00035240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21437 21:47:10.376 0.00026193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21438 21:47:10.376 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21439 21:47:10.376 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21440 21:47:10.376 0.00028761 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21441 21:47:10.376 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21442 21:47:10.376 0.02437295 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21443 21:47:10.406 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21444 21:47:10.406 0.01407052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21445 21:47:10.406 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21446 21:47:10.422 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21447 21:47:10.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21448 21:47:10.422 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21449 21:47:10.422 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21450 21:47:10.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21451 21:47:10.422 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21452 21:47:10.422 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 21453 21:47:10.422 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21454 21:47:10.422 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21455 21:47:10.422 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21456 21:47:10.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21457 21:47:10.422 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21458 21:47:10.422 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21459 21:47:10.422 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21460 21:47:10.422 0.00027496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21461 21:47:10.422 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21462 21:47:10.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21463 21:47:10.422 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21464 21:47:10.422 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21465 21:47:10.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21466 21:47:10.422 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21467 21:47:10.422 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21468 21:47:10.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21469 21:47:10.422 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21470 21:47:10.422 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21471 21:47:10.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21472 21:47:10.422 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21473 21:47:10.422 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21474 21:47:10.422 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21475 21:47:10.422 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21476 21:47:10.422 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21477 21:47:10.422 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21478 21:47:10.422 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21479 21:47:10.422 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21480 21:47:10.422 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21481 21:47:10.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21482 21:47:10.422 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21483 21:47:10.422 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21484 21:47:10.422 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21485 21:47:10.422 0.00017975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21486 21:47:10.422 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21487 21:47:10.422 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21488 21:47:10.422 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21489 21:47:10.422 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21490 21:47:10.422 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21491 21:47:10.422 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21492 21:47:10.422 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21493 21:47:10.422 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21494 21:47:10.422 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21495 21:47:10.422 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21496 21:47:10.422 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21497 21:47:10.422 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21498 21:47:10.422 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21499 21:47:10.422 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21500 21:47:10.422 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21501 21:47:10.422 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21502 21:47:10.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21503 21:47:10.422 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21504 21:47:10.422 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21505 21:47:10.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21506 21:47:10.422 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21507 21:47:10.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21508 21:47:10.422 0.02678401 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21509 21:47:10.453 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21510 21:47:10.453 0.01466193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21511 21:47:10.453 0.00001817 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21512 21:47:10.469 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21513 21:47:10.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21514 21:47:10.469 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21515 21:47:10.469 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21516 21:47:10.469 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21517 21:47:10.469 0.00033383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21518 21:47:10.469 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 21519 21:47:10.469 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21520 21:47:10.469 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21521 21:47:10.469 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21522 21:47:10.469 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21523 21:47:10.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21524 21:47:10.469 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21525 21:47:10.469 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21526 21:47:10.469 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21527 21:47:10.469 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21528 21:47:10.469 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21529 21:47:10.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21530 21:47:10.469 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21531 21:47:10.469 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21532 21:47:10.469 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21533 21:47:10.469 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21534 21:47:10.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21535 21:47:10.469 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21536 21:47:10.469 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21537 21:47:10.469 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21538 21:47:10.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21539 21:47:10.469 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21540 21:47:10.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21541 21:47:10.469 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21542 21:47:10.469 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21543 21:47:10.469 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21544 21:47:10.469 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21545 21:47:10.469 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21546 21:47:10.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21547 21:47:10.469 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21548 21:47:10.469 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21549 21:47:10.469 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21550 21:47:10.469 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21551 21:47:10.469 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21552 21:47:10.469 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21553 21:47:10.469 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21554 21:47:10.469 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21555 21:47:10.469 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21556 21:47:10.469 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21557 21:47:10.469 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21558 21:47:10.469 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21559 21:47:10.469 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21560 21:47:10.469 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21561 21:47:10.469 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21562 21:47:10.469 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21563 21:47:10.469 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21564 21:47:10.469 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21565 21:47:10.469 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21566 21:47:10.469 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21567 21:47:10.469 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21568 21:47:10.469 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21569 21:47:10.469 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21570 21:47:10.469 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21571 21:47:10.469 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21572 21:47:10.469 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21573 21:47:10.469 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21574 21:47:10.469 0.02801700 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21575 21:47:10.500 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21576 21:47:10.500 0.01355141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21577 21:47:10.500 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21578 21:47:10.516 0.00037412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21579 21:47:10.516 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21580 21:47:10.516 0.00034528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21581 21:47:10.516 0.00029630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21582 21:47:10.516 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21583 21:47:10.516 0.00058706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21584 21:47:10.516 0.00054005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 21585 21:47:10.516 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21586 21:47:10.516 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21587 21:47:10.516 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 21588 21:47:10.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21589 21:47:10.516 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21590 21:47:10.516 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21591 21:47:10.516 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21592 21:47:10.516 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21593 21:47:10.516 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21594 21:47:10.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21595 21:47:10.516 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21596 21:47:10.516 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21597 21:47:10.516 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21598 21:47:10.516 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21599 21:47:10.516 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21600 21:47:10.516 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21601 21:47:10.516 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21602 21:47:10.516 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21603 21:47:10.516 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21604 21:47:10.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21605 21:47:10.516 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21606 21:47:10.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21607 21:47:10.516 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21608 21:47:10.516 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21609 21:47:10.516 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21610 21:47:10.516 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21611 21:47:10.516 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21612 21:47:10.516 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21613 21:47:10.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21614 21:47:10.516 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21615 21:47:10.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21616 21:47:10.516 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21617 21:47:10.516 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21618 21:47:10.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21619 21:47:10.516 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21620 21:47:10.516 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21621 21:47:10.516 0.00034568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21622 21:47:10.516 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21623 21:47:10.516 0.00025561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21624 21:47:10.516 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21625 21:47:10.516 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21626 21:47:10.516 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21627 21:47:10.516 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21628 21:47:10.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21629 21:47:10.516 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21630 21:47:10.516 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21631 21:47:10.516 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21632 21:47:10.516 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21633 21:47:10.516 0.00027773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21634 21:47:10.516 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21635 21:47:10.516 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21636 21:47:10.516 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21637 21:47:10.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21638 21:47:10.516 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21639 21:47:10.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21640 21:47:10.516 0.02502440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21641 21:47:10.547 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21642 21:47:10.547 0.00006360 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21643 21:47:10.547 0.01407210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21644 21:47:10.563 0.00034094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21645 21:47:10.563 0.00155496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21646 21:47:10.563 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21647 21:47:10.563 0.00146845 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21648 21:47:10.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21649 21:47:10.563 0.00039546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21650 21:47:10.563 0.00029906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 21651 21:47:10.563 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 21652 21:47:10.563 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21653 21:47:10.563 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21654 21:47:10.563 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21655 21:47:10.563 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21656 21:47:10.563 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21657 21:47:10.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21658 21:47:10.563 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21659 21:47:10.563 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21660 21:47:10.563 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21661 21:47:10.563 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21662 21:47:10.563 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21663 21:47:10.563 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21664 21:47:10.563 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21665 21:47:10.563 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21666 21:47:10.563 0.00008257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21667 21:47:10.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21668 21:47:10.563 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21669 21:47:10.563 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21670 21:47:10.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21671 21:47:10.563 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21672 21:47:10.563 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21673 21:47:10.563 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21674 21:47:10.563 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21675 21:47:10.563 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21676 21:47:10.563 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21677 21:47:10.563 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 21678 21:47:10.563 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 21679 21:47:10.563 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21680 21:47:10.563 0.00033738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21681 21:47:10.563 0.00030143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21682 21:47:10.563 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21683 21:47:10.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21684 21:47:10.563 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21685 21:47:10.563 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21686 21:47:10.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21687 21:47:10.563 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21688 21:47:10.563 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21689 21:47:10.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21690 21:47:10.563 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21691 21:47:10.563 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21692 21:47:10.563 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21693 21:47:10.563 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21694 21:47:10.563 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21695 21:47:10.563 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21696 21:47:10.563 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21697 21:47:10.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21698 21:47:10.563 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21699 21:47:10.563 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21700 21:47:10.563 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21701 21:47:10.563 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21702 21:47:10.563 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21703 21:47:10.563 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21704 21:47:10.563 0.02766105 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21705 21:47:10.594 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21706 21:47:10.594 0.01273601 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21707 21:47:10.594 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21708 21:47:10.610 0.00026548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21709 21:47:10.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21710 21:47:10.610 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21711 21:47:10.610 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21712 21:47:10.610 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 21713 21:47:10.610 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 21714 21:47:10.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21715 21:47:10.610 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21716 21:47:10.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21717 21:47:10.610 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21718 21:47:10.610 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21719 21:47:10.610 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21720 21:47:10.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21721 21:47:10.610 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21722 21:47:10.610 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21723 21:47:10.610 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21724 21:47:10.610 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21725 21:47:10.610 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21726 21:47:10.610 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21727 21:47:10.610 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21728 21:47:10.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21729 21:47:10.610 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21730 21:47:10.610 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21731 21:47:10.610 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21732 21:47:10.610 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21733 21:47:10.610 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21734 21:47:10.610 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21735 21:47:10.610 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21736 21:47:10.610 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 21737 21:47:10.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21738 21:47:10.610 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 21745 21:47:10.610 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21746 21:47:10.610 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21747 21:47:10.610 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21748 21:47:10.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21749 21:47:10.610 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21750 21:47:10.610 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21751 21:47:10.610 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21752 21:47:10.610 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21753 21:47:10.610 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21754 21:47:10.610 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21755 21:47:10.610 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21756 21:47:10.610 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21757 21:47:10.610 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21758 21:47:10.610 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21759 21:47:10.610 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21760 21:47:10.610 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21761 21:47:10.610 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21762 21:47:10.610 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21763 21:47:10.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21764 21:47:10.610 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21765 21:47:10.610 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21766 21:47:10.610 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21767 21:47:10.610 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21768 21:47:10.610 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21769 21:47:10.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21770 21:47:10.610 0.03032258 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21771 21:47:10.641 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21772 21:47:10.641 0.01193324 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21773 21:47:10.641 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21774 21:47:10.657 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21775 21:47:10.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21776 21:47:10.657 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21777 21:47:10.657 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21778 21:47:10.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21779 21:47:10.657 0.00035556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21780 21:47:10.657 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 21781 21:47:10.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21782 21:47:10.657 0.00033106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21783 21:47:10.657 0.00029709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 21784 21:47:10.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21785 21:47:10.657 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21786 21:47:10.657 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21787 21:47:10.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21788 21:47:10.657 0.00028010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21789 21:47:10.657 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21790 21:47:10.657 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21791 21:47:10.657 0.00008020 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21792 21:47:10.657 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21793 21:47:10.657 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21794 21:47:10.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21795 21:47:10.657 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21796 21:47:10.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21797 21:47:10.657 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21798 21:47:10.657 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21799 21:47:10.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21800 21:47:10.657 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21801 21:47:10.657 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21802 21:47:10.657 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21803 21:47:10.657 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21804 21:47:10.657 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21805 21:47:10.657 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21806 21:47:10.657 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21807 21:47:10.657 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21808 21:47:10.657 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21809 21:47:10.657 0.00035635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21810 21:47:10.657 0.00029393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21811 21:47:10.657 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21812 21:47:10.657 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21813 21:47:10.657 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21814 21:47:10.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21815 21:47:10.657 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 21816 21:47:10.657 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 21820 21:47:10.657 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21821 21:47:10.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21822 21:47:10.657 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21823 21:47:10.657 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21824 21:47:10.657 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21825 21:47:10.657 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21826 21:47:10.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21827 21:47:10.657 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21828 21:47:10.657 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21829 21:47:10.657 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21830 21:47:10.657 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21831 21:47:10.657 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21832 21:47:10.657 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21833 21:47:10.657 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21834 21:47:10.657 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21835 21:47:10.657 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21836 21:47:10.657 0.02624475 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21837 21:47:10.688 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21838 21:47:10.688 0.01431309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21839 21:47:10.688 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21840 21:47:10.703 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21841 21:47:10.703 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21842 21:47:10.703 0.00031526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21843 21:47:10.703 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21844 21:47:10.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21845 21:47:10.703 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21846 21:47:10.703 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 21847 21:47:10.703 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 21848 21:47:10.703 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21849 21:47:10.703 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21850 21:47:10.703 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21851 21:47:10.703 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21852 21:47:10.703 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21853 21:47:10.703 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21854 21:47:10.703 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21855 21:47:10.703 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21857 21:47:10.703 0.00030222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21858 21:47:10.703 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21859 21:47:10.703 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21860 21:47:10.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21861 21:47:10.703 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21862 21:47:10.703 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21863 21:47:10.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21864 21:47:10.703 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21865 21:47:10.703 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21866 21:47:10.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21867 21:47:10.703 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21868 21:47:10.703 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21869 21:47:10.703 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21870 21:47:10.703 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21871 21:47:10.703 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21872 21:47:10.703 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21873 21:47:10.703 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21874 21:47:10.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21875 21:47:10.703 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21876 21:47:10.703 0.00032514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21877 21:47:10.703 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21878 21:47:10.703 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21879 21:47:10.703 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21880 21:47:10.703 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21881 21:47:10.703 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21882 21:47:10.703 0.00035121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21883 21:47:10.703 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21884 21:47:10.703 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21885 21:47:10.703 0.00027931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21886 21:47:10.703 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21887 21:47:10.703 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21888 21:47:10.703 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21889 21:47:10.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21890 21:47:10.703 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21891 21:47:10.703 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21892 21:47:10.703 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21893 21:47:10.703 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21894 21:47:10.703 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21895 21:47:10.703 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21896 21:47:10.703 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21897 21:47:10.703 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21898 21:47:10.703 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21899 21:47:10.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21900 21:47:10.703 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21901 21:47:10.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21902 21:47:10.703 0.02633838 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21903 21:47:10.735 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21904 21:47:10.735 0.01329344 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21905 21:47:10.735 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21906 21:47:10.750 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21907 21:47:10.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21908 21:47:10.750 0.00037768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21909 21:47:10.750 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21910 21:47:10.750 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21911 21:47:10.750 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 21912 21:47:10.750 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21913 21:47:10.750 0.00029156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 21914 21:47:10.750 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21915 21:47:10.750 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21916 21:47:10.750 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21917 21:47:10.750 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21918 21:47:10.750 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21919 21:47:10.750 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21920 21:47:10.750 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21921 21:47:10.750 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21922 21:47:10.750 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21923 21:47:10.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21924 21:47:10.750 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21925 21:47:10.750 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21926 21:47:10.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21927 21:47:10.750 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21928 21:47:10.750 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21929 21:47:10.750 0.00027970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21930 21:47:10.750 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21931 21:47:10.750 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21932 21:47:10.750 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21933 21:47:10.750 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21934 21:47:10.750 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21935 21:47:10.750 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21936 21:47:10.750 0.00019872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21937 21:47:10.750 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21938 21:47:10.750 0.00030301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21939 21:47:10.750 0.00023546 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21940 21:47:10.750 0.00008533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21941 21:47:10.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21942 21:47:10.750 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21943 21:47:10.750 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21944 21:47:10.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21945 21:47:10.750 0.00010430 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21946 21:47:10.750 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21947 21:47:10.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21948 21:47:10.750 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21949 21:47:10.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21950 21:47:10.750 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21951 21:47:10.750 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21952 21:47:10.750 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21953 21:47:10.750 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21954 21:47:10.750 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21955 21:47:10.750 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21956 21:47:10.750 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21957 21:47:10.750 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21958 21:47:10.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21959 21:47:10.750 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21960 21:47:10.750 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21961 21:47:10.750 0.00031684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21962 21:47:10.750 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21963 21:47:10.750 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21964 21:47:10.750 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21965 21:47:10.750 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21966 21:47:10.750 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21967 21:47:10.750 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21968 21:47:10.750 0.02902717 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21969 21:47:10.782 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21970 21:47:10.782 0.01244721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21971 21:47:10.782 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 21972 21:47:10.797 0.00038440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 21973 21:47:10.797 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21974 21:47:10.797 0.00033936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21975 21:47:10.797 0.00027970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 21976 21:47:10.797 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21977 21:47:10.797 0.00054756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 21978 21:47:10.797 0.00057205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21979 21:47:10.797 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21980 21:47:10.797 0.00047170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21981 21:47:10.797 0.00040217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 21982 21:47:10.797 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21983 21:47:10.797 0.00033580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21984 21:47:10.797 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 21985 21:47:10.797 0.00020543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21986 21:47:10.797 0.00027536 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21987 21:47:10.797 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21988 21:47:10.797 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21989 21:47:10.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21990 21:47:10.797 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21991 21:47:10.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21992 21:47:10.797 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21993 21:47:10.797 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21994 21:47:10.797 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21995 21:47:10.797 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21996 21:47:10.797 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21997 21:47:10.797 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 21998 21:47:10.797 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 21999 21:47:10.797 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22000 21:47:10.797 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22001 21:47:10.797 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22002 21:47:10.797 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22003 21:47:10.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22004 21:47:10.797 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22005 21:47:10.797 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22006 21:47:10.797 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22007 21:47:10.797 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22008 21:47:10.797 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22009 21:47:10.797 0.00019279 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22010 21:47:10.797 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22011 21:47:10.797 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22012 21:47:10.797 0.00033541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22013 21:47:10.797 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22014 21:47:10.797 0.00018726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22015 21:47:10.797 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22016 21:47:10.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22017 21:47:10.797 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22018 21:47:10.797 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22019 21:47:10.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22020 21:47:10.797 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22021 21:47:10.797 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22022 21:47:10.797 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22023 21:47:10.797 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22024 21:47:10.797 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22025 21:47:10.797 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22026 21:47:10.797 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22027 21:47:10.797 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22028 21:47:10.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22029 21:47:10.797 0.00021136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22030 21:47:10.797 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22031 21:47:10.797 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22033 21:47:10.797 0.00003437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22034 21:47:10.797 0.02526263 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22035 21:47:10.828 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22036 21:47:10.828 0.01260919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22037 21:47:10.828 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22038 21:47:10.844 0.00027141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22039 21:47:10.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22040 21:47:10.844 0.00030815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22041 21:47:10.844 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22042 21:47:10.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22043 21:47:10.844 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22044 21:47:10.844 0.00019081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22045 21:47:10.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22046 21:47:10.844 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22047 21:47:10.844 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 22048 21:47:10.844 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22049 21:47:10.844 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22050 21:47:10.844 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22051 21:47:10.844 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22052 21:47:10.844 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22053 21:47:10.844 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22054 21:47:10.844 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22055 21:47:10.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22056 21:47:10.844 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22057 21:47:10.844 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22058 21:47:10.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22059 21:47:10.844 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22060 21:47:10.844 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22061 21:47:10.844 0.00007783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22062 21:47:10.844 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22063 21:47:10.844 0.00029788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22064 21:47:10.844 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22065 21:47:10.844 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22066 21:47:10.844 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22067 21:47:10.844 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22068 21:47:10.844 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22069 21:47:10.844 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22070 21:47:10.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22071 21:47:10.844 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22072 21:47:10.844 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22073 21:47:10.844 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22074 21:47:10.844 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22075 21:47:10.844 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22076 21:47:10.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22077 21:47:10.844 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22078 21:47:10.844 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22079 21:47:10.844 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22080 21:47:10.844 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22081 21:47:10.844 0.00021136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22082 21:47:10.844 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22083 21:47:10.844 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22084 21:47:10.844 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22085 21:47:10.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22086 21:47:10.844 0.00022716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22087 21:47:10.844 0.00037136 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22088 21:47:10.844 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22089 21:47:10.844 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22090 21:47:10.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22091 21:47:10.844 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22092 21:47:10.844 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22093 21:47:10.844 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22096 21:47:10.844 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22097 21:47:10.844 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22098 21:47:10.844 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22099 21:47:10.844 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22100 21:47:10.844 0.02759310 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22101 21:47:10.875 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22102 21:47:10.875 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22103 21:47:10.875 0.01337561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22104 21:47:10.891 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22105 21:47:10.891 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22106 21:47:10.891 0.00022281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22107 21:47:10.891 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22108 21:47:10.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22109 21:47:10.891 0.00034015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22110 21:47:10.891 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22111 21:47:10.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22112 21:47:10.891 0.00028444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22113 21:47:10.891 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 22114 21:47:10.891 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22115 21:47:10.891 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22116 21:47:10.891 0.00014222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22117 21:47:10.891 0.00037965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22118 21:47:10.891 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22119 21:47:10.891 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22120 21:47:10.891 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22121 21:47:10.891 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22122 21:47:10.891 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22123 21:47:10.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22124 21:47:10.891 0.00022400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22125 21:47:10.891 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22126 21:47:10.891 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22127 21:47:10.891 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22128 21:47:10.891 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22129 21:47:10.891 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22130 21:47:10.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22131 21:47:10.891 0.00010983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22132 21:47:10.891 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22133 21:47:10.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22134 21:47:10.891 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22135 21:47:10.891 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22136 21:47:10.891 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22137 21:47:10.891 0.00028089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22138 21:47:10.891 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22139 21:47:10.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22140 21:47:10.891 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22141 21:47:10.891 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22142 21:47:10.891 0.00036701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22143 21:47:10.891 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22144 21:47:10.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22145 21:47:10.891 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22146 21:47:10.891 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22147 21:47:10.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22148 21:47:10.891 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22149 21:47:10.891 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22150 21:47:10.891 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22151 21:47:10.891 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22152 21:47:10.891 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22153 21:47:10.891 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22154 21:47:10.891 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22155 21:47:10.891 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22156 21:47:10.891 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22157 21:47:10.891 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22158 21:47:10.891 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22159 21:47:10.891 0.00008652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22160 21:47:10.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22161 21:47:10.891 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22162 21:47:10.891 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22163 21:47:10.891 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22164 21:47:10.891 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22165 21:47:10.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22166 21:47:10.891 0.02743823 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22167 21:47:10.922 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22168 21:47:10.922 0.01219714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22169 21:47:10.922 0.00003200 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22170 21:47:10.938 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22171 21:47:10.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22172 21:47:10.938 0.00030578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22173 21:47:10.938 0.00023546 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22174 21:47:10.938 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22175 21:47:10.938 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22176 21:47:10.938 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22177 21:47:10.938 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 22178 21:47:10.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22179 21:47:10.938 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22180 21:47:10.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22181 21:47:10.938 0.00033422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22182 21:47:10.938 0.00027694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22183 21:47:10.938 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22184 21:47:10.938 0.00030894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22185 21:47:10.938 0.00031961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22186 21:47:10.938 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22187 21:47:10.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22188 21:47:10.938 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22189 21:47:10.938 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22190 21:47:10.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22191 21:47:10.938 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22192 21:47:10.938 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22193 21:47:10.938 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22194 21:47:10.938 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22195 21:47:10.938 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22196 21:47:10.938 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22197 21:47:10.938 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22198 21:47:10.938 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22199 21:47:10.938 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22200 21:47:10.938 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22201 21:47:10.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22202 21:47:10.938 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22203 21:47:10.938 0.00021965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22204 21:47:10.938 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22205 21:47:10.938 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22206 21:47:10.938 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22207 21:47:10.938 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22208 21:47:10.938 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22209 21:47:10.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 22213 21:47:10.938 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22214 21:47:10.938 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22215 21:47:10.938 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22216 21:47:10.938 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22217 21:47:10.938 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22218 21:47:10.938 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22219 21:47:10.938 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22220 21:47:10.938 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22221 21:47:10.938 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22222 21:47:10.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22223 21:47:10.938 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22224 21:47:10.938 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22225 21:47:10.938 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22226 21:47:10.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22227 21:47:10.938 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22228 21:47:10.938 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22229 21:47:10.938 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22230 21:47:10.938 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22231 21:47:10.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22232 21:47:10.938 0.02643478 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22233 21:47:10.969 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22234 21:47:10.969 0.01449877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22235 21:47:10.969 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22236 21:47:10.985 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22237 21:47:10.985 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22238 21:47:10.985 0.00043931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22239 21:47:10.985 0.00039901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22240 21:47:10.985 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22241 21:47:10.985 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22242 21:47:10.985 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22243 21:47:10.985 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22244 21:47:10.985 0.00032632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22245 21:47:10.985 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 22246 21:47:10.985 0.00025323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22247 21:47:10.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22248 21:47:10.985 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22249 21:47:10.985 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22250 21:47:10.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22251 21:47:10.985 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22252 21:47:10.985 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22253 21:47:10.985 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22254 21:47:10.985 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22255 21:47:10.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22256 21:47:10.985 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22257 21:47:10.985 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22258 21:47:10.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22259 21:47:10.985 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22260 21:47:10.985 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22261 21:47:10.985 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 22262 21:47:10.985 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22263 21:47:10.985 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22264 21:47:10.985 0.00036701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22265 21:47:10.985 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22266 21:47:10.985 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22267 21:47:10.985 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22268 21:47:10.985 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22269 21:47:10.985 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22270 21:47:10.985 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22271 21:47:10.985 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22272 21:47:10.985 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22273 21:47:10.985 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22274 21:47:10.985 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22275 21:47:10.985 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22276 21:47:10.985 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22277 21:47:10.985 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22278 21:47:10.985 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22279 21:47:10.985 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 22280 21:47:10.985 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22285 21:47:10.985 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22286 21:47:10.985 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22287 21:47:10.985 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22288 21:47:10.985 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22289 21:47:10.985 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22290 21:47:10.985 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22291 21:47:10.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22292 21:47:10.985 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22293 21:47:10.985 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22294 21:47:10.985 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22295 21:47:10.985 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22296 21:47:10.985 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22297 21:47:10.985 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22298 21:47:10.985 0.02638816 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22299 21:47:11.016 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22300 21:47:11.016 0.01364702 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22301 21:47:11.016 0.00001659 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22302 21:47:11.032 0.00035911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22303 21:47:11.032 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22304 21:47:11.032 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22305 21:47:11.032 0.00030222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22306 21:47:11.032 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22307 21:47:11.032 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22308 21:47:11.032 0.00029077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22309 21:47:11.032 0.00028049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 22310 21:47:11.032 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22311 21:47:11.032 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22312 21:47:11.032 0.00042548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22313 21:47:11.032 0.00032751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22314 21:47:11.032 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22315 21:47:11.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22316 21:47:11.032 0.00033462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22317 21:47:11.032 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22318 21:47:11.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22319 21:47:11.032 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22320 21:47:11.032 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22321 21:47:11.032 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22322 21:47:11.032 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22323 21:47:11.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22324 21:47:11.032 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22325 21:47:11.032 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22326 21:47:11.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22327 21:47:11.032 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22328 21:47:11.032 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22329 21:47:11.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22330 21:47:11.032 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22331 21:47:11.032 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22332 21:47:11.032 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22333 21:47:11.032 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22334 21:47:11.032 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22335 21:47:11.032 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22336 21:47:11.032 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22337 21:47:11.032 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22338 21:47:11.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22339 21:47:11.032 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22340 21:47:11.032 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22341 21:47:11.032 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22342 21:47:11.032 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22343 21:47:11.032 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22344 21:47:11.032 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22345 21:47:11.032 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22346 21:47:11.032 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22347 21:47:11.032 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22348 21:47:11.032 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22349 21:47:11.032 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22350 21:47:11.032 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22351 21:47:11.032 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22352 21:47:11.032 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22353 21:47:11.032 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22354 21:47:11.032 0.00008612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22355 21:47:11.032 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22356 21:47:11.032 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22357 21:47:11.032 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22358 21:47:11.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22359 21:47:11.032 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22360 21:47:11.032 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22361 21:47:11.032 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22362 21:47:11.032 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22363 21:47:11.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22364 21:47:11.032 0.02826747 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22365 21:47:11.063 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22366 21:47:11.063 0.01269373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22367 21:47:11.063 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22368 21:47:11.079 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22369 21:47:11.079 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22370 21:47:11.079 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22371 21:47:11.079 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22372 21:47:11.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22373 21:47:11.079 0.00021136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22374 21:47:11.079 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22375 21:47:11.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22376 21:47:11.079 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22377 21:47:11.079 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 22378 21:47:11.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22379 21:47:11.079 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22380 21:47:11.079 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22381 21:47:11.079 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22382 21:47:11.079 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22383 21:47:11.079 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22384 21:47:11.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22385 21:47:11.079 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22386 21:47:11.079 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22387 21:47:11.079 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22388 21:47:11.079 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22389 21:47:11.079 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22390 21:47:11.079 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22391 21:47:11.079 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22392 21:47:11.079 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22393 21:47:11.079 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22394 21:47:11.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22395 21:47:11.079 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22396 21:47:11.079 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22397 21:47:11.079 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22398 21:47:11.079 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22399 21:47:11.079 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22400 21:47:11.079 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22401 21:47:11.079 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22402 21:47:11.079 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22403 21:47:11.079 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22404 21:47:11.079 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22405 21:47:11.079 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22406 21:47:11.079 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22407 21:47:11.079 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22408 21:47:11.079 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22409 21:47:11.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22410 21:47:11.079 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22411 21:47:11.079 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22412 21:47:11.079 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22413 21:47:11.079 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22414 21:47:11.079 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22415 21:47:11.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22416 21:47:11.079 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22417 21:47:11.079 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 22418 21:47:11.079 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22419 21:47:11.079 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 22423 21:47:11.079 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22424 21:47:11.079 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22425 21:47:11.079 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22426 21:47:11.079 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22427 21:47:11.079 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22428 21:47:11.079 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22429 21:47:11.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22430 21:47:11.079 0.02815764 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22431 21:47:11.109 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22432 21:47:11.109 0.01283951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22433 21:47:11.109 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22434 21:47:11.125 0.00037689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22435 21:47:11.125 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22436 21:47:11.125 0.00044089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22437 21:47:11.125 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22438 21:47:11.125 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22439 21:47:11.125 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22440 21:47:11.125 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22441 21:47:11.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22442 21:47:11.125 0.00030262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22443 21:47:11.125 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 22444 21:47:11.125 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22445 21:47:11.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22446 21:47:11.125 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22447 21:47:11.125 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22448 21:47:11.125 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22449 21:47:11.125 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22450 21:47:11.125 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22451 21:47:11.125 0.00030736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22452 21:47:11.125 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22453 21:47:11.125 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22454 21:47:11.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22455 21:47:11.125 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22456 21:47:11.125 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22457 21:47:11.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22458 21:47:11.125 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22459 21:47:11.125 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22460 21:47:11.125 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22461 21:47:11.125 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22462 21:47:11.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22463 21:47:11.125 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22464 21:47:11.125 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22465 21:47:11.125 0.00030933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22466 21:47:11.125 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22467 21:47:11.125 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22468 21:47:11.125 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22469 21:47:11.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22470 21:47:11.125 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22471 21:47:11.125 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22472 21:47:11.125 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22473 21:47:11.125 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22474 21:47:11.125 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22475 21:47:11.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22476 21:47:11.125 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22477 21:47:11.125 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22478 21:47:11.125 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22479 21:47:11.125 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22480 21:47:11.125 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22481 21:47:11.125 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22482 21:47:11.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22483 21:47:11.125 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22484 21:47:11.125 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22485 21:47:11.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22486 21:47:11.125 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22487 21:47:11.125 0.00032514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22488 21:47:11.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22489 21:47:11.125 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22490 21:47:11.125 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22491 21:47:11.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22492 21:47:11.125 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22493 21:47:11.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22494 21:47:11.125 0.02642213 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22495 21:47:11.159 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22496 21:47:11.159 0.02894026 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22497 21:47:11.159 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22498 21:47:11.188 0.00035081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22499 21:47:11.188 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22500 21:47:11.188 0.00034449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22501 21:47:11.188 0.00031605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22502 21:47:11.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22503 21:47:11.188 0.00031921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22504 21:47:11.188 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22505 21:47:11.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22506 21:47:11.188 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 22507 21:47:11.188 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22508 21:47:11.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22509 21:47:11.188 0.00033620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22510 21:47:11.188 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22511 21:47:11.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22512 21:47:11.188 0.00032869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22513 21:47:11.188 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22514 21:47:11.188 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22515 21:47:11.188 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22516 21:47:11.188 0.00025323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22517 21:47:11.188 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22518 21:47:11.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22519 21:47:11.188 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22520 21:47:11.188 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22521 21:47:11.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22522 21:47:11.188 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22523 21:47:11.188 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22524 21:47:11.188 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22525 21:47:11.188 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22526 21:47:11.188 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22527 21:47:11.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22528 21:47:11.188 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22529 21:47:11.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22530 21:47:11.188 0.00029551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22531 21:47:11.188 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22532 21:47:11.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22533 21:47:11.188 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22534 21:47:11.188 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22535 21:47:11.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22536 21:47:11.188 0.00022044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22537 21:47:11.188 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22538 21:47:11.188 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22539 21:47:11.188 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22540 21:47:11.188 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22541 21:47:11.188 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22542 21:47:11.188 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22543 21:47:11.188 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22544 21:47:11.188 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22545 21:47:11.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22546 21:47:11.188 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22547 21:47:11.188 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22548 21:47:11.188 0.00024257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22549 21:47:11.188 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22550 21:47:11.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22551 21:47:11.188 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22552 21:47:11.188 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22553 21:47:11.188 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22554 21:47:11.188 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22555 21:47:11.188 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22556 21:47:11.188 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22557 21:47:11.188 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22558 21:47:11.188 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22559 21:47:11.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22560 21:47:11.188 0.02559171 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22561 21:47:11.219 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22562 21:47:11.219 0.01356880 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22563 21:47:11.219 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22564 21:47:11.234 0.00033027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22565 21:47:11.234 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22566 21:47:11.234 0.00028049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22567 21:47:11.234 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22568 21:47:11.234 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22569 21:47:11.234 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22570 21:47:11.234 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22571 21:47:11.234 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 22572 21:47:11.234 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22573 21:47:11.234 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22574 21:47:11.234 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22575 21:47:11.234 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22576 21:47:11.234 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22577 21:47:11.234 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22578 21:47:11.234 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22579 21:47:11.234 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22580 21:47:11.234 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22581 21:47:11.234 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22582 21:47:11.234 0.00025244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22583 21:47:11.234 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22584 21:47:11.234 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22585 21:47:11.234 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22586 21:47:11.234 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22587 21:47:11.234 0.00032751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22588 21:47:11.234 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22589 21:47:11.234 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22590 21:47:11.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22591 21:47:11.234 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22592 21:47:11.234 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22593 21:47:11.234 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22594 21:47:11.234 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22595 21:47:11.234 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22596 21:47:11.234 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22597 21:47:11.234 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22598 21:47:11.234 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22599 21:47:11.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22600 21:47:11.234 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22601 21:47:11.234 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22602 21:47:11.234 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22603 21:47:11.234 0.00008810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22604 21:47:11.234 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22605 21:47:11.234 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22606 21:47:11.234 0.00024336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22607 21:47:11.234 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22608 21:47:11.234 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22609 21:47:11.234 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22610 21:47:11.234 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22611 21:47:11.234 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22612 21:47:11.234 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22613 21:47:11.234 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22614 21:47:11.234 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22615 21:47:11.234 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22616 21:47:11.234 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22617 21:47:11.234 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22618 21:47:11.234 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22619 21:47:11.234 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22620 21:47:11.234 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22621 21:47:11.234 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22622 21:47:11.234 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22623 21:47:11.234 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22624 21:47:11.234 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22625 21:47:11.234 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22626 21:47:11.234 0.02665562 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22627 21:47:11.266 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22628 21:47:11.266 0.01440356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22629 21:47:11.266 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22630 21:47:11.281 0.00032000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22631 21:47:11.281 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22632 21:47:11.281 0.00089995 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22633 21:47:11.281 0.00054005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22634 21:47:11.281 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22635 21:47:11.281 0.00061077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22636 21:47:11.281 0.00052543 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22637 21:47:11.281 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22638 21:47:11.281 0.00040652 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22639 21:47:11.281 0.00030499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 22640 21:47:11.281 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22641 21:47:11.281 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22642 21:47:11.281 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22643 21:47:11.281 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22644 21:47:11.281 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22645 21:47:11.281 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22646 21:47:11.281 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22647 21:47:11.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22648 21:47:11.281 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22649 21:47:11.281 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22650 21:47:11.281 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22651 21:47:11.281 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22652 21:47:11.281 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22653 21:47:11.281 0.00029630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22654 21:47:11.281 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22655 21:47:11.281 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22656 21:47:11.281 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22657 21:47:11.281 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22658 21:47:11.281 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22659 21:47:11.281 0.00030894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22660 21:47:11.281 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22661 21:47:11.281 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22662 21:47:11.281 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22663 21:47:11.281 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22664 21:47:11.281 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22665 21:47:11.281 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22666 21:47:11.281 0.00015881 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22667 21:47:11.281 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22668 21:47:11.281 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22669 21:47:11.281 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22670 21:47:11.281 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22671 21:47:11.281 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22672 21:47:11.281 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22673 21:47:11.281 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22674 21:47:11.281 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22675 21:47:11.281 0.00016869 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22676 21:47:11.281 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22677 21:47:11.281 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22678 21:47:11.281 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22679 21:47:11.281 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22680 21:47:11.281 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22681 21:47:11.281 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22682 21:47:11.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22683 21:47:11.281 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22684 21:47:11.281 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22685 21:47:11.281 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22686 21:47:11.281 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22687 21:47:11.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22688 21:47:11.281 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22689 21:47:11.281 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22690 21:47:11.281 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22691 21:47:11.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22692 21:47:11.281 0.02683339 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22693 21:47:11.313 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22694 21:47:11.313 0.01175546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22695 21:47:11.313 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22696 21:47:11.328 0.00036227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22697 21:47:11.328 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22698 21:47:11.328 0.00074825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22699 21:47:11.328 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22700 21:47:11.328 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22701 21:47:11.328 0.00039427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22702 21:47:11.328 0.00031368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22703 21:47:11.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22704 21:47:11.328 0.00035911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22705 21:47:11.328 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 22706 21:47:11.328 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22707 21:47:11.328 0.00026035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22708 21:47:11.328 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 22709 21:47:11.328 0.00030380 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22710 21:47:11.328 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22711 21:47:11.328 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22712 21:47:11.328 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22713 21:47:11.328 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22714 21:47:11.328 0.00025244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22715 21:47:11.328 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22716 21:47:11.328 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22717 21:47:11.328 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22718 21:47:11.328 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22719 21:47:11.328 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22720 21:47:11.328 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22721 21:47:11.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22722 21:47:11.328 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22723 21:47:11.328 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22724 21:47:11.328 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22725 21:47:11.328 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22726 21:47:11.328 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22727 21:47:11.328 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22728 21:47:11.328 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22729 21:47:11.328 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22730 21:47:11.328 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22731 21:47:11.328 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22732 21:47:11.328 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22733 21:47:11.328 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22734 21:47:11.328 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22735 21:47:11.328 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22736 21:47:11.328 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22737 21:47:11.328 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22738 21:47:11.328 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22739 21:47:11.328 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22740 21:47:11.328 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22741 21:47:11.328 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22742 21:47:11.328 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22743 21:47:11.328 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22744 21:47:11.328 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22745 21:47:11.328 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22746 21:47:11.328 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22747 21:47:11.328 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22748 21:47:11.328 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22749 21:47:11.328 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22750 21:47:11.328 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22751 21:47:11.328 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22752 21:47:11.328 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22753 21:47:11.328 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22754 21:47:11.328 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22755 21:47:11.328 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22756 21:47:11.328 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22757 21:47:11.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22758 21:47:11.328 0.02673265 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22759 21:47:11.360 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22760 21:47:11.360 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22761 21:47:11.360 0.01394252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22762 21:47:11.375 0.00025798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22763 21:47:11.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22764 21:47:11.375 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22765 21:47:11.375 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22766 21:47:11.375 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22767 21:47:11.375 0.00027299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22768 21:47:11.375 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22769 21:47:11.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22770 21:47:11.375 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 22771 21:47:11.375 0.00018607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22772 21:47:11.375 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22773 21:47:11.375 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22774 21:47:11.375 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22775 21:47:11.375 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22776 21:47:11.375 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22777 21:47:11.375 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22778 21:47:11.375 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22779 21:47:11.375 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22780 21:47:11.375 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22781 21:47:11.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22782 21:47:11.375 0.00021926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22783 21:47:11.375 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22784 21:47:11.375 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22785 21:47:11.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22786 21:47:11.375 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22787 21:47:11.375 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22788 21:47:11.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22789 21:47:11.375 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22790 21:47:11.375 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22791 21:47:11.375 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22792 21:47:11.375 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22793 21:47:11.375 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22794 21:47:11.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22795 21:47:11.375 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22796 21:47:11.375 0.00025521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22797 21:47:11.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22798 21:47:11.375 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22799 21:47:11.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22800 21:47:11.375 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22801 21:47:11.375 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22802 21:47:11.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22803 21:47:11.375 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22804 21:47:11.375 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22805 21:47:11.375 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22806 21:47:11.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22807 21:47:11.375 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22808 21:47:11.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22809 21:47:11.375 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22811 21:47:11.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22812 21:47:11.375 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22813 21:47:11.375 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22814 21:47:11.375 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22815 21:47:11.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22816 21:47:11.375 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22817 21:47:11.375 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22818 21:47:11.375 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22819 21:47:11.375 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22820 21:47:11.375 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22821 21:47:11.375 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22822 21:47:11.375 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22823 21:47:11.375 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22824 21:47:11.375 0.02853058 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22825 21:47:11.407 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22826 21:47:11.407 0.01329502 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22827 21:47:11.407 0.00004464 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22828 21:47:11.422 0.00035240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22829 21:47:11.422 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22830 21:47:11.422 0.00039625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22831 21:47:11.422 0.00032632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22832 21:47:11.422 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22833 21:47:11.422 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22834 21:47:11.422 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22835 21:47:11.422 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 22836 21:47:11.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22837 21:47:11.422 0.00025679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22838 21:47:11.422 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 22839 21:47:11.422 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22840 21:47:11.422 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22841 21:47:11.422 0.00032474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22842 21:47:11.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22843 21:47:11.422 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22844 21:47:11.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22845 21:47:11.422 0.00027812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22846 21:47:11.422 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22847 21:47:11.422 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22848 21:47:11.422 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22849 21:47:11.422 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22850 21:47:11.422 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22851 21:47:11.422 0.00040573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22852 21:47:11.422 0.00033936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22853 21:47:11.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22854 21:47:11.422 0.00033383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22855 21:47:11.422 0.00027259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22856 21:47:11.422 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22857 21:47:11.422 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22858 21:47:11.422 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22859 21:47:11.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22860 21:47:11.422 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22861 21:47:11.422 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22862 21:47:11.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22863 21:47:11.422 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22864 21:47:11.422 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22865 21:47:11.422 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22866 21:47:11.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22867 21:47:11.422 0.00010074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22868 21:47:11.422 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22869 21:47:11.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22870 21:47:11.422 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22871 21:47:11.422 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22872 21:47:11.422 0.00015644 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22873 21:47:11.422 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22874 21:47:11.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22875 21:47:11.422 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22876 21:47:11.422 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22877 21:47:11.422 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22878 21:47:11.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22879 21:47:11.422 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22880 21:47:11.422 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22881 21:47:11.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22882 21:47:11.422 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22883 21:47:11.422 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22884 21:47:11.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22885 21:47:11.422 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22886 21:47:11.422 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22887 21:47:11.422 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22888 21:47:11.422 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22889 21:47:11.422 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22890 21:47:11.422 0.02848199 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22891 21:47:11.454 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22892 21:47:11.454 0.01182855 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22893 21:47:11.454 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22894 21:47:11.469 0.00037412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22895 21:47:11.469 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22896 21:47:11.469 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22897 21:47:11.469 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22898 21:47:11.469 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22899 21:47:11.469 0.00036188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22900 21:47:11.469 0.00031565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 22901 21:47:11.469 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 22902 21:47:11.469 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22903 21:47:11.469 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22904 21:47:11.469 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22905 21:47:11.469 0.00031447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22907 21:47:11.469 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22908 21:47:11.469 0.00026825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22909 21:47:11.469 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22910 21:47:11.469 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22911 21:47:11.469 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22912 21:47:11.469 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22913 21:47:11.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22914 21:47:11.469 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22915 21:47:11.469 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22916 21:47:11.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22917 21:47:11.469 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22918 21:47:11.469 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22919 21:47:11.469 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22920 21:47:11.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22921 21:47:11.469 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22922 21:47:11.469 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22923 21:47:11.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22924 21:47:11.469 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22930 21:47:11.469 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22931 21:47:11.469 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22932 21:47:11.469 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22933 21:47:11.469 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22934 21:47:11.469 0.00030262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22935 21:47:11.469 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22936 21:47:11.469 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22937 21:47:11.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22938 21:47:11.469 0.00027259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22939 21:47:11.469 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22940 21:47:11.469 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22941 21:47:11.469 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22942 21:47:11.469 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22943 21:47:11.469 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22944 21:47:11.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22945 21:47:11.469 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22946 21:47:11.469 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22947 21:47:11.469 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22948 21:47:11.469 0.00013077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22949 21:47:11.469 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22950 21:47:11.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22951 21:47:11.469 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22952 21:47:11.469 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22953 21:47:11.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22954 21:47:11.469 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22955 21:47:11.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22956 21:47:11.469 0.02571379 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22957 21:47:11.500 0.00001106 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22958 21:47:11.500 0.01445334 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22959 21:47:11.500 0.00000435 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 22960 21:47:11.516 0.00032909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 22961 21:47:11.516 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22962 21:47:11.516 0.00030815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 22963 21:47:11.516 0.00030696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22964 21:47:11.516 0.00019200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22965 21:47:11.516 0.00043575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22966 21:47:11.516 0.00027220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 22967 21:47:11.516 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 22968 21:47:11.516 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22969 21:47:11.516 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22970 21:47:11.516 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22971 21:47:11.516 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 22972 21:47:11.516 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 22975 21:47:11.516 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22976 21:47:11.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22977 21:47:11.516 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22978 21:47:11.516 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22979 21:47:11.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22980 21:47:11.516 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22981 21:47:11.516 0.00022400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22982 21:47:11.516 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22983 21:47:11.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22984 21:47:11.516 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22985 21:47:11.516 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22986 21:47:11.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22987 21:47:11.516 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22988 21:47:11.516 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22989 21:47:11.516 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22990 21:47:11.516 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22991 21:47:11.516 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22992 21:47:11.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22993 21:47:11.516 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22994 21:47:11.516 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 22995 21:47:11.516 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22996 21:47:11.516 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22997 21:47:11.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22998 21:47:11.516 0.00033264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 22999 21:47:11.516 0.00027457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23000 21:47:11.516 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23001 21:47:11.516 0.00031012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23002 21:47:11.516 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23003 21:47:11.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23004 21:47:11.516 0.00026667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23005 21:47:11.516 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23006 21:47:11.516 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23007 21:47:11.516 0.00029590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23008 21:47:11.516 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23009 21:47:11.516 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23010 21:47:11.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23011 21:47:11.516 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23012 21:47:11.516 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23013 21:47:11.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23014 21:47:11.516 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23015 21:47:11.516 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23016 21:47:11.516 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23017 21:47:11.516 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23018 21:47:11.516 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23019 21:47:11.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23020 21:47:11.516 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23021 21:47:11.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23022 21:47:11.516 0.02609147 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23023 21:47:11.547 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23024 21:47:11.547 0.01363517 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23025 21:47:11.547 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23026 21:47:11.563 0.00042074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23027 21:47:11.563 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23028 21:47:11.563 0.00114924 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23029 21:47:11.563 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23030 21:47:11.563 0.00025956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 23031 21:47:11.563 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23032 21:47:11.563 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23033 21:47:11.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23034 21:47:11.563 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 23035 21:47:11.563 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23036 21:47:11.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23037 21:47:11.563 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23038 21:47:11.563 0.00033383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23039 21:47:11.563 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23040 21:47:11.563 0.00040770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23041 21:47:11.563 0.00034094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23042 21:47:11.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23043 21:47:11.563 0.00037807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23044 21:47:11.563 0.00028642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23045 21:47:11.563 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23046 21:47:11.563 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23047 21:47:11.563 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23048 21:47:11.563 0.00017067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23049 21:47:11.563 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23050 21:47:11.563 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23051 21:47:11.563 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23052 21:47:11.563 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23053 21:47:11.563 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23054 21:47:11.563 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23055 21:47:11.563 0.00030894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23056 21:47:11.563 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23057 21:47:11.563 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23058 21:47:11.563 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23059 21:47:11.563 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23060 21:47:11.563 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23061 21:47:11.563 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23062 21:47:11.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23063 21:47:11.563 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23064 21:47:11.563 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23065 21:47:11.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23066 21:47:11.563 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23067 21:47:11.563 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23068 21:47:11.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23069 21:47:11.563 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23070 21:47:11.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23071 21:47:11.563 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23072 21:47:11.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23073 21:47:11.563 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23074 21:47:11.563 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23075 21:47:11.563 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23076 21:47:11.563 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23077 21:47:11.563 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23078 21:47:11.563 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23079 21:47:11.563 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23080 21:47:11.563 0.00009679 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23081 21:47:11.563 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23082 21:47:11.563 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23083 21:47:11.563 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23084 21:47:11.563 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23085 21:47:11.563 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23086 21:47:11.563 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23087 21:47:11.563 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23088 21:47:11.563 0.02574342 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23089 21:47:11.594 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23090 21:47:11.594 0.01550934 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23091 21:47:11.594 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23092 21:47:11.610 0.00184494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23093 21:47:11.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23094 21:47:11.610 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23095 21:47:11.610 0.00017264 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23096 21:47:11.610 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 23097 21:47:11.610 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23098 21:47:11.610 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23099 21:47:11.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23100 21:47:11.610 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 23101 21:47:11.610 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23102 21:47:11.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23103 21:47:11.610 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23104 21:47:11.610 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23105 21:47:11.610 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23106 21:47:11.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23107 21:47:11.610 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23108 21:47:11.610 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23109 21:47:11.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23110 21:47:11.610 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23111 21:47:11.610 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23112 21:47:11.610 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23113 21:47:11.610 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23114 21:47:11.610 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23115 21:47:11.610 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23116 21:47:11.610 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23117 21:47:11.610 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23118 21:47:11.610 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23119 21:47:11.610 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23120 21:47:11.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23121 21:47:11.610 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23122 21:47:11.610 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23123 21:47:11.610 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23124 21:47:11.610 0.00025798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23125 21:47:11.610 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23126 21:47:11.610 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23127 21:47:11.610 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23128 21:47:11.610 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23129 21:47:11.610 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23130 21:47:11.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23131 21:47:11.610 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23132 21:47:11.610 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23133 21:47:11.610 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23134 21:47:11.610 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23135 21:47:11.610 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23136 21:47:11.610 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23137 21:47:11.610 0.00020385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23138 21:47:11.610 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23139 21:47:11.610 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23140 21:47:11.610 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23144 21:47:11.610 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23145 21:47:11.610 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23146 21:47:11.610 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23147 21:47:11.610 0.00000079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23148 21:47:11.610 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23149 21:47:11.610 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23150 21:47:11.610 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23151 21:47:11.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23152 21:47:11.610 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23153 21:47:11.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23154 21:47:11.610 0.02705818 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23155 21:47:11.641 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23156 21:47:11.641 0.01224336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23157 21:47:11.641 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23158 21:47:11.657 0.00031526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23159 21:47:11.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23160 21:47:11.657 0.00037057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23161 21:47:11.657 0.00034173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23162 21:47:11.657 0.00021689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 23163 21:47:11.657 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23164 21:47:11.657 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23165 21:47:11.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23166 21:47:11.657 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 23167 21:47:11.657 0.00029156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23168 21:47:11.657 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23169 21:47:11.657 0.00035635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23170 21:47:11.657 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23171 21:47:11.657 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23172 21:47:11.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23173 21:47:11.657 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23174 21:47:11.657 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23175 21:47:11.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23176 21:47:11.657 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23177 21:47:11.657 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23178 21:47:11.657 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23179 21:47:11.657 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23180 21:47:11.657 0.00027812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23181 21:47:11.657 0.00018054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23182 21:47:11.657 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23183 21:47:11.657 0.00040099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23184 21:47:11.657 0.00024138 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23185 21:47:11.657 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23186 21:47:11.657 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23187 21:47:11.657 0.00040533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23188 21:47:11.657 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23189 21:47:11.657 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23190 21:47:11.657 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23191 21:47:11.657 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23192 21:47:11.657 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23193 21:47:11.657 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23194 21:47:11.657 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23195 21:47:11.657 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23196 21:47:11.657 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23197 21:47:11.657 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23198 21:47:11.657 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23199 21:47:11.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23200 21:47:11.657 0.00012721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23201 21:47:11.657 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23202 21:47:11.657 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23203 21:47:11.657 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23207 21:47:11.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23208 21:47:11.657 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23209 21:47:11.657 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23210 21:47:11.657 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23211 21:47:11.657 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23212 21:47:11.657 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23213 21:47:11.657 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23214 21:47:11.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23215 21:47:11.657 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23216 21:47:11.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23217 21:47:11.657 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23218 21:47:11.657 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23219 21:47:11.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23220 21:47:11.657 0.02615902 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23221 21:47:11.688 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23222 21:47:11.688 0.01320336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23223 21:47:11.688 0.00005096 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23224 21:47:11.704 0.00030459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23225 21:47:11.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23228 21:47:11.704 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23229 21:47:11.704 0.00032593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23230 21:47:11.704 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1A 23231 21:47:11.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23232 21:47:11.704 0.00040454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23233 21:47:11.704 0.00031407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 23234 21:47:11.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23235 21:47:11.704 0.00026943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23236 21:47:11.704 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23237 21:47:11.704 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23238 21:47:11.704 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23239 21:47:11.704 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23240 21:47:11.704 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23241 21:47:11.704 0.00036583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23242 21:47:11.704 0.00026153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23243 21:47:11.704 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23244 21:47:11.704 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23245 21:47:11.704 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23246 21:47:11.704 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23247 21:47:11.704 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23248 21:47:11.704 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23249 21:47:11.704 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23250 21:47:11.704 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23251 21:47:11.704 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23252 21:47:11.704 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23253 21:47:11.704 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23254 21:47:11.704 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23255 21:47:11.704 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23256 21:47:11.704 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23257 21:47:11.704 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23258 21:47:11.704 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23259 21:47:11.704 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23260 21:47:11.704 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23261 21:47:11.704 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23262 21:47:11.704 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23263 21:47:11.704 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23264 21:47:11.704 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23265 21:47:11.704 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23266 21:47:11.704 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23267 21:47:11.704 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23268 21:47:11.704 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23269 21:47:11.704 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23270 21:47:11.704 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23271 21:47:11.704 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23272 21:47:11.704 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23273 21:47:11.704 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23274 21:47:11.704 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23275 21:47:11.704 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23276 21:47:11.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23277 21:47:11.704 0.00022558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23278 21:47:11.704 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23279 21:47:11.704 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23280 21:47:11.704 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23281 21:47:11.704 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23282 21:47:11.704 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23283 21:47:11.704 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23284 21:47:11.704 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23285 21:47:11.704 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23286 21:47:11.704 0.02679863 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23287 21:47:11.735 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23288 21:47:11.735 0.01401917 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23289 21:47:11.735 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23290 21:47:11.751 0.00040849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23291 21:47:11.751 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23292 21:47:11.751 0.00034331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23293 21:47:11.751 0.00025640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23294 21:47:11.751 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 23295 21:47:11.751 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23296 21:47:11.751 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23297 21:47:11.751 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23298 21:47:11.751 0.00031961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23299 21:47:11.751 0.00024849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 23300 21:47:11.751 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23301 21:47:11.751 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23302 21:47:11.751 0.00022005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23303 21:47:11.751 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23304 21:47:11.751 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23305 21:47:11.751 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23306 21:47:11.751 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23307 21:47:11.751 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23308 21:47:11.751 0.00022519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23309 21:47:11.751 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23310 21:47:11.751 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23311 21:47:11.751 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23312 21:47:11.751 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23313 21:47:11.751 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23314 21:47:11.751 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23315 21:47:11.751 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23316 21:47:11.751 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23317 21:47:11.751 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23318 21:47:11.751 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23319 21:47:11.751 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23320 21:47:11.751 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23321 21:47:11.751 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23322 21:47:11.751 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23323 21:47:11.751 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23324 21:47:11.751 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23325 21:47:11.751 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23326 21:47:11.751 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23327 21:47:11.751 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23328 21:47:11.751 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23329 21:47:11.751 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23330 21:47:11.751 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23331 21:47:11.751 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23332 21:47:11.751 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23333 21:47:11.751 0.00021452 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23334 21:47:11.751 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23335 21:47:11.751 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23336 21:47:11.751 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23337 21:47:11.751 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23338 21:47:11.751 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23339 21:47:11.751 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23340 21:47:11.751 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23341 21:47:11.751 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23342 21:47:11.751 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23343 21:47:11.751 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23344 21:47:11.751 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23345 21:47:11.751 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23346 21:47:11.751 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23347 21:47:11.751 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23348 21:47:11.751 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23349 21:47:11.751 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23350 21:47:11.751 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23351 21:47:11.751 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23352 21:47:11.751 0.02581808 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23353 21:47:11.781 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23354 21:47:11.781 0.01375210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23355 21:47:11.781 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23356 21:47:11.797 0.00036938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23357 21:47:11.797 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23358 21:47:11.797 0.00030459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23359 21:47:11.797 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23360 21:47:11.797 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23361 21:47:11.797 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23362 21:47:11.797 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 1A 23365 21:47:11.797 0.00037847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 23366 21:47:11.797 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23367 21:47:11.797 0.00051121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23368 21:47:11.797 0.00038281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23369 21:47:11.797 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23370 21:47:11.797 0.00041719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23371 21:47:11.797 0.00032593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23372 21:47:11.797 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23373 21:47:11.797 0.00031526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23374 21:47:11.797 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23375 21:47:11.797 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23376 21:47:11.797 0.00037057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23377 21:47:11.797 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23378 21:47:11.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23379 21:47:11.797 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23380 21:47:11.797 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23381 21:47:11.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23382 21:47:11.797 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23383 21:47:11.797 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23384 21:47:11.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23385 21:47:11.797 0.00033620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23386 21:47:11.797 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23387 21:47:11.797 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23388 21:47:11.797 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23389 21:47:11.797 0.00018726 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23390 21:47:11.797 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23391 21:47:11.797 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23392 21:47:11.797 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23393 21:47:11.797 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23394 21:47:11.797 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23395 21:47:11.797 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23396 21:47:11.797 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23397 21:47:11.797 0.00029788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23398 21:47:11.797 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23399 21:47:11.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23400 21:47:11.797 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23401 21:47:11.797 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23402 21:47:11.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23403 21:47:11.797 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23404 21:47:11.797 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23405 21:47:11.797 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23406 21:47:11.797 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23407 21:47:11.797 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23408 21:47:11.797 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23409 21:47:11.797 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23410 21:47:11.797 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23411 21:47:11.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23412 21:47:11.797 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23413 21:47:11.797 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23414 21:47:11.797 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23415 21:47:11.797 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23416 21:47:11.797 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23417 21:47:11.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23418 21:47:11.797 0.02621078 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23419 21:47:11.828 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23420 21:47:11.828 0.01326815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23421 21:47:11.828 0.00004464 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23422 21:47:11.844 0.00029274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23423 21:47:11.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23424 21:47:11.844 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23425 21:47:11.844 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23426 21:47:11.844 0.00032830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 23427 21:47:11.844 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23428 21:47:11.844 0.00028761 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23429 21:47:11.844 0.00026983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 23430 21:47:11.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23431 21:47:11.844 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23432 21:47:11.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23433 21:47:11.844 0.00032948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23434 21:47:11.844 0.00032948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23435 21:47:11.844 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23436 21:47:11.844 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23437 21:47:11.844 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23438 21:47:11.844 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23439 21:47:11.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23440 21:47:11.844 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23441 21:47:11.844 0.00032593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23442 21:47:11.844 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23443 21:47:11.844 0.00022321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23444 21:47:11.844 0.00023585 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23445 21:47:11.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23446 21:47:11.844 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23447 21:47:11.844 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23448 21:47:11.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23449 21:47:11.844 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23450 21:47:11.844 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23451 21:47:11.844 0.00030578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23452 21:47:11.844 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23453 21:47:11.844 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23454 21:47:11.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23455 21:47:11.844 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23456 21:47:11.844 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23457 21:47:11.844 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23458 21:47:11.844 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23459 21:47:11.844 0.00027496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23460 21:47:11.844 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23461 21:47:11.844 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23462 21:47:11.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23463 21:47:11.844 0.00056573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23464 21:47:11.844 0.00043299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23465 21:47:11.844 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23466 21:47:11.844 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23467 21:47:11.844 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23471 21:47:11.844 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23472 21:47:11.844 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23473 21:47:11.844 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23474 21:47:11.844 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23475 21:47:11.844 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23476 21:47:11.844 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23477 21:47:11.844 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23478 21:47:11.844 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23479 21:47:11.844 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23480 21:47:11.844 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23481 21:47:11.844 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23482 21:47:11.844 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23483 21:47:11.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23484 21:47:11.844 0.02460919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23485 21:47:11.875 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23486 21:47:11.875 0.01402983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23487 21:47:11.875 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23488 21:47:11.891 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23489 21:47:11.891 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23490 21:47:11.891 0.00031763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23491 21:47:11.891 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23492 21:47:11.891 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23493 21:47:11.891 0.00046617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23494 21:47:11.891 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 23495 21:47:11.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23496 21:47:11.891 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 23497 21:47:11.891 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23498 21:47:11.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23499 21:47:11.891 0.00031605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23500 21:47:11.891 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23501 21:47:11.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23502 21:47:11.891 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23503 21:47:11.891 0.00016553 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23504 21:47:11.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23505 21:47:11.891 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23506 21:47:11.891 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23507 21:47:11.891 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23508 21:47:11.891 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23509 21:47:11.891 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23510 21:47:11.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23511 21:47:11.891 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23512 21:47:11.891 0.00015723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23513 21:47:11.891 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23514 21:47:11.891 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23515 21:47:11.891 0.00016553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23516 21:47:11.891 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23517 21:47:11.891 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23518 21:47:11.891 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23519 21:47:11.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23520 21:47:11.891 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23521 21:47:11.891 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23522 21:47:11.891 0.00018528 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23523 21:47:11.891 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23524 21:47:11.891 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23525 21:47:11.891 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23526 21:47:11.891 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23527 21:47:11.891 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23528 21:47:11.891 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23529 21:47:11.891 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23530 21:47:11.891 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23531 21:47:11.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23532 21:47:11.891 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23533 21:47:11.891 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23534 21:47:11.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23535 21:47:11.891 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23536 21:47:11.891 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23537 21:47:11.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23538 21:47:11.891 0.00023901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23539 21:47:11.891 0.00018173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23540 21:47:11.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23541 21:47:11.891 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23542 21:47:11.891 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23543 21:47:11.891 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23544 21:47:11.891 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23545 21:47:11.891 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23546 21:47:11.891 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23547 21:47:11.891 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23548 21:47:11.891 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23549 21:47:11.891 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23550 21:47:11.891 0.02650944 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23551 21:47:11.922 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23552 21:47:11.922 0.01465838 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23553 21:47:11.922 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23554 21:47:11.938 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23555 21:47:11.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23556 21:47:11.938 0.00025837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23557 21:47:11.938 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23558 21:47:11.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23559 21:47:11.938 0.00122469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23560 21:47:11.938 0.00030933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 23561 21:47:11.938 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23562 21:47:11.938 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23563 21:47:11.938 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23564 21:47:11.938 0.00037847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23565 21:47:11.938 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23566 21:47:11.938 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23567 21:47:11.938 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23568 21:47:11.938 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23569 21:47:11.938 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23570 21:47:11.938 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23571 21:47:11.938 0.00031763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23572 21:47:11.938 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23573 21:47:11.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23574 21:47:11.938 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23575 21:47:11.938 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23576 21:47:11.938 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23577 21:47:11.938 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23578 21:47:11.938 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23579 21:47:11.938 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23580 21:47:11.938 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23581 21:47:11.938 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23582 21:47:11.938 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23583 21:47:11.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23584 21:47:11.938 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23585 21:47:11.938 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23586 21:47:11.938 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23587 21:47:11.938 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23588 21:47:11.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23589 21:47:11.938 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23590 21:47:11.938 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23591 21:47:11.938 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23592 21:47:11.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23593 21:47:11.938 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23594 21:47:11.938 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23595 21:47:11.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23596 21:47:11.938 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23597 21:47:11.938 0.00084227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23598 21:47:11.938 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23599 21:47:11.938 0.00073244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23600 21:47:11.938 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23601 21:47:11.938 0.00015170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23602 21:47:11.938 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23603 21:47:11.938 0.00027773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23604 21:47:11.938 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23605 21:47:11.938 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23606 21:47:11.938 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23607 21:47:11.938 0.00037926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23608 21:47:11.938 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23609 21:47:11.938 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23610 21:47:11.938 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23611 21:47:11.938 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23612 21:47:11.938 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23613 21:47:11.938 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23614 21:47:11.938 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23617 21:47:11.969 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23618 21:47:11.969 0.01346094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23619 21:47:11.969 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23620 21:47:11.985 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23621 21:47:11.985 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23622 21:47:11.985 0.00030973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23623 21:47:11.985 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23624 21:47:11.985 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23625 21:47:11.985 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23626 21:47:11.985 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 23627 21:47:11.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23628 21:47:11.985 0.00026588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23629 21:47:11.985 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23630 21:47:11.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23631 21:47:11.985 0.00024691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23632 21:47:11.985 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23633 21:47:11.985 0.00036622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23634 21:47:11.985 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23635 21:47:11.985 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23636 21:47:11.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23637 21:47:11.985 0.00038558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23638 21:47:11.985 0.00032000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23639 21:47:11.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23640 21:47:11.985 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23641 21:47:11.985 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23642 21:47:11.985 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23643 21:47:11.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23644 21:47:11.985 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23645 21:47:11.985 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23646 21:47:11.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23647 21:47:11.985 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23648 21:47:11.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23649 21:47:11.985 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23650 21:47:11.985 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23651 21:47:11.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23652 21:47:11.985 0.00026074 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23653 21:47:11.985 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23654 21:47:11.985 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23655 21:47:11.985 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23656 21:47:11.985 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23657 21:47:11.985 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23658 21:47:11.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23659 21:47:11.985 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23660 21:47:11.985 0.00007506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23661 21:47:11.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23662 21:47:11.985 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23663 21:47:11.985 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23664 21:47:11.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23665 21:47:11.985 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23666 21:47:11.985 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23667 21:47:11.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23668 21:47:11.985 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23669 21:47:11.985 0.00007862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23670 21:47:11.985 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23671 21:47:11.985 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23672 21:47:11.985 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23673 21:47:11.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23674 21:47:11.985 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23675 21:47:11.985 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23676 21:47:11.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23677 21:47:11.985 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23678 21:47:11.985 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23679 21:47:11.985 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23680 21:47:11.985 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23681 21:47:11.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23682 21:47:11.985 0.02708663 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23683 21:47:12.016 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23684 21:47:12.016 0.01495546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23685 21:47:12.016 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23686 21:47:12.032 0.00050291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23687 21:47:12.032 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23688 21:47:12.032 0.00031210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23689 21:47:12.032 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23690 21:47:12.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23691 21:47:12.032 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 23692 21:47:12.032 0.00022756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23693 21:47:12.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23694 21:47:12.032 0.00036069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23695 21:47:12.032 0.00025205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 23696 21:47:12.032 0.00027496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23697 21:47:12.032 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23698 21:47:12.032 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23699 21:47:12.032 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23700 21:47:12.032 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23701 21:47:12.032 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23702 21:47:12.032 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23703 21:47:12.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23704 21:47:12.032 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23705 21:47:12.032 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23706 21:47:12.032 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23707 21:47:12.032 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23708 21:47:12.032 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23709 21:47:12.032 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23710 21:47:12.032 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23711 21:47:12.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23712 21:47:12.032 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23713 21:47:12.032 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23714 21:47:12.032 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23715 21:47:12.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23716 21:47:12.032 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23720 21:47:12.032 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23721 21:47:12.032 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23722 21:47:12.032 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23723 21:47:12.032 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23724 21:47:12.032 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23725 21:47:12.032 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23726 21:47:12.032 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23727 21:47:12.032 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23728 21:47:12.032 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23729 21:47:12.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23730 21:47:12.032 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23731 21:47:12.032 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23732 21:47:12.032 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23733 21:47:12.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23734 21:47:12.032 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23735 21:47:12.032 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23736 21:47:12.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23737 21:47:12.032 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23738 21:47:12.032 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23739 21:47:12.032 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23740 21:47:12.032 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23741 21:47:12.032 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23742 21:47:12.032 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23743 21:47:12.032 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23744 21:47:12.032 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23745 21:47:12.032 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23746 21:47:12.032 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23747 21:47:12.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23748 21:47:12.032 0.02781078 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23749 21:47:12.063 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23750 21:47:12.063 0.01100405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23751 21:47:12.063 0.00002765 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23752 21:47:12.078 0.00034489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23753 21:47:12.078 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23754 21:47:12.078 0.00032277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23755 21:47:12.078 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23756 21:47:12.078 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 23757 21:47:12.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23758 21:47:12.078 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23759 21:47:12.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23760 21:47:12.078 0.00031486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23761 21:47:12.078 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 23762 21:47:12.078 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23763 21:47:12.078 0.00033857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23764 21:47:12.078 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23765 21:47:12.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23766 21:47:12.078 0.00040612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23767 21:47:12.078 0.00043812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23768 21:47:12.078 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23769 21:47:12.078 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23770 21:47:12.078 0.00044207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23771 21:47:12.078 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23772 21:47:12.078 0.00049422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23773 21:47:12.078 0.00031565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23774 21:47:12.078 0.00034726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23775 21:47:12.078 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23776 21:47:12.078 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23777 21:47:12.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23778 21:47:12.078 0.00034291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23779 21:47:12.078 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23780 21:47:12.078 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23781 21:47:12.078 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23782 21:47:12.078 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23783 21:47:12.078 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23784 21:47:12.078 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23785 21:47:12.078 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23786 21:47:12.078 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23787 21:47:12.078 0.00028761 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23788 21:47:12.078 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23789 21:47:12.078 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23790 21:47:12.078 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23791 21:47:12.078 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23792 21:47:12.078 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23793 21:47:12.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23794 21:47:12.078 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23795 21:47:12.078 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23796 21:47:12.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23797 21:47:12.078 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23798 21:47:12.078 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23799 21:47:12.078 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23800 21:47:12.078 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23801 21:47:12.078 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23802 21:47:12.078 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23803 21:47:12.078 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23804 21:47:12.078 0.00007704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23805 21:47:12.078 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23806 21:47:12.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23807 21:47:12.078 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23808 21:47:12.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23809 21:47:12.078 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23810 21:47:12.078 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23811 21:47:12.078 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23812 21:47:12.078 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23813 21:47:12.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23814 21:47:12.078 0.02627596 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23815 21:47:12.110 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23816 21:47:12.110 0.01338667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23817 21:47:12.110 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23818 21:47:12.125 0.00028247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23819 21:47:12.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23820 21:47:12.125 0.00037610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23821 21:47:12.125 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23822 21:47:12.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23823 21:47:12.125 0.00033857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23824 21:47:12.125 0.00032830 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 23825 21:47:12.125 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23826 21:47:12.125 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23827 21:47:12.125 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 23828 21:47:12.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23829 21:47:12.125 0.00034015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23830 21:47:12.125 0.00028168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23831 21:47:12.125 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23832 21:47:12.125 0.00025521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23833 21:47:12.125 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23834 21:47:12.125 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23835 21:47:12.125 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23836 21:47:12.125 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23837 21:47:12.125 0.00001067 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23838 21:47:12.125 0.00027457 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23839 21:47:12.125 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23840 21:47:12.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23841 21:47:12.125 0.00025719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23842 21:47:12.125 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23843 21:47:12.125 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23844 21:47:12.125 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23845 21:47:12.125 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23846 21:47:12.125 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23847 21:47:12.125 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23848 21:47:12.125 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23849 21:47:12.125 0.00018370 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23850 21:47:12.125 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23851 21:47:12.125 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23852 21:47:12.125 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23853 21:47:12.125 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23854 21:47:12.125 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23855 21:47:12.125 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23856 21:47:12.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23857 21:47:12.125 0.00012879 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23858 21:47:12.125 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23859 21:47:12.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23860 21:47:12.125 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23861 21:47:12.125 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23862 21:47:12.125 0.00032316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23863 21:47:12.125 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23864 21:47:12.125 0.00011180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23865 21:47:12.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23866 21:47:12.125 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23867 21:47:12.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23872 21:47:12.125 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23873 21:47:12.125 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23874 21:47:12.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23875 21:47:12.125 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23876 21:47:12.125 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23877 21:47:12.125 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23878 21:47:12.125 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23879 21:47:12.125 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23880 21:47:12.125 0.02538391 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23881 21:47:12.157 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23882 21:47:12.157 0.01489502 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23883 21:47:12.157 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23884 21:47:12.172 0.00034489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23885 21:47:12.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23886 21:47:12.172 0.00031605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23887 21:47:12.172 0.00028365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23888 21:47:12.172 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23889 21:47:12.172 0.00030538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 23890 21:47:12.172 0.00034054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23891 21:47:12.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23892 21:47:12.172 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23893 21:47:12.172 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 23894 21:47:12.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23895 21:47:12.172 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23896 21:47:12.172 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23897 21:47:12.172 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23898 21:47:12.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23899 21:47:12.172 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23903 21:47:12.172 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23904 21:47:12.172 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23905 21:47:12.172 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23906 21:47:12.172 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23907 21:47:12.172 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23908 21:47:12.172 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23909 21:47:12.172 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23910 21:47:12.172 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23911 21:47:12.172 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23912 21:47:12.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23913 21:47:12.172 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23914 21:47:12.172 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23915 21:47:12.172 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23916 21:47:12.172 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23917 21:47:12.172 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23918 21:47:12.172 0.00009363 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23919 21:47:12.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23920 21:47:12.172 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23921 21:47:12.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23922 21:47:12.172 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23923 21:47:12.172 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23924 21:47:12.172 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23925 21:47:12.172 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23926 21:47:12.172 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23927 21:47:12.172 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23928 21:47:12.172 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23929 21:47:12.172 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23933 21:47:12.172 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23934 21:47:12.172 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23935 21:47:12.172 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23936 21:47:12.172 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23937 21:47:12.172 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23938 21:47:12.172 0.00009244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23939 21:47:12.172 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23940 21:47:12.172 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23941 21:47:12.172 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23942 21:47:12.172 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23943 21:47:12.172 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23944 21:47:12.172 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23945 21:47:12.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23946 21:47:12.172 0.02939181 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23947 21:47:12.204 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23948 21:47:12.204 0.01195023 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23949 21:47:12.204 0.00008336 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 23950 21:47:12.219 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 23951 21:47:12.219 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23952 21:47:12.219 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23953 21:47:12.219 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 23954 21:47:12.219 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 23955 21:47:12.219 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23956 21:47:12.219 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23957 21:47:12.219 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 23958 21:47:12.219 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23959 21:47:12.219 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23960 21:47:12.219 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 23961 21:47:12.219 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23962 21:47:12.219 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23963 21:47:12.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23964 21:47:12.219 0.00030420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23966 21:47:12.219 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23967 21:47:12.219 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23968 21:47:12.219 0.00029353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23969 21:47:12.219 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23970 21:47:12.219 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23971 21:47:12.219 0.00024257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23972 21:47:12.219 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 23973 21:47:12.219 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23974 21:47:12.219 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 23981 21:47:12.219 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23982 21:47:12.219 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23983 21:47:12.219 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23984 21:47:12.219 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23985 21:47:12.219 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23986 21:47:12.219 0.00011575 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23987 21:47:12.219 0.00028800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23988 21:47:12.219 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23989 21:47:12.219 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23990 21:47:12.219 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23991 21:47:12.219 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23992 21:47:12.219 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23993 21:47:12.219 0.00027338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23994 21:47:12.219 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23995 21:47:12.219 0.00022795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23996 21:47:12.219 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 23997 21:47:12.219 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 23998 21:47:12.219 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 23999 21:47:12.219 0.00023862 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24000 21:47:12.219 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24001 21:47:12.219 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24002 21:47:12.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24003 21:47:12.219 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24004 21:47:12.219 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24005 21:47:12.219 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24006 21:47:12.219 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24007 21:47:12.219 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24008 21:47:12.219 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24009 21:47:12.219 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24010 21:47:12.219 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24011 21:47:12.219 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24012 21:47:12.219 0.02487942 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24013 21:47:12.250 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24014 21:47:12.250 0.01364346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24015 21:47:12.250 0.00000632 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24016 21:47:12.266 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24017 21:47:12.266 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24018 21:47:12.266 0.00044602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24019 21:47:12.266 0.00037254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24020 21:47:12.266 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24021 21:47:12.266 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24022 21:47:12.266 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24023 21:47:12.266 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24024 21:47:12.266 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 24025 21:47:12.266 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24026 21:47:12.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24027 21:47:12.266 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24028 21:47:12.266 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24029 21:47:12.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24030 21:47:12.266 0.00021136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24031 21:47:12.266 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24032 21:47:12.266 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24033 21:47:12.266 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24034 21:47:12.266 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24035 21:47:12.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24036 21:47:12.266 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24037 21:47:12.266 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24038 21:47:12.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24039 21:47:12.266 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24040 21:47:12.266 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24041 21:47:12.266 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24042 21:47:12.266 0.00014064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24043 21:47:12.266 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24044 21:47:12.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24045 21:47:12.266 0.00037294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24046 21:47:12.266 0.00030973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24047 21:47:12.266 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24048 21:47:12.266 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24049 21:47:12.266 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24050 21:47:12.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24051 21:47:12.266 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24052 21:47:12.266 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24053 21:47:12.266 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24054 21:47:12.266 0.00011457 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24055 21:47:12.266 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24056 21:47:12.266 0.00009877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24057 21:47:12.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24058 21:47:12.266 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24059 21:47:12.266 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24060 21:47:12.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24061 21:47:12.266 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24062 21:47:12.266 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24063 21:47:12.266 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24064 21:47:12.266 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24065 21:47:12.266 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24066 21:47:12.266 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24067 21:47:12.266 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24068 21:47:12.266 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24069 21:47:12.266 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24070 21:47:12.266 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24071 21:47:12.266 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24072 21:47:12.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24073 21:47:12.266 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24074 21:47:12.266 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24075 21:47:12.266 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24076 21:47:12.266 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24077 21:47:12.266 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24078 21:47:12.266 0.02777088 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24079 21:47:12.297 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24080 21:47:12.297 0.01398796 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24081 21:47:12.297 0.00001659 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24082 21:47:12.313 0.00031407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24083 21:47:12.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24084 21:47:12.313 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24086 21:47:12.313 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 24087 21:47:12.313 0.00009995 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24088 21:47:12.313 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24089 21:47:12.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24090 21:47:12.313 0.00032632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24091 21:47:12.313 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 24092 21:47:12.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24093 21:47:12.313 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24094 21:47:12.313 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24095 21:47:12.313 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24096 21:47:12.313 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24097 21:47:12.313 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24098 21:47:12.313 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24099 21:47:12.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24100 21:47:12.313 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24101 21:47:12.313 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24102 21:47:12.313 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24103 21:47:12.313 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24104 21:47:12.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24105 21:47:12.313 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24106 21:47:12.313 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24107 21:47:12.313 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24108 21:47:12.313 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24109 21:47:12.313 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24110 21:47:12.313 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 24111 21:47:12.313 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24113 21:47:12.313 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24114 21:47:12.313 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24115 21:47:12.313 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24116 21:47:12.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24117 21:47:12.313 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24118 21:47:12.313 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24119 21:47:12.313 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24120 21:47:12.313 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24121 21:47:12.313 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24122 21:47:12.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24123 21:47:12.313 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24124 21:47:12.313 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24125 21:47:12.313 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24126 21:47:12.313 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24127 21:47:12.313 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24128 21:47:12.313 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24129 21:47:12.313 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24130 21:47:12.313 0.00010035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24131 21:47:12.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24132 21:47:12.313 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24133 21:47:12.313 0.00015328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24134 21:47:12.313 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24135 21:47:12.313 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24136 21:47:12.313 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 24138 21:47:12.313 0.00009481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24139 21:47:12.313 0.00023111 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24140 21:47:12.313 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24141 21:47:12.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24142 21:47:12.313 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24143 21:47:12.313 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24144 21:47:12.313 0.02567626 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24145 21:47:12.344 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24146 21:47:12.344 0.01474845 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24147 21:47:12.344 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24148 21:47:12.360 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24149 21:47:12.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24150 21:47:12.360 0.00018331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24151 21:47:12.360 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24152 21:47:12.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24153 21:47:12.360 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24154 21:47:12.360 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24155 21:47:12.360 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 24156 21:47:12.360 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24157 21:47:12.360 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24158 21:47:12.360 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24159 21:47:12.360 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24160 21:47:12.360 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24161 21:47:12.360 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24162 21:47:12.360 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24163 21:47:12.360 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24164 21:47:12.360 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24165 21:47:12.360 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24166 21:47:12.360 0.00020662 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24167 21:47:12.360 0.00022084 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24168 21:47:12.360 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24169 21:47:12.360 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24170 21:47:12.360 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24171 21:47:12.360 0.00035714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24172 21:47:12.360 0.00031249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24173 21:47:12.360 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24174 21:47:12.360 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24175 21:47:12.360 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24176 21:47:12.360 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24177 21:47:12.360 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24178 21:47:12.360 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24179 21:47:12.360 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24180 21:47:12.360 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24181 21:47:12.360 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24182 21:47:12.360 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24183 21:47:12.360 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24184 21:47:12.360 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24185 21:47:12.360 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24186 21:47:12.360 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24187 21:47:12.360 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24188 21:47:12.360 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24189 21:47:12.360 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24190 21:47:12.360 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24191 21:47:12.360 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24192 21:47:12.360 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24193 21:47:12.360 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24194 21:47:12.360 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24195 21:47:12.360 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24196 21:47:12.360 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24197 21:47:12.360 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24198 21:47:12.360 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24199 21:47:12.360 0.00001383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24200 21:47:12.360 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24201 21:47:12.360 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24202 21:47:12.360 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24203 21:47:12.360 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24204 21:47:12.360 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24205 21:47:12.360 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24206 21:47:12.360 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24207 21:47:12.360 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24208 21:47:12.360 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24209 21:47:12.360 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24210 21:47:12.360 0.02639290 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24211 21:47:12.391 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24212 21:47:12.391 0.01502499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24213 21:47:12.391 0.00005254 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24214 21:47:12.407 0.00031210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24215 21:47:12.407 0.00034212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24216 21:47:12.407 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24217 21:47:12.407 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24218 21:47:12.407 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24219 21:47:12.407 0.00137007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24220 21:47:12.407 0.00030696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 24221 21:47:12.407 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24222 21:47:12.407 0.00037017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24223 21:47:12.407 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 24224 21:47:12.407 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24225 21:47:12.407 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24227 21:47:12.407 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24228 21:47:12.407 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24229 21:47:12.407 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24230 21:47:12.407 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24231 21:47:12.407 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24232 21:47:12.407 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24233 21:47:12.407 0.00023190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24234 21:47:12.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24235 21:47:12.407 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24236 21:47:12.407 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24237 21:47:12.407 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24238 21:47:12.407 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24239 21:47:12.407 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24240 21:47:12.407 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24241 21:47:12.407 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24242 21:47:12.407 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24243 21:47:12.407 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24244 21:47:12.407 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24245 21:47:12.407 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24246 21:47:12.407 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24247 21:47:12.407 0.00029669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24248 21:47:12.407 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24249 21:47:12.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24250 21:47:12.407 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24251 21:47:12.407 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24252 21:47:12.407 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24253 21:47:12.407 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24254 21:47:12.407 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24255 21:47:12.407 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24256 21:47:12.407 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24257 21:47:12.407 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24258 21:47:12.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24259 21:47:12.407 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24260 21:47:12.407 0.00009284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24261 21:47:12.407 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24262 21:47:12.407 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24263 21:47:12.407 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24264 21:47:12.407 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24265 21:47:12.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24266 21:47:12.407 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24267 21:47:12.407 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24268 21:47:12.407 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24269 21:47:12.407 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24270 21:47:12.407 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24271 21:47:12.407 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24272 21:47:12.407 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24273 21:47:12.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24274 21:47:12.407 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24275 21:47:12.407 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24276 21:47:12.407 0.02648495 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24277 21:47:12.438 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24278 21:47:12.438 0.01334954 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24279 21:47:12.438 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24280 21:47:12.454 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24281 21:47:12.454 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24282 21:47:12.454 0.00037175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24283 21:47:12.454 0.00029077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24284 21:47:12.454 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24285 21:47:12.454 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24286 21:47:12.454 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24287 21:47:12.454 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24288 21:47:12.454 0.00037531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24289 21:47:12.454 0.00030262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 24290 21:47:12.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24291 21:47:12.454 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24292 21:47:12.454 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24293 21:47:12.454 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24294 21:47:12.454 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24295 21:47:12.454 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24296 21:47:12.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24297 21:47:12.454 0.00033857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24298 21:47:12.454 0.00026153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24299 21:47:12.454 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24300 21:47:12.454 0.00034884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24301 21:47:12.454 0.00026627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24302 21:47:12.454 0.00033067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24303 21:47:12.454 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24304 21:47:12.454 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24305 21:47:12.454 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24306 21:47:12.454 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24307 21:47:12.454 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24308 21:47:12.454 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24309 21:47:12.454 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24310 21:47:12.454 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24311 21:47:12.454 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24312 21:47:12.454 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24313 21:47:12.454 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24314 21:47:12.454 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24315 21:47:12.454 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24316 21:47:12.454 0.00024020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24317 21:47:12.454 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24318 21:47:12.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24319 21:47:12.454 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24320 21:47:12.454 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24321 21:47:12.454 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24322 21:47:12.454 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24323 21:47:12.454 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24324 21:47:12.454 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24325 21:47:12.454 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24326 21:47:12.454 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24327 21:47:12.454 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24328 21:47:12.454 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24329 21:47:12.454 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24330 21:47:12.454 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24331 21:47:12.454 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24332 21:47:12.454 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24333 21:47:12.454 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24334 21:47:12.454 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24335 21:47:12.454 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24336 21:47:12.454 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24337 21:47:12.454 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24338 21:47:12.454 0.00021610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24339 21:47:12.454 0.00031052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24340 21:47:12.454 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24341 21:47:12.454 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24342 21:47:12.454 0.02849344 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24343 21:47:12.485 0.00001896 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24344 21:47:12.485 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24345 21:47:12.485 0.02683932 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24346 21:47:12.516 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24347 21:47:12.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24348 21:47:12.516 0.00034607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24349 21:47:12.516 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24350 21:47:12.516 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24351 21:47:12.516 0.00035200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24352 21:47:12.516 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 24353 21:47:12.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24354 21:47:12.516 0.00046894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24355 21:47:12.516 0.00038874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 24356 21:47:12.516 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24357 21:47:12.516 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24358 21:47:12.516 0.00011733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24359 21:47:12.516 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24360 21:47:12.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24361 21:47:12.516 0.00024968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24362 21:47:12.516 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24363 21:47:12.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24364 21:47:12.516 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24365 21:47:12.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24366 21:47:12.516 0.00037926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24367 21:47:12.516 0.00027931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24368 21:47:12.516 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24369 21:47:12.516 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24370 21:47:12.516 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24371 21:47:12.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24372 21:47:12.516 0.00033185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24373 21:47:12.516 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24374 21:47:12.516 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24375 21:47:12.516 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24376 21:47:12.516 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24377 21:47:12.516 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24378 21:47:12.516 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24379 21:47:12.516 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24380 21:47:12.516 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24381 21:47:12.516 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24382 21:47:12.516 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24383 21:47:12.516 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24384 21:47:12.516 0.00033185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24385 21:47:12.516 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24386 21:47:12.516 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24387 21:47:12.516 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24388 21:47:12.516 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24389 21:47:12.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24390 21:47:12.516 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24391 21:47:12.516 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24392 21:47:12.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24393 21:47:12.516 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24394 21:47:12.516 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24395 21:47:12.516 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24396 21:47:12.516 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24397 21:47:12.516 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24398 21:47:12.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24399 21:47:12.516 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24400 21:47:12.516 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24401 21:47:12.516 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24402 21:47:12.516 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24403 21:47:12.516 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24404 21:47:12.516 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24405 21:47:12.516 0.00028563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24406 21:47:12.516 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24407 21:47:12.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24408 21:47:12.516 0.02580939 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24409 21:47:12.547 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24410 21:47:12.547 0.01328593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24411 21:47:12.547 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24412 21:47:12.563 0.00029709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24413 21:47:12.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24414 21:47:12.563 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24415 21:47:12.563 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24416 21:47:12.563 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24417 21:47:12.563 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24418 21:47:12.563 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24419 21:47:12.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24420 21:47:12.563 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24421 21:47:12.563 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 24422 21:47:12.563 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24423 21:47:12.563 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24424 21:47:12.563 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24425 21:47:12.563 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24426 21:47:12.563 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24427 21:47:12.563 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24428 21:47:12.563 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24429 21:47:12.563 0.00021768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24430 21:47:12.563 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24431 21:47:12.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24432 21:47:12.563 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24433 21:47:12.563 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24434 21:47:12.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24435 21:47:12.563 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24436 21:47:12.563 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24437 21:47:12.563 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24438 21:47:12.563 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24439 21:47:12.563 0.00023230 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24440 21:47:12.563 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24441 21:47:12.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24442 21:47:12.563 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24443 21:47:12.563 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24444 21:47:12.563 0.00014380 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24445 21:47:12.563 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24446 21:47:12.563 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24447 21:47:12.563 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24448 21:47:12.563 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24449 21:47:12.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24450 21:47:12.563 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24451 21:47:12.563 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24452 21:47:12.563 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24453 21:47:12.563 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24454 21:47:12.563 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24455 21:47:12.563 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24456 21:47:12.563 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24457 21:47:12.563 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24458 21:47:12.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24459 21:47:12.563 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24460 21:47:12.563 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24461 21:47:12.563 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24462 21:47:12.563 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24463 21:47:12.563 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24464 21:47:12.563 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24465 21:47:12.563 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24466 21:47:12.563 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24467 21:47:12.563 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24468 21:47:12.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24469 21:47:12.563 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24470 21:47:12.563 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 24471 21:47:12.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24472 21:47:12.563 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 24475 21:47:12.594 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24476 21:47:12.594 0.01249146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24477 21:47:12.594 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24478 21:47:12.609 0.00029156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24479 21:47:12.609 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24480 21:47:12.609 0.00031723 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24481 21:47:12.609 0.00027338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24482 21:47:12.609 0.00034331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 24483 21:47:12.609 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24484 21:47:12.609 0.00029590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24485 21:47:12.609 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24486 21:47:12.609 0.00039901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24487 21:47:12.609 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 24488 21:47:12.609 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24489 21:47:12.609 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24490 21:47:12.609 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24491 21:47:12.609 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24492 21:47:12.609 0.00026232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24493 21:47:12.609 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24494 21:47:12.609 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24495 21:47:12.609 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24496 21:47:12.609 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24497 21:47:12.609 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24498 21:47:12.609 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24499 21:47:12.609 0.00009916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24500 21:47:12.609 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24501 21:47:12.609 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24502 21:47:12.609 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24503 21:47:12.609 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24504 21:47:12.609 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24505 21:47:12.609 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24506 21:47:12.609 0.00035674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24507 21:47:12.609 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24508 21:47:12.609 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24509 21:47:12.609 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24510 21:47:12.609 0.00032198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24511 21:47:12.609 0.00025877 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24512 21:47:12.609 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24513 21:47:12.609 0.00032553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24514 21:47:12.609 0.00025719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24515 21:47:12.609 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24516 21:47:12.609 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24517 21:47:12.609 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24518 21:47:12.609 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24519 21:47:12.609 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24520 21:47:12.609 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24521 21:47:12.609 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24522 21:47:12.609 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24523 21:47:12.609 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24524 21:47:12.609 0.00008178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24525 21:47:12.609 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24526 21:47:12.609 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24527 21:47:12.609 0.00009126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24528 21:47:12.609 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24529 21:47:12.609 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24530 21:47:12.609 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24531 21:47:12.609 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24532 21:47:12.609 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24533 21:47:12.609 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24534 21:47:12.609 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24535 21:47:12.609 0.00023743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24536 21:47:12.609 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24537 21:47:12.609 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24538 21:47:12.609 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24539 21:47:12.609 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24540 21:47:12.609 0.02579715 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24541 21:47:12.641 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24542 21:47:12.641 0.01426252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24543 21:47:12.641 0.00003674 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24544 21:47:12.656 0.00040375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24545 21:47:12.656 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24546 21:47:12.656 0.00035951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24547 21:47:12.656 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24548 21:47:12.656 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24549 21:47:12.656 0.00038795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24550 21:47:12.656 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24551 21:47:12.656 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 24552 21:47:12.656 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24553 21:47:12.656 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24554 21:47:12.656 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24555 21:47:12.656 0.00030183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24556 21:47:12.656 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24557 21:47:12.656 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24558 21:47:12.656 0.00041126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24559 21:47:12.656 0.00041402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24560 21:47:12.656 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24561 21:47:12.656 0.00037333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24562 21:47:12.656 0.00041126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24563 21:47:12.656 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24564 21:47:12.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24565 21:47:12.656 0.00015605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24566 21:47:12.656 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24567 21:47:12.656 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24568 21:47:12.656 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24569 21:47:12.656 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24570 21:47:12.656 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24571 21:47:12.656 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24572 21:47:12.656 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24573 21:47:12.656 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24574 21:47:12.656 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24575 21:47:12.656 0.00029037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24576 21:47:12.656 0.00034805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24577 21:47:12.656 0.00024533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24578 21:47:12.656 0.00027654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24579 21:47:12.656 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24580 21:47:12.656 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24581 21:47:12.656 0.00023309 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24582 21:47:12.656 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24583 21:47:12.656 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24584 21:47:12.656 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24585 21:47:12.656 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24586 21:47:12.656 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24587 21:47:12.656 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24588 21:47:12.656 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24589 21:47:12.656 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24590 21:47:12.656 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24591 21:47:12.656 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24592 21:47:12.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24593 21:47:12.656 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24594 21:47:12.656 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24596 21:47:12.656 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24597 21:47:12.656 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24598 21:47:12.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24599 21:47:12.656 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24600 21:47:12.656 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24601 21:47:12.656 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24602 21:47:12.656 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24603 21:47:12.656 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24604 21:47:12.656 0.02659557 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24605 21:47:12.687 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24606 21:47:12.687 0.01373630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24607 21:47:12.687 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24608 21:47:12.703 0.00067793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24609 21:47:12.703 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24610 21:47:12.703 0.00023862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24611 21:47:12.703 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24612 21:47:12.703 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 0B 24613 21:47:12.703 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24615 21:47:12.703 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24616 21:47:12.703 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24617 21:47:12.703 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 24618 21:47:12.703 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24619 21:47:12.703 0.00034173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24620 21:47:12.703 0.00019832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24621 21:47:12.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24622 21:47:12.703 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24623 21:47:12.703 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24624 21:47:12.703 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24625 21:47:12.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24626 21:47:12.703 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24627 21:47:12.703 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24628 21:47:12.703 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24629 21:47:12.703 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24630 21:47:12.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24631 21:47:12.703 0.00016988 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24632 21:47:12.703 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24633 21:47:12.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24634 21:47:12.703 0.00017264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24635 21:47:12.703 0.00014854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24636 21:47:12.703 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24637 21:47:12.703 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24638 21:47:12.703 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24639 21:47:12.703 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24640 21:47:12.703 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24641 21:47:12.703 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24642 21:47:12.703 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24643 21:47:12.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24644 21:47:12.703 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24645 21:47:12.703 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24646 21:47:12.703 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24647 21:47:12.703 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24648 21:47:12.703 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24649 21:47:12.703 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24650 21:47:12.703 0.00016435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24651 21:47:12.703 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24652 21:47:12.703 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24653 21:47:12.703 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24654 21:47:12.703 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24655 21:47:12.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24656 21:47:12.703 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24657 21:47:12.703 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24658 21:47:12.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24659 21:47:12.703 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24660 21:47:12.703 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24661 21:47:12.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24662 21:47:12.703 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24663 21:47:12.703 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24664 21:47:12.703 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24665 21:47:12.703 0.00008810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24666 21:47:12.703 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24667 21:47:12.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24668 21:47:12.703 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24669 21:47:12.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24670 21:47:12.703 0.02825957 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24671 21:47:12.734 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24672 21:47:12.734 0.00033225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24673 21:47:12.734 0.01248396 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24674 21:47:12.750 0.00032672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24675 21:47:12.750 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24676 21:47:12.750 0.00053136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24677 21:47:12.750 0.00045867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24678 21:47:12.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24679 21:47:12.750 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24680 21:47:12.750 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24681 21:47:12.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24682 21:47:12.750 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 24683 21:47:12.750 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24684 21:47:12.750 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24685 21:47:12.750 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 10 24686 21:47:12.750 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 24688 21:47:12.750 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24689 21:47:12.750 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24690 21:47:12.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24691 21:47:12.750 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24692 21:47:12.750 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24693 21:47:12.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24694 21:47:12.750 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24695 21:47:12.750 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24696 21:47:12.750 0.00003753 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24697 21:47:12.750 0.00018884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24698 21:47:12.750 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24699 21:47:12.750 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24700 21:47:12.750 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24701 21:47:12.750 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24702 21:47:12.750 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24703 21:47:12.750 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24704 21:47:12.750 0.00009165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24705 21:47:12.750 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24706 21:47:12.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24707 21:47:12.750 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24708 21:47:12.750 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24709 21:47:12.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24710 21:47:12.750 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24711 21:47:12.750 0.00010193 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24712 21:47:12.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24713 21:47:12.750 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24714 21:47:12.750 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24715 21:47:12.750 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24716 21:47:12.750 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24717 21:47:12.750 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24718 21:47:12.750 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24719 21:47:12.750 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24720 21:47:12.750 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24721 21:47:12.750 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24722 21:47:12.750 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24723 21:47:12.750 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24724 21:47:12.750 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24725 21:47:12.750 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24726 21:47:12.750 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24727 21:47:12.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24728 21:47:12.750 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24729 21:47:12.750 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24730 21:47:12.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24731 21:47:12.750 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24732 21:47:12.750 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24733 21:47:12.750 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24734 21:47:12.750 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24735 21:47:12.750 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24736 21:47:12.750 0.02861117 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24737 21:47:12.781 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24738 21:47:12.781 0.01303072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24739 21:47:12.781 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24740 21:47:12.797 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24741 21:47:12.797 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24742 21:47:12.797 0.00028168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24743 21:47:12.797 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24744 21:47:12.797 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24745 21:47:12.797 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 24746 21:47:12.797 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24747 21:47:12.797 0.00021847 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 24748 21:47:12.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24749 21:47:12.797 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24750 21:47:12.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24751 21:47:12.797 0.00022756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24752 21:47:12.797 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24753 21:47:12.797 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24754 21:47:12.797 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24755 21:47:12.797 0.00024415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24756 21:47:12.797 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24757 21:47:12.797 0.00031407 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24758 21:47:12.797 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24759 21:47:12.797 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24760 21:47:12.797 0.00017699 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24761 21:47:12.797 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24762 21:47:12.797 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24763 21:47:12.797 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24764 21:47:12.797 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 24765 21:47:12.797 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 24767 21:47:12.797 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24768 21:47:12.797 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24769 21:47:12.797 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24770 21:47:12.797 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24771 21:47:12.797 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24772 21:47:12.797 0.00008059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24773 21:47:12.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24774 21:47:12.797 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24775 21:47:12.797 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24776 21:47:12.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24777 21:47:12.797 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24778 21:47:12.797 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24779 21:47:12.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24780 21:47:12.797 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24781 21:47:12.797 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24782 21:47:12.797 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24783 21:47:12.797 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24784 21:47:12.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24785 21:47:12.797 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24786 21:47:12.797 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24787 21:47:12.797 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24788 21:47:12.797 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24789 21:47:12.797 0.00011931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24790 21:47:12.797 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24791 21:47:12.797 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24792 21:47:12.797 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24793 21:47:12.797 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24794 21:47:12.797 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24795 21:47:12.797 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24796 21:47:12.797 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24797 21:47:12.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24798 21:47:12.797 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24799 21:47:12.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24800 21:47:12.797 0.02743270 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24801 21:47:12.828 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24802 21:47:12.828 0.01380228 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24803 21:47:12.828 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24804 21:47:12.844 0.00032395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24805 21:47:12.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24806 21:47:12.844 0.00038558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24807 21:47:12.844 0.00028049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24808 21:47:12.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24809 21:47:12.844 0.00045116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24810 21:47:12.844 0.00037689 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24811 21:47:12.844 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24812 21:47:12.844 0.00026469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24813 21:47:12.844 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 24814 21:47:12.844 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24815 21:47:12.844 0.00024257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24816 21:47:12.844 0.00032474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24817 21:47:12.844 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24818 21:47:12.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24819 21:47:12.844 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24820 21:47:12.844 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24821 21:47:12.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24822 21:47:12.844 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24823 21:47:12.844 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24824 21:47:12.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24825 21:47:12.844 0.00014617 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24826 21:47:12.844 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24827 21:47:12.844 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24828 21:47:12.844 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24829 21:47:12.844 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24830 21:47:12.844 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24831 21:47:12.844 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24832 21:47:12.844 0.00030025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24833 21:47:12.844 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24834 21:47:12.844 0.00017541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24835 21:47:12.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24836 21:47:12.844 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24837 21:47:12.844 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24838 21:47:12.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24839 21:47:12.844 0.00032790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24840 21:47:12.844 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24841 21:47:12.844 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24842 21:47:12.844 0.00044168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24843 21:47:12.844 0.00033659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24844 21:47:12.844 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24845 21:47:12.844 0.00039348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24846 21:47:12.844 0.00034212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24847 21:47:12.844 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24848 21:47:12.844 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24849 21:47:12.844 0.00034054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24850 21:47:12.844 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24851 21:47:12.844 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24853 21:47:12.844 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24854 21:47:12.844 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24855 21:47:12.844 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24856 21:47:12.844 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24857 21:47:12.844 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24858 21:47:12.844 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24859 21:47:12.844 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24860 21:47:12.844 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24861 21:47:12.844 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24862 21:47:12.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24863 21:47:12.844 0.00027694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24864 21:47:12.844 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24865 21:47:12.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24866 21:47:12.844 0.02649483 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24867 21:47:12.875 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24868 21:47:12.875 0.01528020 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24869 21:47:12.875 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24870 21:47:12.893 0.00035911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24871 21:47:12.893 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24872 21:47:12.893 0.00034805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24873 21:47:12.893 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24874 21:47:12.893 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24875 21:47:12.893 0.00016435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24876 21:47:12.893 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 24877 21:47:12.893 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24878 21:47:12.893 0.00035002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24879 21:47:12.893 0.00029353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 24880 21:47:12.893 0.00028484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24881 21:47:12.893 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24882 21:47:12.893 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24883 21:47:12.893 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24884 21:47:12.893 0.00034805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24885 21:47:12.893 0.00029037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24886 21:47:12.893 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24887 21:47:12.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24888 21:47:12.893 0.00010864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24889 21:47:12.893 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24890 21:47:12.893 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24891 21:47:12.893 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24892 21:47:12.893 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24893 21:47:12.893 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24895 21:47:12.893 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24896 21:47:12.893 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24897 21:47:12.893 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24898 21:47:12.893 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24899 21:47:12.893 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24900 21:47:12.893 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24901 21:47:12.893 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24902 21:47:12.893 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24903 21:47:12.893 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24904 21:47:12.893 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24905 21:47:12.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24906 21:47:12.893 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24907 21:47:12.893 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24908 21:47:12.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24909 21:47:12.893 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24910 21:47:12.893 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24911 21:47:12.893 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24912 21:47:12.893 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24913 21:47:12.893 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24914 21:47:12.893 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24915 21:47:12.893 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24916 21:47:12.893 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24917 21:47:12.893 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24918 21:47:12.893 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24919 21:47:12.893 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24920 21:47:12.893 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24921 21:47:12.893 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24922 21:47:12.893 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24923 21:47:12.893 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24924 21:47:12.893 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24925 21:47:12.893 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24926 21:47:12.893 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24927 21:47:12.893 0.00014064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24928 21:47:12.893 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24929 21:47:12.893 0.00036583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24930 21:47:12.893 0.00029946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24931 21:47:12.893 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24932 21:47:12.893 0.02747695 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24933 21:47:12.922 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24934 21:47:12.922 0.00969008 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24935 21:47:12.922 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 24936 21:47:12.938 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 24937 21:47:12.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24938 21:47:12.938 0.00034331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24939 21:47:12.938 0.00014894 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 24940 21:47:12.938 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24941 21:47:12.938 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24942 21:47:12.938 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 24943 21:47:12.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24944 21:47:12.938 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: B0 24945 21:47:12.938 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24946 21:47:12.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24947 21:47:12.938 0.00018370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24948 21:47:12.938 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 24949 21:47:12.938 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24950 21:47:12.938 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24951 21:47:12.938 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24952 21:47:12.938 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24953 21:47:12.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24954 21:47:12.938 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24955 21:47:12.938 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24956 21:47:12.938 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24957 21:47:12.938 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24958 21:47:12.938 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24959 21:47:12.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24960 21:47:12.938 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24961 21:47:12.938 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24962 21:47:12.938 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24963 21:47:12.938 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24964 21:47:12.938 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24965 21:47:12.938 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24966 21:47:12.938 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24967 21:47:12.938 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24968 21:47:12.938 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24969 21:47:12.938 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24970 21:47:12.938 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24971 21:47:12.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24972 21:47:12.938 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24973 21:47:12.938 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24974 21:47:12.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24975 21:47:12.938 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24976 21:47:12.938 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24977 21:47:12.938 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24978 21:47:12.938 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24979 21:47:12.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24980 21:47:12.938 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24981 21:47:12.938 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24982 21:47:12.938 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24983 21:47:12.938 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24984 21:47:12.938 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24985 21:47:12.938 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24986 21:47:12.938 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24987 21:47:12.938 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24988 21:47:12.938 0.00078380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24989 21:47:12.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24990 21:47:12.938 0.00073165 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24991 21:47:12.938 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24992 21:47:12.938 0.00024257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24993 21:47:12.938 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24994 21:47:12.938 0.00019240 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 24995 21:47:12.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24996 21:47:12.938 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24997 21:47:12.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 24998 21:47:12.938 0.02687566 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24999 21:47:12.969 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25000 21:47:12.969 0.01406657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25001 21:47:12.969 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25002 21:47:12.984 0.00027654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25003 21:47:12.984 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25004 21:47:12.984 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25005 21:47:12.984 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25006 21:47:12.984 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25007 21:47:12.984 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25008 21:47:12.984 0.00021728 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 25009 21:47:12.984 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25010 21:47:12.984 0.00044563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25011 21:47:12.984 0.00041640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 25012 21:47:12.984 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25013 21:47:12.984 0.00029630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25014 21:47:12.984 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25015 21:47:12.984 0.00020030 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25016 21:47:12.984 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25017 21:47:12.984 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25018 21:47:12.984 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25019 21:47:12.984 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25020 21:47:12.984 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25021 21:47:12.984 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25022 21:47:12.984 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25023 21:47:12.984 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25024 21:47:12.984 0.00030301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25025 21:47:12.984 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25026 21:47:12.984 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25027 21:47:12.984 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25028 21:47:12.984 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25029 21:47:12.984 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25030 21:47:12.984 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25031 21:47:12.984 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25032 21:47:12.984 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25033 21:47:12.984 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25034 21:47:12.984 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25035 21:47:12.984 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25036 21:47:12.984 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25037 21:47:12.984 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25038 21:47:12.984 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25039 21:47:12.984 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25040 21:47:12.984 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25041 21:47:12.984 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25042 21:47:12.984 0.00009165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25043 21:47:12.984 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25044 21:47:12.984 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25045 21:47:12.984 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25046 21:47:12.984 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25047 21:47:12.984 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25048 21:47:12.984 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25049 21:47:12.984 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25050 21:47:12.984 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25051 21:47:12.984 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25052 21:47:12.984 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25053 21:47:12.984 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25054 21:47:12.984 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25055 21:47:12.984 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25056 21:47:12.984 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25057 21:47:12.984 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25058 21:47:12.984 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25059 21:47:12.984 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25060 21:47:12.984 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25062 21:47:12.984 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25063 21:47:12.984 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25064 21:47:12.984 0.02750737 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25065 21:47:13.016 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25066 21:47:13.016 0.01358973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25067 21:47:13.016 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25068 21:47:13.032 0.00038044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25069 21:47:13.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25070 21:47:13.032 0.00020030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25071 21:47:13.032 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25072 21:47:13.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25073 21:47:13.032 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25074 21:47:13.032 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 25075 21:47:13.032 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25076 21:47:13.032 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 25077 21:47:13.032 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25078 21:47:13.032 0.00008889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25079 21:47:13.032 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25080 21:47:13.032 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25081 21:47:13.032 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25082 21:47:13.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25083 21:47:13.032 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25084 21:47:13.032 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25085 21:47:13.032 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25086 21:47:13.032 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25087 21:47:13.032 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25088 21:47:13.032 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25089 21:47:13.032 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25090 21:47:13.032 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25091 21:47:13.032 0.00018647 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25092 21:47:13.032 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25093 21:47:13.032 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25094 21:47:13.032 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25095 21:47:13.032 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25096 21:47:13.032 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25097 21:47:13.032 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25098 21:47:13.032 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25099 21:47:13.032 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25100 21:47:13.032 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25101 21:47:13.032 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25102 21:47:13.032 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25103 21:47:13.032 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25104 21:47:13.032 0.00032435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25106 21:47:13.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25107 21:47:13.032 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25108 21:47:13.032 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25109 21:47:13.032 0.00014538 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25110 21:47:13.032 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25111 21:47:13.032 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25112 21:47:13.032 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25113 21:47:13.032 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25114 21:47:13.032 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25115 21:47:13.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25116 21:47:13.032 0.00004504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25117 21:47:13.032 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25118 21:47:13.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25119 21:47:13.032 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25120 21:47:13.032 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25121 21:47:13.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25122 21:47:13.032 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25123 21:47:13.032 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25124 21:47:13.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25125 21:47:13.032 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25126 21:47:13.032 0.00012681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25127 21:47:13.032 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25128 21:47:13.032 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25129 21:47:13.032 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25130 21:47:13.032 0.02843023 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25131 21:47:13.063 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25132 21:47:13.063 0.01379991 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25133 21:47:13.063 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25134 21:47:13.079 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25135 21:47:13.079 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25136 21:47:13.079 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25137 21:47:13.079 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25138 21:47:13.079 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 25139 21:47:13.079 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25140 21:47:13.079 0.00015605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25141 21:47:13.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25142 21:47:13.079 0.00016514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 25143 21:47:13.079 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25144 21:47:13.079 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25146 21:47:13.079 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25147 21:47:13.079 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25148 21:47:13.079 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25149 21:47:13.079 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25150 21:47:13.079 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25151 21:47:13.079 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25152 21:47:13.079 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25153 21:47:13.079 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25154 21:47:13.079 0.00032869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25155 21:47:13.079 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25156 21:47:13.079 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25157 21:47:13.079 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25158 21:47:13.079 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25159 21:47:13.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25160 21:47:13.079 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25161 21:47:13.079 0.00028326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25162 21:47:13.079 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25163 21:47:13.079 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25164 21:47:13.079 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25165 21:47:13.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25166 21:47:13.079 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25167 21:47:13.079 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25168 21:47:13.079 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25169 21:47:13.079 0.00013195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25170 21:47:13.079 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25171 21:47:13.079 0.00008533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25172 21:47:13.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25173 21:47:13.079 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25174 21:47:13.079 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25175 21:47:13.079 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25176 21:47:13.079 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25177 21:47:13.079 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25178 21:47:13.079 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25179 21:47:13.079 0.00009719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25180 21:47:13.079 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25181 21:47:13.079 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25182 21:47:13.079 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25183 21:47:13.079 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25184 21:47:13.079 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25185 21:47:13.079 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25186 21:47:13.079 0.00008849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25187 21:47:13.079 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25188 21:47:13.079 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25189 21:47:13.079 0.00008336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25190 21:47:13.079 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25191 21:47:13.079 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25192 21:47:13.079 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25193 21:47:13.079 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25194 21:47:13.079 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25195 21:47:13.079 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25196 21:47:13.079 0.02830105 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25197 21:47:13.110 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25198 21:47:13.110 0.01302361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25199 21:47:13.110 0.00001738 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25200 21:47:13.126 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25201 21:47:13.126 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25202 21:47:13.126 0.00023941 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25203 21:47:13.126 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25204 21:47:13.126 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25205 21:47:13.126 0.00038716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 25206 21:47:13.126 0.00043378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25207 21:47:13.126 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 25208 21:47:13.126 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25209 21:47:13.126 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25210 21:47:13.126 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25211 21:47:13.126 0.00041244 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25212 21:47:13.126 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25213 21:47:13.126 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25214 21:47:13.126 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25215 21:47:13.126 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25216 21:47:13.126 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25217 21:47:13.126 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25218 21:47:13.126 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25219 21:47:13.126 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25220 21:47:13.126 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25221 21:47:13.126 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25222 21:47:13.126 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25223 21:47:13.126 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25224 21:47:13.126 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25225 21:47:13.126 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25226 21:47:13.126 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25227 21:47:13.126 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25228 21:47:13.126 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25229 21:47:13.126 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25230 21:47:13.126 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25231 21:47:13.126 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25232 21:47:13.126 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25233 21:47:13.126 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25234 21:47:13.126 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25235 21:47:13.126 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25236 21:47:13.126 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25237 21:47:13.126 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25238 21:47:13.126 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25239 21:47:13.126 0.00014696 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25240 21:47:13.126 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25241 21:47:13.126 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25242 21:47:13.126 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25243 21:47:13.126 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25244 21:47:13.126 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25245 21:47:13.126 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25246 21:47:13.126 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25247 21:47:13.126 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25248 21:47:13.126 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25249 21:47:13.126 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25250 21:47:13.126 0.00020148 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25251 21:47:13.126 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25252 21:47:13.126 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25253 21:47:13.126 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25254 21:47:13.126 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25255 21:47:13.126 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25256 21:47:13.126 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25257 21:47:13.126 0.00028998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25258 21:47:13.126 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25259 21:47:13.126 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25260 21:47:13.126 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25261 21:47:13.126 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25262 21:47:13.126 0.02781157 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25263 21:47:13.157 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25264 21:47:13.157 0.01324998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25266 21:47:13.172 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25267 21:47:13.172 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25268 21:47:13.172 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25269 21:47:13.172 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25270 21:47:13.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25271 21:47:13.172 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0B 25272 21:47:13.172 0.00020188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25273 21:47:13.172 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 25274 21:47:13.172 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25275 21:47:13.172 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25276 21:47:13.172 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25277 21:47:13.172 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25278 21:47:13.172 0.00016830 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25279 21:47:13.172 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25280 21:47:13.172 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25281 21:47:13.172 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25282 21:47:13.172 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25283 21:47:13.172 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25284 21:47:13.172 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25286 21:47:13.172 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25287 21:47:13.172 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25288 21:47:13.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25289 21:47:13.172 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25290 21:47:13.172 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25291 21:47:13.172 0.00023625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25292 21:47:13.172 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25293 21:47:13.172 0.00017304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25294 21:47:13.172 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25295 21:47:13.172 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25296 21:47:13.172 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25297 21:47:13.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25298 21:47:13.172 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25299 21:47:13.172 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25300 21:47:13.172 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25301 21:47:13.172 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25302 21:47:13.172 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25303 21:47:13.172 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25304 21:47:13.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25305 21:47:13.172 0.00007901 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25306 21:47:13.172 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25307 21:47:13.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25308 21:47:13.172 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25309 21:47:13.172 0.00008296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25310 21:47:13.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25311 21:47:13.172 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25312 21:47:13.172 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25313 21:47:13.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25314 21:47:13.172 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25315 21:47:13.172 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25316 21:47:13.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25317 21:47:13.172 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25318 21:47:13.172 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25319 21:47:13.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25320 21:47:13.172 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25321 21:47:13.172 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25322 21:47:13.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25323 21:47:13.172 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25324 21:47:13.172 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25325 21:47:13.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25326 21:47:13.172 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25327 21:47:13.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25328 21:47:13.172 0.02784278 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25329 21:47:13.204 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25330 21:47:13.204 0.01343684 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25331 21:47:13.204 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25332 21:47:13.219 0.00043022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25333 21:47:13.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25334 21:47:13.219 0.00041086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25335 21:47:13.219 0.00036504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25336 21:47:13.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25337 21:47:13.219 0.00035279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25338 21:47:13.219 0.00031170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1B 25339 21:47:13.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25340 21:47:13.219 0.00034015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25341 21:47:13.219 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 25342 21:47:13.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25343 21:47:13.219 0.00031368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25344 21:47:13.219 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25345 21:47:13.219 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25346 21:47:13.219 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25347 21:47:13.219 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25348 21:47:13.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25349 21:47:13.219 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25350 21:47:13.219 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25351 21:47:13.219 0.00004464 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25352 21:47:13.219 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25353 21:47:13.219 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25354 21:47:13.219 0.00012563 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25355 21:47:13.219 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25356 21:47:13.219 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25357 21:47:13.219 0.00017541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25358 21:47:13.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25359 21:47:13.219 0.00014183 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25360 21:47:13.219 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25361 21:47:13.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25362 21:47:13.219 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25363 21:47:13.219 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25364 21:47:13.219 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25365 21:47:13.219 0.00015210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25366 21:47:13.219 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25367 21:47:13.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25368 21:47:13.219 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25369 21:47:13.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25370 21:47:13.219 0.00024296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25371 21:47:13.219 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25372 21:47:13.219 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25373 21:47:13.219 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25374 21:47:13.219 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25375 21:47:13.219 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25376 21:47:13.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25377 21:47:13.219 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25378 21:47:13.219 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25379 21:47:13.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25380 21:47:13.219 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25381 21:47:13.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25382 21:47:13.219 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25383 21:47:13.219 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25384 21:47:13.219 0.00015644 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25385 21:47:13.219 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25386 21:47:13.219 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25387 21:47:13.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25388 21:47:13.219 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25389 21:47:13.219 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25390 21:47:13.219 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25391 21:47:13.219 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25392 21:47:13.219 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25393 21:47:13.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25394 21:47:13.219 0.02752238 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25395 21:47:13.250 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25396 21:47:13.250 0.01253373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25397 21:47:13.250 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25398 21:47:13.266 0.00032237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25399 21:47:13.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25400 21:47:13.266 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25401 21:47:13.266 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25402 21:47:13.266 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25403 21:47:13.266 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 0B 25408 21:47:13.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25409 21:47:13.266 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25410 21:47:13.266 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25411 21:47:13.266 0.00019951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25412 21:47:13.266 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25413 21:47:13.266 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25414 21:47:13.266 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25415 21:47:13.266 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25416 21:47:13.266 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25417 21:47:13.266 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25418 21:47:13.266 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25419 21:47:13.266 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25420 21:47:13.266 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25421 21:47:13.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25422 21:47:13.266 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25423 21:47:13.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25424 21:47:13.266 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25425 21:47:13.266 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25426 21:47:13.266 0.00024849 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25427 21:47:13.266 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25428 21:47:13.266 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25429 21:47:13.266 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25430 21:47:13.266 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25431 21:47:13.266 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25432 21:47:13.266 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25433 21:47:13.266 0.00007309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25434 21:47:13.266 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25435 21:47:13.266 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25436 21:47:13.266 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25437 21:47:13.266 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25438 21:47:13.266 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25439 21:47:13.266 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25440 21:47:13.266 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25441 21:47:13.266 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25442 21:47:13.266 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25443 21:47:13.266 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25444 21:47:13.266 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25445 21:47:13.266 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25446 21:47:13.266 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25447 21:47:13.266 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25448 21:47:13.266 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25449 21:47:13.266 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25450 21:47:13.266 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25451 21:47:13.266 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25452 21:47:13.266 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25453 21:47:13.266 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25454 21:47:13.266 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25455 21:47:13.266 0.00012760 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25456 21:47:13.266 0.00007980 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25457 21:47:13.266 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25458 21:47:13.266 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25459 21:47:13.266 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25460 21:47:13.266 0.02781117 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25461 21:47:13.297 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25462 21:47:13.297 0.01300504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25463 21:47:13.297 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25464 21:47:13.313 0.00036425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25465 21:47:13.313 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25466 21:47:13.313 0.00038677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25467 21:47:13.313 0.00025600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25468 21:47:13.313 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 1B 25469 21:47:13.313 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25470 21:47:13.313 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 25474 21:47:13.313 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25475 21:47:13.313 0.00031842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25476 21:47:13.313 0.00026785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25477 21:47:13.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25478 21:47:13.313 0.00026588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25479 21:47:13.313 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25480 21:47:13.313 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25481 21:47:13.313 0.00034528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25482 21:47:13.313 0.00026706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25483 21:47:13.313 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25484 21:47:13.313 0.00032711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25485 21:47:13.313 0.00025481 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25486 21:47:13.313 0.00038005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25487 21:47:13.313 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25488 21:47:13.313 0.00030104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25489 21:47:13.313 0.00038321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25490 21:47:13.313 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25491 21:47:13.313 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25492 21:47:13.313 0.00032435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25493 21:47:13.313 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25494 21:47:13.313 0.00013906 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25495 21:47:13.313 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25496 21:47:13.313 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25497 21:47:13.313 0.00031012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25498 21:47:13.313 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25499 21:47:13.313 0.00023072 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25500 21:47:13.313 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25501 21:47:13.313 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25502 21:47:13.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25503 21:47:13.313 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25504 21:47:13.313 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25505 21:47:13.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25506 21:47:13.313 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25507 21:47:13.313 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25508 21:47:13.313 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25509 21:47:13.313 0.00036978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25510 21:47:13.313 0.00020109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25511 21:47:13.313 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25512 21:47:13.313 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25513 21:47:13.313 0.00010153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25514 21:47:13.313 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25515 21:47:13.313 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25516 21:47:13.313 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25517 21:47:13.313 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25518 21:47:13.313 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25519 21:47:13.313 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25520 21:47:13.313 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25521 21:47:13.313 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25522 21:47:13.313 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25523 21:47:13.313 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25524 21:47:13.313 0.02587339 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25525 21:47:13.344 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25526 21:47:13.344 0.01337956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25527 21:47:13.344 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25528 21:47:13.359 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25529 21:47:13.359 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25530 21:47:13.359 0.00025521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25531 21:47:13.359 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25532 21:47:13.359 0.00104454 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25533 21:47:13.359 0.00108958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 25534 21:47:13.359 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25535 21:47:13.359 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25536 21:47:13.359 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 25537 21:47:13.359 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25538 21:47:13.359 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25539 21:47:13.359 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25540 21:47:13.359 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25541 21:47:13.359 0.00020109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25542 21:47:13.359 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25543 21:47:13.359 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25544 21:47:13.359 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25545 21:47:13.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25546 21:47:13.359 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25547 21:47:13.359 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25548 21:47:13.359 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25549 21:47:13.359 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25550 21:47:13.359 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25551 21:47:13.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25552 21:47:13.359 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25553 21:47:13.359 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25554 21:47:13.359 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25555 21:47:13.359 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25556 21:47:13.359 0.00008454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25557 21:47:13.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25558 21:47:13.359 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25559 21:47:13.359 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25560 21:47:13.359 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25561 21:47:13.359 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25562 21:47:13.359 0.00030183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25563 21:47:13.359 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25564 21:47:13.359 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25565 21:47:13.359 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25566 21:47:13.359 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25567 21:47:13.359 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25568 21:47:13.359 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25569 21:47:13.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25570 21:47:13.359 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25571 21:47:13.359 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25572 21:47:13.359 0.00023467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25573 21:47:13.359 0.00024731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25574 21:47:13.359 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25575 21:47:13.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25576 21:47:13.359 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25577 21:47:13.359 0.00010272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25578 21:47:13.359 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25579 21:47:13.359 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25580 21:47:13.359 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25581 21:47:13.359 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25582 21:47:13.359 0.00006835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25583 21:47:13.359 0.00007941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25584 21:47:13.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25585 21:47:13.359 0.00005926 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25586 21:47:13.359 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25587 21:47:13.359 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25588 21:47:13.359 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25589 21:47:13.359 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25590 21:47:13.359 0.02669552 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25591 21:47:13.391 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25592 21:47:13.391 0.01446322 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25593 21:47:13.391 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25594 21:47:13.406 0.00032474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25595 21:47:13.406 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25596 21:47:13.406 0.00030736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25597 21:47:13.406 0.00032909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25598 21:47:13.406 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25599 21:47:13.406 0.00044089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25600 21:47:13.406 0.00032514 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 25601 21:47:13.406 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25602 21:47:13.406 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 25603 21:47:13.406 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25604 21:47:13.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25605 21:47:13.406 0.00030854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25606 21:47:13.406 0.00028247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25607 21:47:13.406 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25608 21:47:13.406 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25609 21:47:13.406 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25610 21:47:13.406 0.00026311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25611 21:47:13.406 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25612 21:47:13.406 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25613 21:47:13.406 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25614 21:47:13.406 0.00009837 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25615 21:47:13.406 0.00011536 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25616 21:47:13.406 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25617 21:47:13.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25618 21:47:13.406 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25619 21:47:13.406 0.00000079 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25620 21:47:13.406 0.00027141 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25621 21:47:13.406 0.00015684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25622 21:47:13.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25623 21:47:13.406 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25624 21:47:13.406 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25625 21:47:13.406 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25626 21:47:13.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25627 21:47:13.406 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25628 21:47:13.406 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25629 21:47:13.406 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25630 21:47:13.406 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25631 21:47:13.406 0.00016237 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25632 21:47:13.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25633 21:47:13.406 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25634 21:47:13.406 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25635 21:47:13.406 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25636 21:47:13.406 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25637 21:47:13.406 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25638 21:47:13.406 0.00021649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25639 21:47:13.406 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25640 21:47:13.406 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25641 21:47:13.406 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25642 21:47:13.406 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25643 21:47:13.406 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25644 21:47:13.406 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25645 21:47:13.406 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25646 21:47:13.406 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25647 21:47:13.406 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25648 21:47:13.406 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25649 21:47:13.406 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25650 21:47:13.406 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25651 21:47:13.406 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25652 21:47:13.406 0.00008652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25653 21:47:13.406 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25654 21:47:13.406 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25655 21:47:13.406 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25656 21:47:13.406 0.02711626 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25657 21:47:13.438 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25658 21:47:13.438 0.01324524 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25659 21:47:13.438 0.00001817 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25660 21:47:13.453 0.00028484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25661 21:47:13.453 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25662 21:47:13.453 0.00023625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25663 21:47:13.453 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25664 21:47:13.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25665 21:47:13.453 0.00104573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25666 21:47:13.453 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 25667 21:47:13.453 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25668 21:47:13.453 0.00034331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25669 21:47:13.453 0.00028523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25670 21:47:13.453 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25671 21:47:13.453 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25672 21:47:13.453 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25673 21:47:13.453 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25674 21:47:13.453 0.00030064 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25675 21:47:13.453 0.00026390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25676 21:47:13.453 0.00023269 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25677 21:47:13.453 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25678 21:47:13.453 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25679 21:47:13.453 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25680 21:47:13.453 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25681 21:47:13.453 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25682 21:47:13.453 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25683 21:47:13.453 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25684 21:47:13.453 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25685 21:47:13.453 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25686 21:47:13.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25687 21:47:13.453 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25688 21:47:13.453 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25689 21:47:13.453 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25690 21:47:13.453 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25691 21:47:13.453 0.00021768 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25692 21:47:13.453 0.00011891 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25693 21:47:13.453 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25694 21:47:13.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25695 21:47:13.453 0.00015368 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25696 21:47:13.453 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25697 21:47:13.453 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25698 21:47:13.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25699 21:47:13.453 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25700 21:47:13.453 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25701 21:47:13.453 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25702 21:47:13.453 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25703 21:47:13.453 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25704 21:47:13.453 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25705 21:47:13.453 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25706 21:47:13.453 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25707 21:47:13.453 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25708 21:47:13.453 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25709 21:47:13.453 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25710 21:47:13.453 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25711 21:47:13.453 0.00004109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25712 21:47:13.453 0.00008731 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25713 21:47:13.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25714 21:47:13.453 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25715 21:47:13.453 0.00007625 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25716 21:47:13.453 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25717 21:47:13.453 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25718 21:47:13.453 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25719 21:47:13.453 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25720 21:47:13.453 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25721 21:47:13.453 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25722 21:47:13.453 0.02683063 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25723 21:47:13.485 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25724 21:47:13.485 0.01416573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25725 21:47:13.485 0.00001462 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25726 21:47:13.500 0.00039190 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25727 21:47:13.500 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25728 21:47:13.500 0.00034923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25729 21:47:13.500 0.00033185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25730 21:47:13.500 0.00022637 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 25731 21:47:13.500 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25732 21:47:13.500 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25733 21:47:13.500 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25734 21:47:13.500 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25735 21:47:13.500 0.00022756 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25736 21:47:13.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25737 21:47:13.500 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25738 21:47:13.500 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25739 21:47:13.500 0.00025719 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25740 21:47:13.500 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25741 21:47:13.500 0.00024573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25742 21:47:13.500 0.00015526 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25743 21:47:13.500 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25744 21:47:13.500 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25745 21:47:13.500 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25746 21:47:13.500 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25747 21:47:13.500 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25748 21:47:13.500 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25749 21:47:13.500 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25750 21:47:13.500 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25751 21:47:13.500 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25752 21:47:13.500 0.00032395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25753 21:47:13.500 0.00022637 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25754 21:47:13.500 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25755 21:47:13.500 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25756 21:47:13.500 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25757 21:47:13.500 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25758 21:47:13.500 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25759 21:47:13.500 0.00014262 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25760 21:47:13.500 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25761 21:47:13.500 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25762 21:47:13.500 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25763 21:47:13.500 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25764 21:47:13.500 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25765 21:47:13.500 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25766 21:47:13.500 0.00019121 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25767 21:47:13.500 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25768 21:47:13.500 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25769 21:47:13.500 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25770 21:47:13.500 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25771 21:47:13.500 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25772 21:47:13.500 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25773 21:47:13.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25774 21:47:13.500 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25775 21:47:13.500 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25776 21:47:13.500 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25777 21:47:13.500 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25778 21:47:13.500 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25779 21:47:13.500 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25780 21:47:13.500 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25781 21:47:13.500 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25783 21:47:13.500 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25784 21:47:13.500 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25785 21:47:13.500 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25786 21:47:13.500 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25787 21:47:13.500 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25788 21:47:13.500 0.02706925 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25789 21:47:13.532 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25790 21:47:13.532 0.01405946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25791 21:47:13.532 0.00001185 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25792 21:47:13.548 0.00033462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25793 21:47:13.548 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25794 21:47:13.548 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25795 21:47:13.548 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25796 21:47:13.548 0.00090193 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25797 21:47:13.548 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 25798 21:47:13.548 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25799 21:47:13.548 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25800 21:47:13.548 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25801 21:47:13.548 0.00020306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 25802 21:47:13.548 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25803 21:47:13.548 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 25804 21:47:13.548 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25805 21:47:13.548 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25806 21:47:13.548 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25807 21:47:13.548 0.00037491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25808 21:47:13.548 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25809 21:47:13.548 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25810 21:47:13.548 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25811 21:47:13.548 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25812 21:47:13.548 0.00018686 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25813 21:47:13.548 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25814 21:47:13.548 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25815 21:47:13.548 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25816 21:47:13.548 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25817 21:47:13.548 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25818 21:47:13.548 0.00018844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25819 21:47:13.548 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25820 21:47:13.548 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25821 21:47:13.548 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25822 21:47:13.548 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25823 21:47:13.548 0.00030775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25824 21:47:13.548 0.00023783 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25825 21:47:13.548 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25826 21:47:13.548 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25827 21:47:13.548 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25828 21:47:13.548 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25829 21:47:13.548 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25830 21:47:13.548 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25831 21:47:13.548 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25833 21:47:13.548 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25834 21:47:13.548 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25835 21:47:13.548 0.00008454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25836 21:47:13.548 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25837 21:47:13.548 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25838 21:47:13.548 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25839 21:47:13.548 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25840 21:47:13.548 0.00010390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25841 21:47:13.548 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25842 21:47:13.548 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25843 21:47:13.548 0.00012247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25844 21:47:13.548 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25845 21:47:13.548 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25846 21:47:13.548 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25847 21:47:13.548 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25848 21:47:13.548 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25849 21:47:13.548 0.00008217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25850 21:47:13.548 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25851 21:47:13.548 0.00026746 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25852 21:47:13.548 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25853 21:47:13.548 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25854 21:47:13.548 0.02598362 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25855 21:47:13.579 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25856 21:47:13.579 0.01392198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25857 21:47:13.579 0.00003358 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25858 21:47:13.594 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25859 21:47:13.594 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25860 21:47:13.594 0.00029472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25861 21:47:13.594 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25862 21:47:13.594 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25863 21:47:13.594 0.00027970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25864 21:47:13.594 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 25865 21:47:13.594 0.00019635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 25866 21:47:13.594 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25867 21:47:13.594 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25868 21:47:13.594 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25869 21:47:13.594 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25870 21:47:13.594 0.00003279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25871 21:47:13.594 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25872 21:47:13.594 0.00027180 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25873 21:47:13.594 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25874 21:47:13.594 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25875 21:47:13.594 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25876 21:47:13.594 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25877 21:47:13.594 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25878 21:47:13.594 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25879 21:47:13.594 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25880 21:47:13.594 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25881 21:47:13.594 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25882 21:47:13.594 0.00004859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25883 21:47:13.594 0.00027615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25884 21:47:13.594 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25885 21:47:13.594 0.00022479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25886 21:47:13.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25887 21:47:13.594 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25888 21:47:13.594 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25889 21:47:13.594 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25890 21:47:13.594 0.00053886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25891 21:47:13.594 0.00040770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25892 21:47:13.594 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25893 21:47:13.594 0.00034094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25894 21:47:13.594 0.00027654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25895 21:47:13.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25896 21:47:13.594 0.00024059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25898 21:47:13.594 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25899 21:47:13.594 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25900 21:47:13.594 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25901 21:47:13.594 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25902 21:47:13.594 0.00020899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25903 21:47:13.594 0.00016869 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25904 21:47:13.594 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25905 21:47:13.594 0.00025402 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25906 21:47:13.594 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25907 21:47:13.594 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25908 21:47:13.594 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25909 21:47:13.594 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25910 21:47:13.594 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25911 21:47:13.594 0.00032277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25912 21:47:13.594 0.00028286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25913 21:47:13.594 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25914 21:47:13.594 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25915 21:47:13.594 0.00026983 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25916 21:47:13.594 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25917 21:47:13.594 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25918 21:47:13.594 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25919 21:47:13.594 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25920 21:47:13.594 0.02495764 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25921 21:47:13.626 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25922 21:47:13.626 0.01428188 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25923 21:47:13.626 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25924 21:47:13.641 0.00036188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25925 21:47:13.641 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25926 21:47:13.641 0.00036069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25927 21:47:13.641 0.00029393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25928 21:47:13.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25929 21:47:13.641 0.00026825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25930 21:47:13.641 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 25931 21:47:13.641 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 25932 21:47:13.641 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25933 21:47:13.641 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25934 21:47:13.641 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 25935 21:47:13.641 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25936 21:47:13.641 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25937 21:47:13.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25938 21:47:13.641 0.00037373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25939 21:47:13.641 0.00032711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25940 21:47:13.641 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25941 21:47:13.641 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25942 21:47:13.641 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25943 21:47:13.641 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25944 21:47:13.641 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25945 21:47:13.641 0.00014933 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25946 21:47:13.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25947 21:47:13.641 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25948 21:47:13.641 0.00012919 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25949 21:47:13.641 0.00029827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25950 21:47:13.641 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25951 21:47:13.641 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25952 21:47:13.641 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25953 21:47:13.641 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25954 21:47:13.641 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25955 21:47:13.641 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25956 21:47:13.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25957 21:47:13.641 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25958 21:47:13.641 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25959 21:47:13.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25960 21:47:13.641 0.00003398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25961 21:47:13.641 0.00012168 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25962 21:47:13.641 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25963 21:47:13.641 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25964 21:47:13.641 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25965 21:47:13.641 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25966 21:47:13.641 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25967 21:47:13.641 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25968 21:47:13.641 0.00019279 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25969 21:47:13.641 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25970 21:47:13.641 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 25971 21:47:13.641 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25973 21:47:13.641 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25974 21:47:13.641 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25975 21:47:13.641 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25976 21:47:13.641 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25977 21:47:13.641 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25978 21:47:13.641 0.00008257 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25979 21:47:13.641 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25980 21:47:13.641 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25981 21:47:13.641 0.00010193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25982 21:47:13.641 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 25983 21:47:13.641 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25984 21:47:13.641 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25985 21:47:13.641 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25986 21:47:13.641 0.02693216 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25987 21:47:13.672 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25988 21:47:13.672 0.01368731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25989 21:47:13.672 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 25990 21:47:13.688 0.00027417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 25991 21:47:13.688 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 25992 21:47:13.688 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25993 21:47:13.688 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25994 21:47:13.688 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25995 21:47:13.688 0.00022202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 25996 21:47:13.688 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 25997 21:47:13.688 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 25998 21:47:13.688 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 25999 21:47:13.688 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26000 21:47:13.688 0.00018054 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26001 21:47:13.688 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26002 21:47:13.688 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26003 21:47:13.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26004 21:47:13.688 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26005 21:47:13.688 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26006 21:47:13.688 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26007 21:47:13.688 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26008 21:47:13.688 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26009 21:47:13.688 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26010 21:47:13.688 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26011 21:47:13.688 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26012 21:47:13.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26013 21:47:13.688 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26014 21:47:13.688 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26015 21:47:13.688 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26016 21:47:13.688 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26017 21:47:13.688 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26018 21:47:13.688 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26019 21:47:13.688 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26020 21:47:13.688 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26021 21:47:13.688 0.00011062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26022 21:47:13.688 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26023 21:47:13.688 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26024 21:47:13.688 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26025 21:47:13.688 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26026 21:47:13.688 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26027 21:47:13.688 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26028 21:47:13.688 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26029 21:47:13.688 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26030 21:47:13.688 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26031 21:47:13.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26032 21:47:13.688 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26033 21:47:13.688 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26034 21:47:13.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26035 21:47:13.688 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26036 21:47:13.688 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26037 21:47:13.688 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26038 21:47:13.688 0.00008059 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26039 21:47:13.688 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26040 21:47:13.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26041 21:47:13.688 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26042 21:47:13.688 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26043 21:47:13.688 0.00003556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26044 21:47:13.688 0.00005847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26045 21:47:13.688 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26046 21:47:13.688 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26047 21:47:13.688 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26048 21:47:13.688 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26049 21:47:13.688 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26050 21:47:13.688 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26051 21:47:13.688 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26052 21:47:13.688 0.02877038 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26053 21:47:13.719 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26054 21:47:13.719 0.01342381 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26055 21:47:13.719 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26056 21:47:13.735 0.00034094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26057 21:47:13.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26058 21:47:13.735 0.00034331 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26059 21:47:13.735 0.00026509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26060 21:47:13.735 0.00028761 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 26061 21:47:13.735 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26062 21:47:13.735 0.00019042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26063 21:47:13.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26064 21:47:13.735 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26065 21:47:13.735 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 26066 21:47:13.735 0.00030301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26067 21:47:13.735 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26068 21:47:13.735 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26069 21:47:13.735 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26070 21:47:13.735 0.00025363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26071 21:47:13.735 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26072 21:47:13.735 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26073 21:47:13.735 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26074 21:47:13.735 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26075 21:47:13.735 0.00019556 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26076 21:47:13.735 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26077 21:47:13.735 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26078 21:47:13.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26079 21:47:13.735 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26081 21:47:13.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26082 21:47:13.735 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26083 21:47:13.735 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26084 21:47:13.735 0.00015486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26085 21:47:13.735 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26086 21:47:13.735 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26087 21:47:13.735 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26088 21:47:13.735 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26089 21:47:13.735 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26090 21:47:13.735 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26091 21:47:13.735 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26092 21:47:13.735 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26093 21:47:13.735 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26094 21:47:13.735 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26095 21:47:13.735 0.00022835 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26096 21:47:13.735 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26097 21:47:13.735 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26098 21:47:13.735 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26099 21:47:13.735 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26100 21:47:13.735 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26101 21:47:13.735 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26102 21:47:13.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26103 21:47:13.735 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26104 21:47:13.735 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26105 21:47:13.735 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 26106 21:47:13.735 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26107 21:47:13.735 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26111 21:47:13.735 0.00443378 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26112 21:47:13.735 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26113 21:47:13.735 0.00025284 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26114 21:47:13.735 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26115 21:47:13.735 0.00024612 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26116 21:47:13.735 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26117 21:47:13.735 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26118 21:47:13.735 0.02011537 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26119 21:47:13.766 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26120 21:47:13.766 0.01439922 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26121 21:47:13.766 0.00005728 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26122 21:47:13.781 0.00044365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26123 21:47:13.781 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26124 21:47:13.781 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26125 21:47:13.781 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26126 21:47:13.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26127 21:47:13.781 0.00037570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26128 21:47:13.781 0.00028247 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 26129 21:47:13.781 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 26130 21:47:13.781 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26131 21:47:13.781 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26132 21:47:13.781 0.00027575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26133 21:47:13.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26134 21:47:13.781 0.00016632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26135 21:47:13.781 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26136 21:47:13.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26137 21:47:13.781 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26138 21:47:13.781 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26139 21:47:13.781 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26140 21:47:13.781 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26141 21:47:13.781 0.00011615 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26142 21:47:13.781 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26143 21:47:13.781 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26144 21:47:13.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26145 21:47:13.781 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26146 21:47:13.781 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26147 21:47:13.781 0.00023743 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26148 21:47:13.781 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26149 21:47:13.781 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26150 21:47:13.781 0.00024533 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26151 21:47:13.781 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26152 21:47:13.781 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26153 21:47:13.781 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26154 21:47:13.781 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26155 21:47:13.781 0.00005491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26156 21:47:13.781 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26157 21:47:13.781 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26158 21:47:13.781 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26159 21:47:13.781 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26160 21:47:13.781 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26161 21:47:13.781 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26162 21:47:13.781 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26163 21:47:13.781 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26164 21:47:13.781 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26165 21:47:13.781 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26166 21:47:13.781 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26167 21:47:13.781 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26168 21:47:13.781 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26169 21:47:13.781 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26170 21:47:13.781 0.00018765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26171 21:47:13.781 0.00018765 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26172 21:47:13.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26173 21:47:13.781 0.00014459 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26174 21:47:13.781 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 26175 21:47:13.781 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26176 21:47:13.781 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26177 21:47:13.781 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26178 21:47:13.781 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26179 21:47:13.781 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26180 21:47:13.781 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26181 21:47:13.781 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26182 21:47:13.781 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26183 21:47:13.781 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26184 21:47:13.781 0.02576554 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26185 21:47:13.813 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26186 21:47:13.813 0.01497798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26187 21:47:13.813 0.00001146 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26188 21:47:13.828 0.00040652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26189 21:47:13.828 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26190 21:47:13.828 0.00033620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26191 21:47:13.828 0.00027970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26192 21:47:13.828 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26193 21:47:13.828 0.00037057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26194 21:47:13.828 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 26195 21:47:13.828 0.00003635 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26196 21:47:13.828 0.00037373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26197 21:47:13.828 0.00032632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 26198 21:47:13.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26199 21:47:13.828 0.00039190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26200 21:47:13.828 0.00030262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26201 21:47:13.828 0.00027812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26202 21:47:13.828 0.00015684 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26203 21:47:13.828 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26204 21:47:13.828 0.00018212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26205 21:47:13.828 0.00030064 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26206 21:47:13.828 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26207 21:47:13.828 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26208 21:47:13.828 0.00024336 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26209 21:47:13.828 0.00030025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26210 21:47:13.828 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26211 21:47:13.828 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26212 21:47:13.828 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26213 21:47:13.828 0.00029037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26214 21:47:13.828 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26215 21:47:13.828 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26216 21:47:13.828 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26217 21:47:13.828 0.00003990 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26218 21:47:13.828 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26219 21:47:13.828 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26220 21:47:13.828 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26221 21:47:13.828 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26222 21:47:13.828 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26223 21:47:13.828 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26224 21:47:13.828 0.00008494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26225 21:47:13.828 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26226 21:47:13.828 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26227 21:47:13.828 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26228 21:47:13.828 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26229 21:47:13.828 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26230 21:47:13.828 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26231 21:47:13.828 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26232 21:47:13.828 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26233 21:47:13.828 0.00002568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26234 21:47:13.828 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26235 21:47:13.828 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26236 21:47:13.828 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26237 21:47:13.828 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26238 21:47:13.828 0.00026153 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26239 21:47:13.828 0.00037570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26240 21:47:13.828 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26241 21:47:13.828 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26242 21:47:13.828 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26243 21:47:13.828 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26244 21:47:13.828 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26245 21:47:13.828 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26246 21:47:13.828 0.00020978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26247 21:47:13.828 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26248 21:47:13.828 0.00013116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26249 21:47:13.828 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26250 21:47:13.828 0.02573986 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26251 21:47:13.860 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26252 21:47:13.860 0.01350203 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26253 21:47:13.860 0.00004899 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26254 21:47:13.875 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26255 21:47:13.875 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26256 21:47:13.875 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26257 21:47:13.875 0.00010627 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26258 21:47:13.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26259 21:47:13.875 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 26260 21:47:13.875 0.00012681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26261 21:47:13.875 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26262 21:47:13.875 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26263 21:47:13.875 0.00013511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 26264 21:47:13.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26265 21:47:13.875 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26266 21:47:13.875 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26267 21:47:13.875 0.00009521 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26268 21:47:13.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26269 21:47:13.875 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26270 21:47:13.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26271 21:47:13.875 0.00013156 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26272 21:47:13.875 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26273 21:47:13.875 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26274 21:47:13.875 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26275 21:47:13.875 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26276 21:47:13.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26277 21:47:13.875 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26278 21:47:13.875 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26279 21:47:13.875 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26280 21:47:13.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26281 21:47:13.875 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26282 21:47:13.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26283 21:47:13.875 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26284 21:47:13.875 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26285 21:47:13.875 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26286 21:47:13.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26287 21:47:13.875 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26288 21:47:13.875 0.00012365 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26289 21:47:13.875 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26290 21:47:13.875 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26291 21:47:13.875 0.00023388 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26292 21:47:13.875 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26293 21:47:13.875 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26294 21:47:13.875 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26297 21:47:13.875 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26298 21:47:13.875 0.00012998 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26299 21:47:13.875 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26300 21:47:13.875 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 26301 21:47:13.875 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26302 21:47:13.875 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26305 21:47:13.875 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26306 21:47:13.875 0.00009086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26307 21:47:13.875 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26308 21:47:13.875 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26309 21:47:13.875 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26310 21:47:13.875 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26311 21:47:13.875 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26312 21:47:13.875 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26313 21:47:13.875 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26314 21:47:13.875 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26315 21:47:13.875 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26316 21:47:13.875 0.02950875 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26317 21:47:13.907 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26318 21:47:13.907 0.01315003 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26319 21:47:13.907 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26320 21:47:13.922 0.00033225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26321 21:47:13.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26322 21:47:13.922 0.00031526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26323 21:47:13.922 0.00023664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26324 21:47:13.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26325 21:47:13.922 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26326 21:47:13.922 0.00024099 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 26327 21:47:13.922 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26328 21:47:13.922 0.00038242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26329 21:47:13.922 0.00041402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 26330 21:47:13.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26331 21:47:13.922 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26332 21:47:13.922 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26333 21:47:13.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26334 21:47:13.922 0.00035714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26335 21:47:13.922 0.00028010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26336 21:47:13.922 0.00034923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26337 21:47:13.922 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26338 21:47:13.922 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26339 21:47:13.922 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26340 21:47:13.922 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26341 21:47:13.922 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26342 21:47:13.922 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26343 21:47:13.922 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26344 21:47:13.922 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26345 21:47:13.922 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26346 21:47:13.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26347 21:47:13.922 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26348 21:47:13.922 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26349 21:47:13.922 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26350 21:47:13.922 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26351 21:47:13.922 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26352 21:47:13.922 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26353 21:47:13.922 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26354 21:47:13.922 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26355 21:47:13.922 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26356 21:47:13.922 0.00006874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26357 21:47:13.922 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26358 21:47:13.922 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26359 21:47:13.922 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26360 21:47:13.922 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26361 21:47:13.922 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26362 21:47:13.922 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26363 21:47:13.922 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 26364 21:47:13.922 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26365 21:47:13.922 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26369 21:47:13.922 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26370 21:47:13.922 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26371 21:47:13.922 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26372 21:47:13.922 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26373 21:47:13.922 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26374 21:47:13.922 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26375 21:47:13.922 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26376 21:47:13.922 0.00004543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26377 21:47:13.922 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26378 21:47:13.922 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26379 21:47:13.922 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26380 21:47:13.922 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26381 21:47:13.922 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26382 21:47:13.922 0.02627359 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26383 21:47:13.954 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26384 21:47:13.954 0.01379635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26385 21:47:13.954 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26386 21:47:13.969 0.00031052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26387 21:47:13.969 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26388 21:47:13.969 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26389 21:47:13.969 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26390 21:47:13.969 0.00026035 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 26391 21:47:13.969 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26392 21:47:13.969 0.00018094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26393 21:47:13.969 0.00030854 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 26394 21:47:13.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26395 21:47:13.969 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26396 21:47:13.969 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26397 21:47:13.969 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26398 21:47:13.969 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26399 21:47:13.969 0.00035319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26400 21:47:13.969 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26401 21:47:13.969 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26402 21:47:13.969 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26403 21:47:13.969 0.00036622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26404 21:47:13.969 0.00029314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26405 21:47:13.969 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26406 21:47:13.969 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26407 21:47:13.969 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26408 21:47:13.969 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26409 21:47:13.969 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26410 21:47:13.969 0.00019437 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26411 21:47:13.969 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26412 21:47:13.969 0.00004385 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26413 21:47:13.969 0.00013551 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26414 21:47:13.969 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26415 21:47:13.969 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26416 21:47:13.969 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26417 21:47:13.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26418 21:47:13.969 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26419 21:47:13.969 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26420 21:47:13.969 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26421 21:47:13.969 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26422 21:47:13.969 0.00011299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26423 21:47:13.969 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26424 21:47:13.969 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26425 21:47:13.969 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26426 21:47:13.969 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26427 21:47:13.969 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26429 21:47:13.969 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26430 21:47:13.969 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26431 21:47:13.969 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26432 21:47:13.969 0.00021570 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26433 21:47:13.969 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26434 21:47:13.969 0.00014104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26435 21:47:13.969 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26436 21:47:13.969 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26437 21:47:13.969 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26438 21:47:13.969 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26439 21:47:13.969 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26440 21:47:13.969 0.00005412 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26441 21:47:13.969 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26442 21:47:13.969 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26443 21:47:13.969 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26444 21:47:13.969 0.00012919 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26445 21:47:13.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26446 21:47:13.969 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26447 21:47:13.969 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26448 21:47:13.969 0.02696613 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26449 21:47:14.000 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26450 21:47:14.000 0.01397768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26451 21:47:14.000 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26452 21:47:14.016 0.00032948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26453 21:47:14.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26454 21:47:14.016 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26455 21:47:14.016 0.00015605 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26456 21:47:14.016 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26457 21:47:14.016 0.00027970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26458 21:47:14.016 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 26459 21:47:14.016 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26460 21:47:14.016 0.00035951 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 26461 21:47:14.016 0.00033027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26462 21:47:14.016 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26463 21:47:14.016 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26464 21:47:14.016 0.00026904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26465 21:47:14.016 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26466 21:47:14.016 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26467 21:47:14.016 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26468 21:47:14.016 0.00031486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26469 21:47:14.016 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26470 21:47:14.016 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26471 21:47:14.016 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26472 21:47:14.016 0.00032553 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26473 21:47:14.016 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26474 21:47:14.016 0.00022677 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26475 21:47:14.016 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26476 21:47:14.016 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26477 21:47:14.016 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26478 21:47:14.016 0.00006044 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26479 21:47:14.016 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26480 21:47:14.016 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26481 21:47:14.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26482 21:47:14.016 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26483 21:47:14.016 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26484 21:47:14.016 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26485 21:47:14.016 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26486 21:47:14.016 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26487 21:47:14.016 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26488 21:47:14.016 0.00010114 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26489 21:47:14.016 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26490 21:47:14.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26491 21:47:14.016 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26492 21:47:14.016 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26493 21:47:14.016 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26494 21:47:14.016 0.00008217 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26495 21:47:14.016 0.00012444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26496 21:47:14.016 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26497 21:47:14.016 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26498 21:47:14.016 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26499 21:47:14.016 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26500 21:47:14.016 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26501 21:47:14.016 0.00011852 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26502 21:47:14.016 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26503 21:47:14.016 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26504 21:47:14.016 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26505 21:47:14.016 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26506 21:47:14.016 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26507 21:47:14.016 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26508 21:47:14.016 0.00023822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26509 21:47:14.016 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26510 21:47:14.016 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26511 21:47:14.016 0.00021294 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26512 21:47:14.016 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26513 21:47:14.016 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26514 21:47:14.016 0.02697522 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26515 21:47:14.047 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26516 21:47:14.047 0.01321719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26517 21:47:14.047 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26518 21:47:14.063 0.00031328 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26519 21:47:14.063 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26520 21:47:14.063 0.00035714 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26521 21:47:14.063 0.00024889 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26522 21:47:14.063 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 26523 21:47:14.063 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26524 21:47:14.063 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26525 21:47:14.063 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 26526 21:47:14.063 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26527 21:47:14.063 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26528 21:47:14.063 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26529 21:47:14.063 0.00029077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26530 21:47:14.063 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26531 21:47:14.063 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26532 21:47:14.063 0.00043220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26533 21:47:14.063 0.00036267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26534 21:47:14.063 0.00024968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26535 21:47:14.063 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26536 21:47:14.063 0.00018291 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26537 21:47:14.063 0.00029195 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26538 21:47:14.063 0.00007664 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26539 21:47:14.063 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26540 21:47:14.063 0.00016435 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26541 21:47:14.063 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26542 21:47:14.063 0.00012444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26543 21:47:14.063 0.00020464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26544 21:47:14.063 0.00007151 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26545 21:47:14.063 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26546 21:47:14.063 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26547 21:47:14.063 0.00025205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26548 21:47:14.063 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26549 21:47:14.063 0.00036385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26550 21:47:14.063 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26551 21:47:14.063 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26552 21:47:14.063 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26553 21:47:14.063 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26554 21:47:14.063 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26555 21:47:14.063 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26556 21:47:14.063 0.00012405 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26557 21:47:14.063 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26558 21:47:14.063 0.00003081 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26559 21:47:14.063 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26560 21:47:14.063 0.00016277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26561 21:47:14.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26562 21:47:14.063 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26563 21:47:14.063 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26564 21:47:14.063 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26565 21:47:14.063 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26566 21:47:14.063 0.00005570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26567 21:47:14.063 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26568 21:47:14.063 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26569 21:47:14.063 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26570 21:47:14.063 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26571 21:47:14.063 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26572 21:47:14.063 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26573 21:47:14.063 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26574 21:47:14.063 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26575 21:47:14.063 0.00019002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26576 21:47:14.063 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26577 21:47:14.063 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26578 21:47:14.063 0.00014973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26579 21:47:14.063 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26580 21:47:14.063 0.02667023 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26581 21:47:14.094 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26582 21:47:14.094 0.02888653 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26583 21:47:14.094 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26584 21:47:14.125 0.00033027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26585 21:47:14.125 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26586 21:47:14.125 0.00039625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26587 21:47:14.125 0.00036385 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26588 21:47:14.125 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26589 21:47:14.125 0.00025640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26590 21:47:14.125 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0C 26591 21:47:14.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26592 21:47:14.125 0.00029235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26593 21:47:14.125 0.00019990 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 26594 21:47:14.125 0.00022242 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26595 21:47:14.125 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26596 21:47:14.125 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26597 21:47:14.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26598 21:47:14.125 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26599 21:47:14.125 0.00016632 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26600 21:47:14.125 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26601 21:47:14.125 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26602 21:47:14.125 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26603 21:47:14.125 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26604 21:47:14.125 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26605 21:47:14.125 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26606 21:47:14.125 0.00023901 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26607 21:47:14.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26608 21:47:14.125 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26609 21:47:14.125 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26610 21:47:14.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26611 21:47:14.125 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26612 21:47:14.125 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26613 21:47:14.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26614 21:47:14.125 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26615 21:47:14.125 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26616 21:47:14.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26617 21:47:14.125 0.00005294 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26618 21:47:14.125 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26619 21:47:14.125 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26620 21:47:14.125 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26621 21:47:14.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26622 21:47:14.125 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26623 21:47:14.125 0.00022163 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26624 21:47:14.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26625 21:47:14.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26626 21:47:14.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 26630 21:47:14.125 0.00035200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26631 21:47:14.125 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26632 21:47:14.125 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26633 21:47:14.125 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26634 21:47:14.125 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26635 21:47:14.125 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26636 21:47:14.125 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26637 21:47:14.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26638 21:47:14.125 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26639 21:47:14.125 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26640 21:47:14.125 0.00024494 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26641 21:47:14.125 0.00017857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26642 21:47:14.125 0.00017738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26643 21:47:14.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26644 21:47:14.125 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26645 21:47:14.125 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26646 21:47:14.125 0.02732129 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26647 21:47:14.156 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26648 21:47:14.156 0.01211299 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26649 21:47:14.156 0.00001580 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26650 21:47:14.172 0.00036780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 26651 21:47:14.172 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26652 21:47:14.172 0.00014854 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26653 21:47:14.172 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 26654 21:47:14.172 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1C 26655 21:47:14.172 0.00017936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26656 21:47:14.172 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26657 21:47:14.172 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 26658 21:47:14.172 0.00028800 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26659 21:47:14.172 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26660 21:47:14.172 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26661 21:47:14.172 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 26662 21:47:14.172 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26663 21:47:14.172 0.00005807 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26664 21:47:14.172 0.00029590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26665 21:47:14.172 0.00021886 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26666 21:47:14.172 0.00019832 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26667 21:47:14.172 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26668 21:47:14.172 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 26671 21:47:14.172 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26672 21:47:14.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26673 21:47:14.172 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26674 21:47:14.172 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26675 21:47:14.172 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26676 21:47:14.172 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26677 21:47:14.172 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26678 21:47:14.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26679 21:47:14.172 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26680 21:47:14.172 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26681 21:47:14.172 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26682 21:47:14.172 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26683 21:47:14.172 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26684 21:47:14.172 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26685 21:47:14.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26686 21:47:14.172 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26687 21:47:14.172 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26688 21:47:14.172 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26689 21:47:14.172 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26690 21:47:14.172 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26691 21:47:14.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26692 21:47:14.172 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26693 21:47:14.172 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26694 21:47:14.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26695 21:47:14.172 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26696 21:47:14.172 0.00020859 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26697 21:47:14.172 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26698 21:47:14.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26699 21:47:14.172 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26700 21:47:14.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26701 21:47:14.172 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26702 21:47:14.172 0.00008968 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26703 21:47:14.172 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26704 21:47:14.172 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26705 21:47:14.172 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26706 21:47:14.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26707 21:47:14.172 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26708 21:47:14.172 0.00008612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 26709 21:47:14.172 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26710 21:47:14.172 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26711 21:47:14.172 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26712 21:47:14.172 0.02711547 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26713 21:47:14.203 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26714 21:47:14.203 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 26715 21:47:14.203 0.00012484 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 26716 21:47:14.203 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: 26717 21:47:14.203 0.00027062 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_DTR COM1 SUCCESS 26718 21:47:14.203 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 26719 21:47:14.203 0.01740090 UV4BAND_E_CPS. IRP_MJ_CLOSE COM1 SUCCESS Port Closed