SUDT ACCESSPORT LOG FILE - Monitor mode Monitor: COM1 Create Time: 2016-12-01, 21:49:32 Computer Name: ÐüB£µF System version: (Build 9200) # Time Duration (s) Process Request Port Result Data ( Hex ) 1 21:48:56.219 0.14176559 UV4BAND_E_CPS. IRP_MJ_CREATE COM1 SUCCESS Port Opened 2 21:48:56.375 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 3 21:48:56.375 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_QUEUE_SIZE COM1 SUCCESS InSize: 1024, OutSize: 512 4 21:48:56.375 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 5 21:48:56.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_TIMEOUTS COM1 SUCCESS ReadIntervalTimeout: -1, ReadTotalTimeoutMultiplier: 0, ReadTotalTimeoutConstant: 0, WriteTotalTimeoutMultiplier: 0, WriteTotalTimeoutConstant: 5000 6 21:48:56.375 0.06112674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_BAUD_RATE COM1 SUCCESS Baud Rate: 9600 7 21:48:56.375 0.06116506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 8 21:48:56.438 0.00060800 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_RTS COM1 SUCCESS 9 21:48:56.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 10 21:48:56.438 0.01579694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 11 21:48:56.438 0.00040138 UV4BAND_E_CPS. IOCTL_SERIAL_SET_DTR COM1 SUCCESS 12 21:48:56.438 0.00046617 UV4BAND_E_CPS. IOCTL_SERIAL_SET_LINE_CONTROL COM1 SUCCESS StopBits: 1, Parity: No, DataBits: 8 13 21:48:56.438 0.00030973 UV4BAND_E_CPS. IOCTL_SERIAL_SET_CHARS COM1 SUCCESS EofChar: 0x1A, ErrorChar: 0x0, BreakChar: 0x0, EventChar: 0x0, XonChar: 0x11, XoffChar: 0x13 14 21:48:56.438 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_HANDFLOW COM1 SUCCESS ControlHandShake: 0x1, FlowReplace: 0x0, XonLimit: 256, XoffLimit: 256 15 21:48:56.438 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 Purge: RXABORT RXCLEAR 16 21:48:56.438 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 17 21:48:56.454 0.00023506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 55 18 21:48:56.454 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 19 21:48:56.454 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 20 21:48:56.454 0.00002133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 21 21:48:56.454 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 22 21:48:56.454 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 16 23 21:48:56.454 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 24 21:48:56.454 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 25 21:48:56.454 0.00028761 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 26 21:48:56.454 0.00025916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 27 21:48:56.454 0.00028326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 28 21:48:56.454 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 29 21:48:56.454 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 30 21:48:56.454 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 31 21:48:56.454 0.00010746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: DC 32 21:48:56.454 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 33 21:48:56.454 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 34 21:48:56.454 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 35 21:48:56.454 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 36 21:48:56.454 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 37 21:48:56.454 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 38 21:48:56.454 0.00751921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 39 21:48:56.454 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 40 21:48:56.454 0.00799645 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 41 21:48:56.469 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 42 21:48:56.469 0.00953482 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 43 21:48:56.469 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 44 21:48:56.469 0.00992593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 45 21:48:56.484 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 46 21:48:56.484 0.01044702 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 47 21:48:56.500 0.00001027 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 48 21:48:56.500 0.00915832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 49 21:48:56.500 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 50 21:48:56.500 0.00972642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 51 21:48:56.516 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 52 21:48:56.516 0.00952613 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 53 21:48:56.532 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 54 21:48:56.532 0.00991645 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 55 21:48:56.532 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 56 21:48:56.532 0.01003497 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 57 21:48:56.547 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 58 21:48:56.547 0.00966716 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 59 21:48:56.547 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 60 21:48:56.547 0.00970707 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 61 21:48:56.563 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 62 21:48:56.563 0.01027398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 63 21:48:56.578 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 65 21:48:56.578 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 66 21:48:56.578 0.01005591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 67 21:48:56.594 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 68 21:48:56.594 0.00947398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 69 21:48:56.610 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 70 21:48:56.610 0.00996386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 71 21:48:56.610 0.00010943 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 72 21:48:56.610 0.00978805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 73 21:48:56.625 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 74 21:48:56.625 0.00952455 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 75 21:48:56.641 0.00002291 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 76 21:48:56.641 0.00978173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 77 21:48:56.641 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 78 21:48:56.641 0.01010410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 79 21:48:56.657 0.00020978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 81 21:48:56.672 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 82 21:48:56.672 0.00968139 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 83 21:48:56.672 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 84 21:48:56.672 0.01036129 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 85 21:48:56.688 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 86 21:48:56.688 0.00934400 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 87 21:48:56.688 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 88 21:48:56.688 0.00970549 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 89 21:48:56.704 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 90 21:48:56.704 0.00990104 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 91 21:48:56.720 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 92 21:48:56.720 0.00965176 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 93 21:48:56.720 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 94 21:48:56.720 0.00978805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 95 21:48:56.734 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 96 21:48:56.734 0.00963595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 97 21:48:56.750 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 98 21:48:56.750 0.00991566 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 99 21:48:56.750 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 100 21:48:56.750 0.01018391 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 101 21:48:56.766 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 102 21:48:56.766 0.00944395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 103 21:48:56.781 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 104 21:48:56.781 0.00982242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 105 21:48:56.781 0.00012128 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 106 21:48:56.781 0.00978134 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 107 21:48:56.797 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 108 21:48:56.797 0.00992593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 109 21:48:56.813 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 110 21:48:56.813 0.00964386 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 111 21:48:56.813 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 112 21:48:56.813 0.00945383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 113 21:48:56.828 0.00019556 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 114 21:48:56.828 0.00967586 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 115 21:48:56.828 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 116 21:48:56.828 0.01010055 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 117 21:48:56.844 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 118 21:48:56.844 0.00950282 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 119 21:48:56.860 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 120 21:48:56.860 0.00977028 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 121 21:48:56.860 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 122 21:48:56.860 0.01041778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 123 21:48:56.875 0.00017146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 124 21:48:56.875 0.00928119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 125 21:48:56.891 0.00002173 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 126 21:48:56.891 0.00968968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 127 21:48:56.891 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 128 21:48:56.891 0.01001956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 129 21:48:56.906 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 130 21:48:56.906 0.00969837 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 131 21:48:56.922 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 132 21:48:56.922 0.00993028 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 133 21:48:56.922 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 134 21:48:56.922 0.00974065 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 135 21:48:56.938 0.00000830 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 136 21:48:56.938 0.00953442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 137 21:48:56.938 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 138 21:48:56.938 0.00178370 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 139 21:48:56.938 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 140 21:48:56.938 0.00010153 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 141 21:48:56.938 0.00000158 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 142 21:48:56.938 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 143 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 144 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07 145 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 146 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 147 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 148 21:48:56.953 0.00014459 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 149 21:48:56.953 0.00000119 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 150 21:48:56.953 0.00003990 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 151 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 152 21:48:56.953 0.00003002 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 153 21:48:56.953 0.00000751 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 154 21:48:56.953 0.00002686 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 155 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 156 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02 157 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 158 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 159 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 02 160 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 07 161 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 162 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 163 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 164 21:48:56.953 0.00003477 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 165 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 166 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 56 167 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 43 168 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32 169 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30 170 21:48:56.953 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 30 171 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 32 172 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 173 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 174 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 175 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 04 176 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 08 177 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 178 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 179 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 180 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 181 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 05 182 21:48:56.953 0.00000198 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 183 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 03 184 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 09 185 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 186 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 187 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 01 188 21:48:56.953 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 55 189 21:48:56.953 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 190 21:48:56.953 0.00030262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 191 21:48:56.953 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 192 21:48:56.953 0.00818963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 193 21:48:56.953 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 194 21:48:56.953 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 195 21:48:56.953 0.00652524 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 196 21:48:56.969 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 53 197 21:48:56.969 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 198 21:48:56.969 0.00062775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 199 21:48:56.969 0.00059299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 3D 200 21:48:56.969 0.00021965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 201 21:48:56.969 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 202 21:48:56.969 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 203 21:48:56.969 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 204 21:48:56.969 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 205 21:48:56.969 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 206 21:48:56.969 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 207 21:48:56.969 0.08901416 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 208 21:48:57.047 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 209 21:48:57.047 0.00068701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 210 21:48:57.047 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 211 21:48:57.047 0.00078222 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 212 21:48:57.047 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 213 21:48:57.047 0.00103783 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 214 21:48:57.062 0.00004346 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 215 21:48:57.062 0.00135151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 216 21:48:57.062 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 217 21:48:57.062 0.00120296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 218 21:48:57.062 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 219 21:48:57.062 0.00118479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 220 21:48:57.062 0.00014775 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 221 21:48:57.062 0.00130015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 222 21:48:57.062 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 223 21:48:57.062 0.00136849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 224 21:48:57.062 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 225 21:48:57.062 0.00122232 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 226 21:48:57.062 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 227 21:48:57.062 0.00143486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 228 21:48:57.062 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 229 21:48:57.062 0.00132267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 230 21:48:57.062 0.00003121 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 231 21:48:57.062 0.00127803 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 232 21:48:57.062 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 233 21:48:57.062 0.00128158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 234 21:48:57.062 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 235 21:48:57.062 0.00136731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 236 21:48:57.078 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 237 21:48:57.078 0.00143407 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 238 21:48:57.078 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 239 21:48:57.078 0.00099674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 240 21:48:57.078 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 241 21:48:57.078 0.00132109 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 242 21:48:57.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 243 21:48:57.078 0.00137956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 244 21:48:57.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 245 21:48:57.078 0.00086163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 246 21:48:57.078 0.00000158 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 05 247 21:48:57.078 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 58 248 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 3D 249 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: F0 250 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 10 251 21:48:57.078 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 252 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 253 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 254 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 255 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 256 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 257 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 258 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 259 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 260 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 261 21:48:57.078 0.00000040 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 262 21:48:57.078 0.00001106 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 20 263 21:48:57.078 0.00000079 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 264 21:48:57.078 0.00011062 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 265 21:48:57.078 0.00003911 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 266 21:48:57.078 0.00010509 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: RXABORT RXCLEAR 267 21:48:57.078 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 268 21:48:57.078 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 269 21:48:57.078 0.00030775 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 270 21:48:57.078 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 271 21:48:57.078 0.00163003 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 272 21:48:57.078 0.00000158 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 00 273 21:48:57.078 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 274 21:48:57.078 0.00585245 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 275 21:48:57.078 0.00006242 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 276 21:48:57.094 0.00024652 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 277 21:48:57.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 278 21:48:57.094 0.00028958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 279 21:48:57.094 0.00023348 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 280 21:48:57.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 281 21:48:57.094 0.00026509 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 282 21:48:57.094 0.00022835 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 283 21:48:57.094 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 284 21:48:57.094 0.00043615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 285 21:48:57.094 0.00036464 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 289 21:48:57.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 290 21:48:57.094 0.00031328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 291 21:48:57.094 0.00021333 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 292 21:48:57.094 0.00026232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 293 21:48:57.094 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 294 21:48:57.094 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 295 21:48:57.094 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 296 21:48:57.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 297 21:48:57.094 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 298 21:48:57.094 0.00016474 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 299 21:48:57.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 300 21:48:57.094 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 301 21:48:57.094 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 302 21:48:57.094 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 303 21:48:57.094 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 304 21:48:57.094 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 305 21:48:57.094 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 306 21:48:57.094 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 307 21:48:57.094 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 308 21:48:57.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 309 21:48:57.094 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 310 21:48:57.094 0.00008691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 311 21:48:57.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 312 21:48:57.094 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 313 21:48:57.094 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 314 21:48:57.094 0.00004662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 315 21:48:57.094 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 316 21:48:57.094 0.00010983 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 317 21:48:57.094 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 318 21:48:57.094 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 319 21:48:57.094 0.00008415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 320 21:48:57.094 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 321 21:48:57.094 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 322 21:48:57.094 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 323 21:48:57.094 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 324 21:48:57.094 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 325 21:48:57.094 0.00031447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 326 21:48:57.094 0.00022953 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 327 21:48:57.094 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 328 21:48:57.094 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 329 21:48:57.094 0.00018686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 331 21:48:57.094 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 332 21:48:57.094 0.00010943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 333 21:48:57.094 0.00013590 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 334 21:48:57.094 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 335 21:48:57.094 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 336 21:48:57.094 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 337 21:48:57.094 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 338 21:48:57.094 0.07290116 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 339 21:48:57.172 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 340 21:48:57.172 0.01555872 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 341 21:48:57.172 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 342 21:48:57.188 0.00034331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 343 21:48:57.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 344 21:48:57.188 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 345 21:48:57.188 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 346 21:48:57.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 347 21:48:57.188 0.00024415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 348 21:48:57.188 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 349 21:48:57.188 0.00029393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 350 21:48:57.188 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 351 21:48:57.188 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 352 21:48:57.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 353 21:48:57.188 0.00025442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 354 21:48:57.188 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 355 21:48:57.188 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 356 21:48:57.188 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 357 21:48:57.188 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 358 21:48:57.188 0.00012760 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 359 21:48:57.188 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 360 21:48:57.188 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 361 21:48:57.188 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 362 21:48:57.188 0.00000988 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 363 21:48:57.188 0.00021807 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 364 21:48:57.188 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 365 21:48:57.188 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 366 21:48:57.188 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 367 21:48:57.188 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 368 21:48:57.188 0.00021689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 370 21:48:57.188 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 371 21:48:57.188 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 372 21:48:57.188 0.00018963 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 373 21:48:57.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 374 21:48:57.188 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 375 21:48:57.188 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 376 21:48:57.188 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 377 21:48:57.188 0.00043259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 378 21:48:57.188 0.00029077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 379 21:48:57.188 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 380 21:48:57.188 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 381 21:48:57.188 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 382 21:48:57.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 383 21:48:57.188 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 384 21:48:57.188 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 385 21:48:57.188 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 386 21:48:57.188 0.00021847 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 387 21:48:57.188 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 388 21:48:57.188 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 389 21:48:57.188 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 390 21:48:57.188 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 391 21:48:57.188 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 392 21:48:57.188 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 393 21:48:57.188 0.00004622 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 394 21:48:57.188 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 395 21:48:57.188 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 396 21:48:57.188 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 397 21:48:57.188 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 398 21:48:57.188 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 399 21:48:57.188 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 400 21:48:57.188 0.00009560 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 401 21:48:57.188 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 402 21:48:57.188 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 403 21:48:57.188 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 404 21:48:57.188 0.02619063 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 405 21:48:57.219 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 406 21:48:57.219 0.01458450 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 407 21:48:57.219 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 408 21:48:57.235 0.00024810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 409 21:48:57.235 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 410 21:48:57.235 0.00029353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 411 21:48:57.235 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 412 21:48:57.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 413 21:48:57.235 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 414 21:48:57.235 0.00024612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 415 21:48:57.235 0.00034173 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 416 21:48:57.235 0.00023072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 417 21:48:57.235 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 418 21:48:57.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 419 21:48:57.235 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 420 21:48:57.235 0.00025126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 421 21:48:57.235 0.00016198 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 422 21:48:57.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 423 21:48:57.235 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 424 21:48:57.235 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 425 21:48:57.235 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 426 21:48:57.235 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 427 21:48:57.235 0.00014815 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 428 21:48:57.235 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 429 21:48:57.235 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 430 21:48:57.235 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 431 21:48:57.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 432 21:48:57.235 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 433 21:48:57.235 0.00027536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 434 21:48:57.235 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 435 21:48:57.235 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 436 21:48:57.235 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 437 21:48:57.235 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 438 21:48:57.235 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 439 21:48:57.235 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 440 21:48:57.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 441 21:48:57.235 0.00008889 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 442 21:48:57.235 0.00017896 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 443 21:48:57.235 0.00008810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 444 21:48:57.235 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 445 21:48:57.235 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 446 21:48:57.235 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 447 21:48:57.235 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 448 21:48:57.235 0.00008217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 449 21:48:57.235 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 450 21:48:57.235 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 451 21:48:57.235 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 452 21:48:57.235 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 453 21:48:57.235 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 454 21:48:57.235 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 455 21:48:57.235 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 456 21:48:57.235 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 457 21:48:57.235 0.00007348 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 458 21:48:57.235 0.00025047 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 459 21:48:57.235 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 460 21:48:57.235 0.00028049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 461 21:48:57.235 0.00029946 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 462 21:48:57.235 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 463 21:48:57.235 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 464 21:48:57.235 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 465 21:48:57.235 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 466 21:48:57.235 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 467 21:48:57.235 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 468 21:48:57.235 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 469 21:48:57.235 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 470 21:48:57.235 0.02712692 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 471 21:48:57.266 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 472 21:48:57.266 0.01437354 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 473 21:48:57.266 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 474 21:48:57.282 0.00052622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 475 21:48:57.282 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 476 21:48:57.282 0.00034133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 477 21:48:57.282 0.00017659 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 478 21:48:57.282 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 479 21:48:57.282 0.00026272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 480 21:48:57.282 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 481 21:48:57.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 482 21:48:57.282 0.00013748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 483 21:48:57.282 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 484 21:48:57.282 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 485 21:48:57.282 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 486 21:48:57.282 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 487 21:48:57.282 0.00020069 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 488 21:48:57.282 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 489 21:48:57.282 0.00013867 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 490 21:48:57.282 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 491 21:48:57.282 0.00000909 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 492 21:48:57.282 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 493 21:48:57.282 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 494 21:48:57.282 0.00019240 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 495 21:48:57.282 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 496 21:48:57.282 0.00012484 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 497 21:48:57.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 498 21:48:57.282 0.00008968 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 499 21:48:57.282 0.00012286 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 500 21:48:57.282 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 501 21:48:57.282 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 502 21:48:57.282 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 503 21:48:57.282 0.00011654 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 504 21:48:57.282 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 505 21:48:57.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 506 21:48:57.282 0.00018252 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 507 21:48:57.282 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 508 21:48:57.282 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 509 21:48:57.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 510 21:48:57.282 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 511 21:48:57.282 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 14 512 21:48:57.282 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 513 21:48:57.282 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 514 21:48:57.282 0.00008691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 515 21:48:57.282 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 516 21:48:57.282 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 517 21:48:57.282 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 518 21:48:57.282 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 519 21:48:57.282 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 520 21:48:57.282 0.00009442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 521 21:48:57.282 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 522 21:48:57.282 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 523 21:48:57.282 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 524 21:48:57.282 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 525 21:48:57.282 0.00021294 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 526 21:48:57.282 0.00012800 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 527 21:48:57.282 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 528 21:48:57.282 0.00012207 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 529 21:48:57.282 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 530 21:48:57.282 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 531 21:48:57.282 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 532 21:48:57.282 0.00010509 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 533 21:48:57.282 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 534 21:48:57.282 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 535 21:48:57.282 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 536 21:48:57.282 0.02834134 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 537 21:48:57.313 0.00003240 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 538 21:48:57.313 0.01279921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 539 21:48:57.313 0.00004385 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 540 21:48:57.328 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 541 21:48:57.328 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 542 21:48:57.328 0.00071822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 543 21:48:57.328 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 544 21:48:57.328 0.00023783 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 545 21:48:57.328 0.00013314 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 546 21:48:57.328 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 547 21:48:57.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 548 21:48:57.328 0.00034291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 549 21:48:57.328 0.00022242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 550 21:48:57.328 0.00016711 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 551 21:48:57.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 552 21:48:57.328 0.00012800 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 553 21:48:57.328 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 554 21:48:57.328 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 555 21:48:57.328 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 556 21:48:57.328 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 557 21:48:57.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 558 21:48:57.328 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 559 21:48:57.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 560 21:48:57.328 0.00026588 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 561 21:48:57.328 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 562 21:48:57.328 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 563 21:48:57.328 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 564 21:48:57.328 0.00003911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 565 21:48:57.328 0.00010864 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 566 21:48:57.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 567 21:48:57.328 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 568 21:48:57.328 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 569 21:48:57.328 0.00012840 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 570 21:48:57.328 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 571 21:48:57.328 0.00026272 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 572 21:48:57.328 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 573 21:48:57.328 0.00014499 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 574 21:48:57.328 0.00008810 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 575 21:48:57.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 576 21:48:57.328 0.00005057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 577 21:48:57.328 0.00015289 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 578 21:48:57.328 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 579 21:48:57.328 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 580 21:48:57.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 581 21:48:57.328 0.00013827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 582 21:48:57.328 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 583 21:48:57.328 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 584 21:48:57.328 0.00028681 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 585 21:48:57.328 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 586 21:48:57.328 0.00010390 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 587 21:48:57.328 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 588 21:48:57.328 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 589 21:48:57.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 590 21:48:57.328 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 591 21:48:57.328 0.00009600 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 592 21:48:57.328 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 593 21:48:57.328 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 594 21:48:57.328 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 595 21:48:57.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 596 21:48:57.328 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 597 21:48:57.328 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 598 21:48:57.328 0.00024178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 599 21:48:57.328 0.00007269 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 600 21:48:57.328 0.00013748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 601 21:48:57.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 602 21:48:57.328 0.02590737 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 603 21:48:57.359 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 604 21:48:57.359 0.01455210 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 605 21:48:57.359 0.00001225 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 606 21:48:57.375 0.00018410 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 607 21:48:57.375 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 608 21:48:57.375 0.00018489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 609 21:48:57.375 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 610 21:48:57.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 611 21:48:57.375 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 612 21:48:57.375 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 613 21:48:57.375 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 614 21:48:57.375 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 615 21:48:57.375 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 616 21:48:57.375 0.00000869 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 617 21:48:57.375 0.00021491 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 618 21:48:57.375 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 619 21:48:57.375 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 620 21:48:57.375 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 621 21:48:57.375 0.00013235 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 622 21:48:57.375 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 623 21:48:57.375 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 624 21:48:57.375 0.00009205 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 625 21:48:57.375 0.00014341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 626 21:48:57.375 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 627 21:48:57.375 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 628 21:48:57.375 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 629 21:48:57.375 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 630 21:48:57.375 0.00002686 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 631 21:48:57.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 632 21:48:57.375 0.00016079 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 633 21:48:57.375 0.00012879 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 634 21:48:57.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 635 21:48:57.375 0.00016672 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 636 21:48:57.375 0.00010904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 637 21:48:57.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 638 21:48:57.375 0.00022519 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 639 21:48:57.375 0.00013630 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 640 21:48:57.375 0.00007743 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 641 21:48:57.375 0.00029906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 642 21:48:57.375 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 643 21:48:57.375 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 644 21:48:57.375 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 645 21:48:57.375 0.00038005 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 646 21:48:57.375 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 647 21:48:57.375 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 648 21:48:57.375 0.00019358 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 649 21:48:57.375 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 650 21:48:57.375 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 651 21:48:57.375 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 652 21:48:57.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 653 21:48:57.375 0.00023704 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 654 21:48:57.375 0.00027220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 655 21:48:57.375 0.00018844 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 656 21:48:57.375 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 657 21:48:57.375 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 658 21:48:57.375 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 659 21:48:57.375 0.00020069 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 660 21:48:57.375 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 661 21:48:57.375 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 662 21:48:57.375 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 663 21:48:57.375 0.00015802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 664 21:48:57.375 0.00026114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 665 21:48:57.375 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 666 21:48:57.375 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 667 21:48:57.375 0.00003319 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 668 21:48:57.375 0.02700446 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 669 21:48:57.406 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 670 21:48:57.406 0.01344593 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 671 21:48:57.406 0.00001264 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 672 21:48:57.422 0.00029511 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 673 21:48:57.422 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 674 21:48:57.422 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 675 21:48:57.422 0.00019121 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 676 21:48:57.422 0.00017580 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 677 21:48:57.422 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 678 21:48:57.422 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 679 21:48:57.422 0.00028405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 680 21:48:57.422 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 681 21:48:57.422 0.00025561 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 682 21:48:57.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 683 21:48:57.422 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 684 21:48:57.422 0.00022914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 685 21:48:57.422 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 686 21:48:57.422 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 687 21:48:57.422 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 688 21:48:57.422 0.00015802 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 689 21:48:57.422 0.00004741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 690 21:48:57.422 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 691 21:48:57.422 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 692 21:48:57.422 0.00028010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 693 21:48:57.422 0.00018726 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 694 21:48:57.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 695 21:48:57.422 0.00016751 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 696 21:48:57.422 0.00021017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 697 21:48:57.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 698 21:48:57.422 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 699 21:48:57.422 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 700 21:48:57.422 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 701 21:48:57.422 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 702 21:48:57.422 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 703 21:48:57.422 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 704 21:48:57.422 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 705 21:48:57.422 0.00016435 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 706 21:48:57.422 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 707 21:48:57.422 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 708 21:48:57.422 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 712 21:48:57.422 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 713 21:48:57.422 0.00009798 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 714 21:48:57.422 0.00002607 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 715 21:48:57.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 716 21:48:57.422 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 717 21:48:57.422 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 718 21:48:57.422 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 719 21:48:57.422 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 720 21:48:57.422 0.00016198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 721 21:48:57.422 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 722 21:48:57.422 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 723 21:48:57.422 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 724 21:48:57.422 0.00023941 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 725 21:48:57.422 0.00011852 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 726 21:48:57.422 0.00007388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 727 21:48:57.422 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 728 21:48:57.422 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 729 21:48:57.422 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 730 21:48:57.422 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 731 21:48:57.422 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 732 21:48:57.422 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 733 21:48:57.422 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 734 21:48:57.422 0.02683300 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 735 21:48:57.453 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 736 21:48:57.453 0.01351388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 737 21:48:57.453 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 738 21:48:57.469 0.00026785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 739 21:48:57.469 0.00011022 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 740 21:48:57.469 0.00021175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 741 21:48:57.469 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 742 21:48:57.469 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 743 21:48:57.469 0.00011694 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 744 21:48:57.469 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 745 21:48:57.469 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 746 21:48:57.469 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 747 21:48:57.469 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 748 21:48:57.469 0.00020188 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 749 21:48:57.469 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 750 21:48:57.469 0.00013946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 751 21:48:57.469 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 752 21:48:57.469 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 753 21:48:57.469 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 754 21:48:57.469 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 755 21:48:57.469 0.00015052 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 756 21:48:57.469 0.00010430 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 757 21:48:57.469 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 758 21:48:57.469 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 759 21:48:57.469 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 760 21:48:57.469 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 761 21:48:57.469 0.00005610 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 762 21:48:57.469 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 763 21:48:57.469 0.00011496 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 764 21:48:57.469 0.00013511 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 765 21:48:57.469 0.00005254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 766 21:48:57.469 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 767 21:48:57.469 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 768 21:48:57.469 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 769 21:48:57.469 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 770 21:48:57.469 0.00006281 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 771 21:48:57.469 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 773 21:48:57.469 0.00018015 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 774 21:48:57.469 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 775 21:48:57.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 776 21:48:57.469 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 777 21:48:57.469 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 778 21:48:57.469 0.00009323 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 779 21:48:57.469 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 780 21:48:57.469 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 781 21:48:57.469 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 782 21:48:57.469 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 783 21:48:57.469 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 784 21:48:57.469 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 785 21:48:57.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 786 21:48:57.469 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 787 21:48:57.469 0.00008612 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 788 21:48:57.469 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 789 21:48:57.469 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 790 21:48:57.469 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 791 21:48:57.469 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 792 21:48:57.469 0.00009442 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 793 21:48:57.469 0.00009007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 794 21:48:57.469 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 795 21:48:57.469 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 796 21:48:57.469 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 797 21:48:57.469 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 798 21:48:57.469 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 799 21:48:57.469 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 800 21:48:57.469 0.02717670 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 801 21:48:57.500 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 802 21:48:57.500 0.01474924 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 803 21:48:57.500 0.00001422 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 804 21:48:57.516 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 805 21:48:57.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 806 21:48:57.516 0.00026390 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 807 21:48:57.516 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 808 21:48:57.516 0.00023111 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 809 21:48:57.516 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 810 21:48:57.516 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 811 21:48:57.516 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 812 21:48:57.516 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 813 21:48:57.516 0.00021333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 814 21:48:57.516 0.00002370 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 815 21:48:57.516 0.00025758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 816 21:48:57.516 0.00020227 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 817 21:48:57.516 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 818 21:48:57.516 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 819 21:48:57.516 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 820 21:48:57.516 0.00016000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 821 21:48:57.516 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 822 21:48:57.516 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 823 21:48:57.516 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 824 21:48:57.516 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 825 21:48:57.516 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 826 21:48:57.516 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C8 827 21:48:57.516 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 828 21:48:57.516 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 829 21:48:57.516 0.00025561 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 1F 830 21:48:57.516 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 831 21:48:57.516 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 832 21:48:57.516 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 833 21:48:57.516 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 834 21:48:57.516 0.00015565 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 835 21:48:57.516 0.00013590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 836 21:48:57.516 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 837 21:48:57.516 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 838 21:48:57.516 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 839 21:48:57.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 840 21:48:57.516 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 841 21:48:57.516 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 842 21:48:57.516 0.00015605 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 843 21:48:57.516 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 844 21:48:57.516 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 845 21:48:57.516 0.00027852 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 846 21:48:57.516 0.00028602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 847 21:48:57.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 848 21:48:57.516 0.00029077 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 849 21:48:57.516 0.00022914 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 850 21:48:57.516 0.00024296 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 851 21:48:57.516 0.00005531 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 852 21:48:57.516 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 853 21:48:57.516 0.00022479 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 854 21:48:57.516 0.00007941 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 855 21:48:57.516 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 856 21:48:57.516 0.00022874 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 857 21:48:57.516 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 858 21:48:57.516 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 859 21:48:57.516 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 860 21:48:57.516 0.00010351 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 861 21:48:57.516 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 862 21:48:57.516 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 863 21:48:57.516 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 864 21:48:57.516 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 865 21:48:57.516 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 866 21:48:57.516 0.02683063 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 867 21:48:57.547 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 868 21:48:57.547 0.01406381 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 869 21:48:57.547 0.00001541 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 870 21:48:57.563 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 871 21:48:57.563 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 872 21:48:57.563 0.00022005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 873 21:48:57.563 0.00018094 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 874 21:48:57.563 0.00027891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 875 21:48:57.563 0.00005096 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 876 21:48:57.563 0.00024849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 877 21:48:57.563 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 878 21:48:57.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 879 21:48:57.563 0.00015842 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 880 21:48:57.563 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 881 21:48:57.563 0.00033580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 882 21:48:57.563 0.00024770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 883 21:48:57.563 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 884 21:48:57.563 0.00024415 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 885 21:48:57.563 0.00009402 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 886 21:48:57.563 0.00006084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 887 21:48:57.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 888 21:48:57.563 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 889 21:48:57.563 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 890 21:48:57.563 0.00023388 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 891 21:48:57.563 0.00015012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 892 21:48:57.563 0.00017106 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 893 21:48:57.563 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 894 21:48:57.563 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 895 21:48:57.563 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 896 21:48:57.563 0.00014578 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 897 21:48:57.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 898 21:48:57.563 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 899 21:48:57.563 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 900 21:48:57.563 0.00004030 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 901 21:48:57.563 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 902 21:48:57.563 0.00022993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 903 21:48:57.563 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 904 21:48:57.563 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 905 21:48:57.563 0.00033541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 906 21:48:57.563 0.00013472 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 907 21:48:57.563 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 908 21:48:57.563 0.00020543 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 909 21:48:57.563 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 910 21:48:57.563 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 911 21:48:57.563 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 912 21:48:57.563 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 913 21:48:57.563 0.00013116 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 914 21:48:57.563 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 915 21:48:57.563 0.00009047 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 916 21:48:57.563 0.00001225 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 917 21:48:57.563 0.00016474 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 918 21:48:57.563 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 919 21:48:57.563 0.00019595 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 920 21:48:57.563 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 921 21:48:57.563 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 922 21:48:57.563 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 923 21:48:57.563 0.00020227 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 924 21:48:57.563 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 925 21:48:57.563 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 926 21:48:57.563 0.00002805 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 927 21:48:57.563 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 928 21:48:57.563 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 929 21:48:57.563 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 930 21:48:57.563 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 931 21:48:57.563 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 932 21:48:57.563 0.02692268 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 933 21:48:57.594 0.00000790 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 934 21:48:57.594 0.01334993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 935 21:48:57.594 0.00001343 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 936 21:48:57.610 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 937 21:48:57.610 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 938 21:48:57.610 0.00021215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 939 21:48:57.610 0.00019081 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 940 21:48:57.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 941 21:48:57.610 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 942 21:48:57.610 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 943 21:48:57.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 944 21:48:57.610 0.00036425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 945 21:48:57.610 0.00024533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 946 21:48:57.610 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 947 21:48:57.610 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 948 21:48:57.610 0.00016909 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 949 21:48:57.610 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 950 21:48:57.610 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 951 21:48:57.610 0.00002410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 952 21:48:57.610 0.00004780 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 953 21:48:57.610 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 954 21:48:57.610 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 955 21:48:57.610 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 956 21:48:57.610 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C7 957 21:48:57.610 0.00013985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 958 21:48:57.610 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 959 21:48:57.610 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 960 21:48:57.610 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 961 21:48:57.610 0.00011536 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 962 21:48:57.610 0.00010232 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 963 21:48:57.610 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 964 21:48:57.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 965 21:48:57.610 0.00013709 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 966 21:48:57.610 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 967 21:48:57.610 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 968 21:48:57.610 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 969 21:48:57.610 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 970 21:48:57.610 0.00011970 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 971 21:48:57.610 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 972 21:48:57.610 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 973 21:48:57.610 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 974 21:48:57.610 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 976 21:48:57.610 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 977 21:48:57.610 0.00021254 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 978 21:48:57.610 0.00028484 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 979 21:48:57.610 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 980 21:48:57.610 0.00026904 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 981 21:48:57.610 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 982 21:48:57.610 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 983 21:48:57.610 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 984 21:48:57.610 0.00019635 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 985 21:48:57.610 0.00010311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 986 21:48:57.610 0.00011299 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 987 21:48:57.610 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 988 21:48:57.610 0.00002844 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 989 21:48:57.610 0.00011378 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 990 21:48:57.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 991 21:48:57.610 0.00008691 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 992 21:48:57.610 0.00010114 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 993 21:48:57.610 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 994 21:48:57.610 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 995 21:48:57.610 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 996 21:48:57.610 0.02933967 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 997 21:48:57.641 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 998 21:48:57.641 0.00004938 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 999 21:48:57.641 0.01191270 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1000 21:48:57.657 0.00030617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1001 21:48:57.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1002 21:48:57.657 0.00020701 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1003 21:48:57.657 0.00015921 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1004 21:48:57.657 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1005 21:48:57.657 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1006 21:48:57.657 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 0E 1009 21:48:57.657 0.00027733 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1010 21:48:57.657 0.00019319 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1011 21:48:57.657 0.00020662 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1012 21:48:57.657 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1013 21:48:57.657 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1014 21:48:57.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1015 21:48:57.657 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1016 21:48:57.657 0.00015961 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1017 21:48:57.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1018 21:48:57.657 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1019 21:48:57.657 0.00019911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1020 21:48:57.657 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1021 21:48:57.657 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1022 21:48:57.657 0.00018805 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1023 21:48:57.657 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1024 21:48:57.657 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1025 21:48:57.657 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1026 21:48:57.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1027 21:48:57.657 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1028 21:48:57.657 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1029 21:48:57.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1030 21:48:57.657 0.00022716 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1031 21:48:57.657 0.00002094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1032 21:48:57.657 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1033 21:48:57.657 0.00014143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1034 21:48:57.657 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1035 21:48:57.657 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1036 21:48:57.657 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1037 21:48:57.657 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1038 21:48:57.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1039 21:48:57.657 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1040 21:48:57.657 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1041 21:48:57.657 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1042 21:48:57.657 0.00015249 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1043 21:48:57.657 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1044 21:48:57.657 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1045 21:48:57.657 0.00001422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1046 21:48:57.657 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1047 21:48:57.657 0.00015763 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1048 21:48:57.657 0.00011931 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1049 21:48:57.657 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1050 21:48:57.657 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1051 21:48:57.657 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1052 21:48:57.657 0.00001185 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1053 21:48:57.657 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1054 21:48:57.657 0.00011654 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1055 21:48:57.657 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1056 21:48:57.657 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1057 21:48:57.657 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1058 21:48:57.657 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1059 21:48:57.657 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1060 21:48:57.657 0.00010667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1061 21:48:57.657 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1062 21:48:57.657 0.02651418 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1063 21:48:57.688 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1064 21:48:57.688 0.01367151 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1065 21:48:57.688 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1066 21:48:57.703 0.00030380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1067 21:48:57.703 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1068 21:48:57.703 0.00033422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1069 21:48:57.703 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1070 21:48:57.703 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1071 21:48:57.703 0.00042667 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1072 21:48:57.703 0.00033778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 1073 21:48:57.703 0.00017383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 1074 21:48:57.703 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1075 21:48:57.703 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1076 21:48:57.703 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1077 21:48:57.703 0.00031131 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1078 21:48:57.703 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1079 21:48:57.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1080 21:48:57.703 0.00046025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1081 21:48:57.703 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1082 21:48:57.703 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1083 21:48:57.703 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1084 21:48:57.703 0.00025481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1085 21:48:57.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1086 21:48:57.703 0.00017501 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1087 21:48:57.703 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1088 21:48:57.703 0.00022440 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1089 21:48:57.703 0.00015526 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1090 21:48:57.703 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1091 21:48:57.703 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1092 21:48:57.703 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1093 21:48:57.703 0.00011496 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1094 21:48:57.703 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1095 21:48:57.703 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1096 21:48:57.703 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1097 21:48:57.703 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1098 21:48:57.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1099 21:48:57.703 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1100 21:48:57.703 0.00018015 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1101 21:48:57.703 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1102 21:48:57.703 0.00017778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1103 21:48:57.703 0.00022598 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1104 21:48:57.703 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1105 21:48:57.703 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1106 21:48:57.703 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1107 21:48:57.703 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1108 21:48:57.703 0.00004227 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1109 21:48:57.703 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1110 21:48:57.703 0.00008375 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1111 21:48:57.703 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1112 21:48:57.703 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1113 21:48:57.703 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1114 21:48:57.703 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1115 21:48:57.703 0.00031249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1116 21:48:57.703 0.00015131 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1117 21:48:57.703 0.00020938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1118 21:48:57.703 0.00016119 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1119 21:48:57.703 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1120 21:48:57.703 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1121 21:48:57.703 0.00022202 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1122 21:48:57.703 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1123 21:48:57.703 0.00007467 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1124 21:48:57.703 0.00016040 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1125 21:48:57.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1126 21:48:57.703 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1127 21:48:57.703 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1128 21:48:57.703 0.02652525 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1129 21:48:57.734 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1130 21:48:57.734 0.01337640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1131 21:48:57.734 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1132 21:48:57.750 0.00035002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1133 21:48:57.750 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1134 21:48:57.750 0.00032237 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1135 21:48:57.750 0.00025165 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1136 21:48:57.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1137 21:48:57.750 0.00026864 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1138 21:48:57.750 0.00021017 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 1139 21:48:57.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1140 21:48:57.750 0.00029630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 1141 21:48:57.750 0.00032632 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1142 21:48:57.750 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1143 21:48:57.750 0.00030143 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1144 21:48:57.750 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1145 21:48:57.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1146 21:48:57.750 0.00032277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1147 21:48:57.750 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 1148 21:48:57.750 0.00024375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 1149 21:48:57.750 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1150 21:48:57.750 0.00020780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1151 21:48:57.750 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 1152 21:48:57.750 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1153 21:48:57.750 0.00014815 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1154 21:48:57.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1155 21:48:57.750 0.00019753 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1156 21:48:57.750 0.00013156 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0A 1157 21:48:57.750 0.00018568 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 1158 21:48:57.750 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1159 21:48:57.750 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1160 21:48:57.750 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1161 21:48:57.750 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1162 21:48:57.750 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1169 21:48:57.750 0.00005452 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1170 21:48:57.750 0.00023190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1171 21:48:57.750 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1172 21:48:57.750 0.00022795 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1173 21:48:57.750 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1174 21:48:57.750 0.00017699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1175 21:48:57.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1176 21:48:57.750 0.00017304 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1177 21:48:57.750 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1178 21:48:57.750 0.00013551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1179 21:48:57.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1180 21:48:57.750 0.00008454 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1181 21:48:57.750 0.00016277 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1182 21:48:57.750 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1183 21:48:57.750 0.00017580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1184 21:48:57.750 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1185 21:48:57.750 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1186 21:48:57.750 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1187 21:48:57.750 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1188 21:48:57.750 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1189 21:48:57.750 0.00011338 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1190 21:48:57.750 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1191 21:48:57.750 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1192 21:48:57.750 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1195 21:48:57.782 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1196 21:48:57.782 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1197 21:48:57.782 0.01202094 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1198 21:48:57.797 0.00028761 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1199 21:48:57.797 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1200 21:48:57.797 0.00028721 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1201 21:48:57.797 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1202 21:48:57.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1203 21:48:57.797 0.00018291 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 1204 21:48:57.797 0.00049146 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1205 21:48:57.797 0.00024059 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 1206 21:48:57.797 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1207 21:48:57.797 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1208 21:48:57.797 0.00020148 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1209 21:48:57.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1210 21:48:57.797 0.00001896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1211 21:48:57.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1212 21:48:57.797 0.00027931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1213 21:48:57.797 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1214 21:48:57.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1215 21:48:57.797 0.00029827 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1216 21:48:57.797 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 1217 21:48:57.797 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 1218 21:48:57.797 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1219 21:48:57.797 0.00010548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1220 21:48:57.797 0.00013472 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 1221 21:48:57.797 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1222 21:48:57.797 0.00008849 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1223 21:48:57.797 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1224 21:48:57.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1225 21:48:57.797 0.00001304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1226 21:48:57.797 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1227 21:48:57.797 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1228 21:48:57.797 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1229 21:48:57.797 0.00019398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1230 21:48:57.797 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1231 21:48:57.797 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1232 21:48:57.797 0.00009758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1233 21:48:57.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1234 21:48:57.797 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1235 21:48:57.797 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1236 21:48:57.797 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1237 21:48:57.797 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1238 21:48:57.797 0.00008691 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1239 21:48:57.797 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1240 21:48:57.797 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1241 21:48:57.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1242 21:48:57.797 0.00016593 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1243 21:48:57.797 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1244 21:48:57.797 0.00010825 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1245 21:48:57.797 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1246 21:48:57.797 0.00011970 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1247 21:48:57.797 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1248 21:48:57.797 0.00016316 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1250 21:48:57.797 0.00009679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1251 21:48:57.797 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1252 21:48:57.797 0.00005333 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1253 21:48:57.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1254 21:48:57.797 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1255 21:48:57.797 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1256 21:48:57.797 0.00012207 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1257 21:48:57.797 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1258 21:48:57.797 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1259 21:48:57.797 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1260 21:48:57.797 0.02659952 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1261 21:48:57.829 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1262 21:48:57.829 0.01448218 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1263 21:48:57.829 0.00001304 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1264 21:48:57.844 0.00030222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1265 21:48:57.844 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1266 21:48:57.844 0.00032158 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1267 21:48:57.844 0.00026667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1268 21:48:57.844 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1269 21:48:57.844 0.00043931 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1270 21:48:57.844 0.00035516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 1271 21:48:57.844 0.00028089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 1272 21:48:57.844 0.00020504 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1273 21:48:57.844 0.00001620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1274 21:48:57.844 0.00002528 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1275 21:48:57.844 0.00033383 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1276 21:48:57.844 0.00033936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1277 21:48:57.844 0.00033067 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 09 1278 21:48:57.844 0.00014657 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1279 21:48:57.844 0.00017896 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1280 21:48:57.844 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 08 1281 21:48:57.844 0.00009916 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1282 21:48:57.844 0.00017620 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1283 21:48:57.844 0.00011338 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 07 1284 21:48:57.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1285 21:48:57.844 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1286 21:48:57.844 0.00020583 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1287 21:48:57.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1288 21:48:57.844 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1289 21:48:57.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1290 21:48:57.844 0.00014025 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1291 21:48:57.844 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1292 21:48:57.844 0.00033857 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1293 21:48:57.844 0.00019358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1294 21:48:57.844 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1295 21:48:57.844 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1296 21:48:57.844 0.00030657 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1297 21:48:57.844 0.00033146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1298 21:48:57.844 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1299 21:48:57.844 0.00020622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1300 21:48:57.844 0.00021057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1301 21:48:57.844 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1302 21:48:57.844 0.00028681 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1303 21:48:57.844 0.00030617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1304 21:48:57.844 0.00023032 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1305 21:48:57.844 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1306 21:48:57.844 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1307 21:48:57.844 0.00030301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1308 21:48:57.844 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1309 21:48:57.844 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1310 21:48:57.844 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1311 21:48:57.844 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1312 21:48:57.844 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1316 21:48:57.844 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1317 21:48:57.844 0.00027062 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1318 21:48:57.844 0.00027259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1319 21:48:57.844 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1320 21:48:57.844 0.00019002 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1321 21:48:57.844 0.00017185 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1322 21:48:57.844 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1323 21:48:57.844 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1324 21:48:57.844 0.00020504 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1325 21:48:57.844 0.00002054 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1326 21:48:57.844 0.02617127 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1327 21:48:57.875 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1328 21:48:57.875 0.01303981 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1329 21:48:57.875 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1330 21:48:57.891 0.00030736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1331 21:48:57.891 0.00000514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1332 21:48:57.891 0.00028444 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1333 21:48:57.891 0.00019161 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1334 21:48:57.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1335 21:48:57.891 0.00034923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1336 21:48:57.891 0.00029551 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1337 21:48:57.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1338 21:48:57.891 0.00016079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1339 21:48:57.891 0.00020267 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1340 21:48:57.891 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1341 21:48:57.891 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1342 21:48:57.891 0.00029511 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1343 21:48:57.891 0.00025007 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1344 21:48:57.891 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1345 21:48:57.891 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1346 21:48:57.891 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1347 21:48:57.891 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1348 21:48:57.891 0.00015723 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 1349 21:48:57.891 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1350 21:48:57.891 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1351 21:48:57.891 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1352 21:48:57.891 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1353 21:48:57.891 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1354 21:48:57.891 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1355 21:48:57.891 0.00017936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 1356 21:48:57.891 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1357 21:48:57.891 0.00007111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1358 21:48:57.891 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1359 21:48:57.891 0.00020464 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1360 21:48:57.891 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1361 21:48:57.891 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1362 21:48:57.891 0.00011220 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1363 21:48:57.891 0.00015012 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1364 21:48:57.891 0.00006756 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1365 21:48:57.891 0.00026746 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1366 21:48:57.891 0.00018805 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1367 21:48:57.891 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1368 21:48:57.891 0.00005965 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1369 21:48:57.891 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1370 21:48:57.891 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1371 21:48:57.891 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1372 21:48:57.891 0.00005689 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1373 21:48:57.891 0.00009244 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1374 21:48:57.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1375 21:48:57.891 0.00006440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1376 21:48:57.891 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1377 21:48:57.891 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1378 21:48:57.891 0.00013788 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1379 21:48:57.891 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1380 21:48:57.891 0.00017225 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1381 21:48:57.891 0.00020346 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1382 21:48:57.891 0.00004267 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1383 21:48:57.891 0.00008928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1384 21:48:57.891 0.00010904 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1385 21:48:57.891 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1386 21:48:57.891 0.00019595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1387 21:48:57.891 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1388 21:48:57.891 0.00002726 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1389 21:48:57.891 0.00016356 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1390 21:48:57.891 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1391 21:48:57.891 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1392 21:48:57.891 0.02707517 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1393 21:48:57.922 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1394 21:48:57.922 0.01330568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1395 21:48:57.922 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1396 21:48:57.938 0.00029590 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1397 21:48:57.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1398 21:48:57.938 0.00038519 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1399 21:48:57.938 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1400 21:48:57.938 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1401 21:48:57.938 0.00021452 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1402 21:48:57.938 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1403 21:48:57.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1404 21:48:57.938 0.00041086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1405 21:48:57.938 0.00042311 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1406 21:48:57.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1407 21:48:57.938 0.00024928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1408 21:48:57.938 0.00021531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1409 21:48:57.938 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1410 21:48:57.938 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1411 21:48:57.938 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1412 21:48:57.938 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1413 21:48:57.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1414 21:48:57.938 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1415 21:48:57.938 0.00012010 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1416 21:48:57.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1417 21:48:57.938 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1418 21:48:57.938 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1419 21:48:57.938 0.00017027 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1420 21:48:57.938 0.00020346 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1421 21:48:57.938 0.00012721 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1422 21:48:57.938 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1423 21:48:57.938 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1424 21:48:57.938 0.00013393 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1425 21:48:57.938 0.00008612 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1426 21:48:57.938 0.00006953 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1427 21:48:57.938 0.00009402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1428 21:48:57.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1429 21:48:57.938 0.00009956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1430 21:48:57.938 0.00013788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1431 21:48:57.938 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1432 21:48:57.938 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1433 21:48:57.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1434 21:48:57.938 0.00141748 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1435 21:48:57.938 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1436 21:48:57.938 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1437 21:48:57.938 0.00018528 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1438 21:48:57.938 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1439 21:48:57.938 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1440 21:48:57.938 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1441 21:48:57.938 0.00006558 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1442 21:48:57.938 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1443 21:48:57.938 0.00003477 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1444 21:48:57.938 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1445 21:48:57.938 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1446 21:48:57.938 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1447 21:48:57.938 0.00009719 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1448 21:48:57.938 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1449 21:48:57.938 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1450 21:48:57.938 0.00001264 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1451 21:48:57.938 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1452 21:48:57.938 0.00018173 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1453 21:48:57.938 0.00011022 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1454 21:48:57.938 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1455 21:48:57.938 0.00006242 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1456 21:48:57.938 0.00016119 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1457 21:48:57.938 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1458 21:48:57.938 0.02506115 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1459 21:48:57.969 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1460 21:48:57.969 0.01469591 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1461 21:48:57.969 0.00001383 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1462 21:48:57.985 0.00036109 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1463 21:48:57.985 0.00024454 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1464 21:48:57.985 0.00006400 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1465 21:48:57.985 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1466 21:48:57.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1467 21:48:57.985 0.00015368 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1468 21:48:57.985 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1469 21:48:57.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1470 21:48:57.985 0.00022440 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1471 21:48:57.985 0.00021610 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1472 21:48:57.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1473 21:48:57.985 0.00026469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1474 21:48:57.985 0.00023822 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1475 21:48:57.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1476 21:48:57.985 0.00032198 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1477 21:48:57.985 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1478 21:48:57.985 0.00024020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 1479 21:48:57.985 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1480 21:48:57.985 0.00017343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1481 21:48:57.985 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1482 21:48:57.985 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 06 1483 21:48:57.985 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1484 21:48:57.985 0.00028207 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1485 21:48:57.985 0.00033738 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1486 21:48:57.985 0.00007625 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1487 21:48:57.985 0.00024928 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 1488 21:48:57.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1489 21:48:57.985 0.00022163 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1490 21:48:57.985 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1491 21:48:57.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1492 21:48:57.985 0.00009363 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1493 21:48:57.985 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1494 21:48:57.985 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1495 21:48:57.985 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1496 21:48:57.985 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1497 21:48:57.985 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1498 21:48:57.985 0.00003160 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1499 21:48:57.985 0.00008257 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1500 21:48:57.985 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1501 21:48:57.985 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1502 21:48:57.985 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1503 21:48:57.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1504 21:48:57.985 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1505 21:48:57.985 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1506 21:48:57.985 0.00006519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1507 21:48:57.985 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1508 21:48:57.985 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1509 21:48:57.985 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1510 21:48:57.985 0.00003200 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1511 21:48:57.985 0.00012089 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1512 21:48:57.985 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1513 21:48:57.985 0.00011615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1514 21:48:57.985 0.00011891 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1515 21:48:57.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1516 21:48:57.985 0.00004306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1517 21:48:57.985 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1518 21:48:57.985 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1519 21:48:57.985 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1520 21:48:57.985 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1521 21:48:57.985 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1522 21:48:57.985 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1523 21:48:57.985 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1524 21:48:57.985 0.02695310 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1525 21:48:58.016 0.00000632 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1526 21:48:58.016 0.01361818 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1527 21:48:58.016 0.00001699 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1528 21:48:58.032 0.00038558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1529 21:48:58.032 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1530 21:48:58.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1531 21:48:58.032 0.00016909 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1532 21:48:58.032 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1533 21:48:58.032 0.00027891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1534 21:48:58.032 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1535 21:48:58.032 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 1536 21:48:58.032 0.00012523 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1537 21:48:58.032 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1538 21:48:58.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1539 21:48:58.032 0.00024217 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1540 21:48:58.032 0.00025956 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1541 21:48:58.032 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1542 21:48:58.032 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 1543 21:48:58.032 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1547 21:48:58.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1548 21:48:58.032 0.00021886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1549 21:48:58.032 0.00023111 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1550 21:48:58.032 0.00026351 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1551 21:48:58.032 0.00009560 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1552 21:48:58.032 0.00012602 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1553 21:48:58.032 0.00017343 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1554 21:48:58.032 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1555 21:48:58.032 0.00017462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1556 21:48:58.032 0.00036622 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1557 21:48:58.032 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1558 21:48:58.032 0.00023546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1559 21:48:58.032 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1560 21:48:58.032 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1561 21:48:58.032 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1562 21:48:58.032 0.00020820 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1563 21:48:58.032 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1564 21:48:58.032 0.00010311 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1565 21:48:58.032 0.00033225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1566 21:48:58.032 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1567 21:48:58.032 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1568 21:48:58.032 0.00012602 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1569 21:48:58.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1570 21:48:58.032 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1571 21:48:58.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1572 21:48:58.032 0.00027615 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1573 21:48:58.032 0.00021649 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1574 21:48:58.032 0.00015091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1575 21:48:58.032 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1576 21:48:58.032 0.00009481 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1577 21:48:58.032 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1578 21:48:58.032 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1579 21:48:58.032 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1580 21:48:58.032 0.00000119 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1581 21:48:58.032 0.00019161 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1582 21:48:58.032 0.00014459 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1583 21:48:58.032 0.00016158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1584 21:48:58.032 0.00031170 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1585 21:48:58.032 0.00036978 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1586 21:48:58.032 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1587 21:48:58.032 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1588 21:48:58.032 0.00011417 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1589 21:48:58.032 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1590 21:48:58.032 0.02734105 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1591 21:48:58.063 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1592 21:48:58.063 0.01212129 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1593 21:48:58.063 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1594 21:48:58.078 0.00025679 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1595 21:48:58.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1596 21:48:58.078 0.00026193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1597 21:48:58.078 0.00022953 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1598 21:48:58.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1599 21:48:58.078 0.00024731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1600 21:48:58.078 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1601 21:48:58.078 0.00020780 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 40 1602 21:48:58.078 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1603 21:48:58.078 0.00015486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1604 21:48:58.078 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1605 21:48:58.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1606 21:48:58.078 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1607 21:48:58.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1608 21:48:58.078 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1609 21:48:58.078 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 03 1610 21:48:58.078 0.00008573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1611 21:48:58.078 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1612 21:48:58.078 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1613 21:48:58.078 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1614 21:48:58.078 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1615 21:48:58.078 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1616 21:48:58.078 0.00004899 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1617 21:48:58.078 0.00028405 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1618 21:48:58.078 0.00019477 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1619 21:48:58.078 0.00019200 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 1620 21:48:58.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1621 21:48:58.078 0.00015961 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1622 21:48:58.078 0.00030973 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1623 21:48:58.078 0.00024810 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1624 21:48:58.078 0.00004938 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1625 21:48:58.078 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1626 21:48:58.078 0.00021057 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1627 21:48:58.078 0.00014617 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1628 21:48:58.078 0.00021373 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1629 21:48:58.078 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1630 21:48:58.078 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1631 21:48:58.078 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1632 21:48:58.078 0.00023980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1633 21:48:58.078 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1634 21:48:58.078 0.00016395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 01 1635 21:48:58.078 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1636 21:48:58.078 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1637 21:48:58.078 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1638 21:48:58.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1639 21:48:58.078 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1640 21:48:58.078 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1641 21:48:58.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1642 21:48:58.078 0.00013432 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1643 21:48:58.078 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1644 21:48:58.078 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1645 21:48:58.078 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1646 21:48:58.078 0.00017462 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1647 21:48:58.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1648 21:48:58.078 0.00007032 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1649 21:48:58.078 0.00017620 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1650 21:48:58.078 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1651 21:48:58.078 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1652 21:48:58.078 0.00012523 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1653 21:48:58.078 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1654 21:48:58.078 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1655 21:48:58.078 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1656 21:48:58.078 0.02640791 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1657 21:48:58.110 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1658 21:48:58.110 0.01493136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1659 21:48:58.110 0.00001501 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1660 21:48:58.125 0.00023664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1661 21:48:58.125 0.00025442 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1662 21:48:58.125 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1663 21:48:58.125 0.00015289 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1664 21:48:58.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1665 21:48:58.125 0.00061788 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1667 21:48:58.125 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1668 21:48:58.125 0.00018963 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1669 21:48:58.125 0.00015881 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 50 1670 21:48:58.125 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1671 21:48:58.125 0.00004148 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1672 21:48:58.125 0.00010706 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1673 21:48:58.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1674 21:48:58.125 0.00018133 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1675 21:48:58.125 0.00020859 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1676 21:48:58.125 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1677 21:48:58.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1678 21:48:58.125 0.00009284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1679 21:48:58.125 0.00020741 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1680 21:48:58.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1681 21:48:58.125 0.00014578 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1682 21:48:58.125 0.00013274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1683 21:48:58.125 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1684 21:48:58.125 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1685 21:48:58.125 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1686 21:48:58.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1687 21:48:58.125 0.00011062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1688 21:48:58.125 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1689 21:48:58.125 0.00032948 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1691 21:48:58.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1692 21:48:58.125 0.00032277 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1693 21:48:58.125 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1694 21:48:58.125 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1695 21:48:58.125 0.00020306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1696 21:48:58.125 0.00014499 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1697 21:48:58.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1698 21:48:58.125 0.00035674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1699 21:48:58.125 0.00030341 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1700 21:48:58.125 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1701 21:48:58.125 0.00023309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1702 21:48:58.125 0.00020425 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1703 21:48:58.125 0.00022044 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1704 21:48:58.125 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1705 21:48:58.125 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1706 21:48:58.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 1707 21:48:58.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1708 21:48:58.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1711 21:48:58.125 0.00035911 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1712 21:48:58.125 0.00016158 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1713 21:48:58.125 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1714 21:48:58.125 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1715 21:48:58.125 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1716 21:48:58.125 0.00032790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1717 21:48:58.125 0.00023427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1718 21:48:58.125 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: FF 1719 21:48:58.125 0.00012089 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1720 21:48:58.125 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1723 21:48:58.157 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1724 21:48:58.157 0.01327447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1725 21:48:58.157 0.00012128 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1726 21:48:58.172 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1727 21:48:58.172 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1728 21:48:58.172 0.00025600 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1729 21:48:58.172 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1730 21:48:58.172 0.00019714 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1731 21:48:58.172 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1732 21:48:58.172 0.00006677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1733 21:48:58.172 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 60 1734 21:48:58.172 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1735 21:48:58.172 0.00007190 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1736 21:48:58.172 0.00019516 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1737 21:48:58.172 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1738 21:48:58.172 0.00008770 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 04 1739 21:48:58.172 0.00008928 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1740 21:48:58.172 0.00003832 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1741 21:48:58.172 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1742 21:48:58.172 0.00009837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1743 21:48:58.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1744 21:48:58.172 0.00009323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1745 21:48:58.172 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 00 1746 21:48:58.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1747 21:48:58.172 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1748 21:48:58.172 0.00003674 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1749 21:48:58.172 0.00036306 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1751 21:48:58.172 0.00001580 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1752 21:48:58.172 0.00015249 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 1753 21:48:58.172 0.00017106 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1754 21:48:58.172 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1755 21:48:58.172 0.00008099 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1756 21:48:58.172 0.00012010 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1757 21:48:58.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1758 21:48:58.172 0.00025877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1759 21:48:58.172 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1760 21:48:58.172 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1761 21:48:58.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1762 21:48:58.172 0.00008533 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1763 21:48:58.172 0.00016316 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1764 21:48:58.172 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1765 21:48:58.172 0.00012168 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1766 21:48:58.172 0.00011259 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1767 21:48:58.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1768 21:48:58.172 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1769 21:48:58.172 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 01 1770 21:48:58.172 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1771 21:48:58.172 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 1773 21:48:58.172 0.00029788 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1774 21:48:58.172 0.00005017 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1775 21:48:58.172 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 02 1776 21:48:58.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1777 21:48:58.172 0.00012326 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1778 21:48:58.172 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1779 21:48:58.172 0.00014736 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1780 21:48:58.172 0.00015131 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 05 1781 21:48:58.172 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1782 21:48:58.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1783 21:48:58.172 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1784 21:48:58.172 0.00013946 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1785 21:48:58.172 0.00005728 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1786 21:48:58.172 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1787 21:48:58.172 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1788 21:48:58.172 0.02667458 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1789 21:48:58.204 0.00002331 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1790 21:48:58.204 0.01446361 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1791 21:48:58.204 0.00003753 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1792 21:48:58.219 0.00033817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1793 21:48:58.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1794 21:48:58.219 0.00041640 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1795 21:48:58.219 0.00031684 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1796 21:48:58.219 0.00029827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1797 21:48:58.219 0.00016948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1798 21:48:58.219 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1799 21:48:58.219 0.00010746 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1800 21:48:58.219 0.00022321 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 70 1801 21:48:58.219 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1802 21:48:58.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1803 21:48:58.219 0.00019793 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1804 21:48:58.219 0.00022084 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1805 21:48:58.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1806 21:48:58.219 0.00021570 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1807 21:48:58.219 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1808 21:48:58.219 0.00016790 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1809 21:48:58.219 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1810 21:48:58.219 0.00012563 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1811 21:48:58.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1812 21:48:58.219 0.00026627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1813 21:48:58.219 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1814 21:48:58.219 0.00006716 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1815 21:48:58.219 0.00035753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1816 21:48:58.219 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1817 21:48:58.219 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1818 21:48:58.219 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1819 21:48:58.219 0.00016948 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0E 1820 21:48:58.219 0.00002015 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1821 21:48:58.219 0.00019319 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1823 21:48:58.219 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1824 21:48:58.219 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1825 21:48:58.219 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1826 21:48:58.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1827 21:48:58.219 0.00026548 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1828 21:48:58.219 0.00021491 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1829 21:48:58.219 0.00022400 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1830 21:48:58.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1831 21:48:58.219 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1832 21:48:58.219 0.00014380 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1833 21:48:58.219 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1834 21:48:58.219 0.00013274 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1835 21:48:58.219 0.00016356 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1836 21:48:58.219 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1837 21:48:58.219 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1838 21:48:58.219 0.00018884 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 00 1839 21:48:58.219 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1840 21:48:58.219 0.00008138 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1841 21:48:58.219 0.00018607 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1842 21:48:58.219 0.00000553 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1843 21:48:58.219 0.00015447 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1844 21:48:58.219 0.00017422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1845 21:48:58.219 0.00006321 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1846 21:48:58.219 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1847 21:48:58.219 0.00019042 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1848 21:48:58.219 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1849 21:48:58.219 0.00011220 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1850 21:48:58.219 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 1851 21:48:58.219 0.00009640 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1852 21:48:58.219 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1853 21:48:58.219 0.00002884 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1854 21:48:58.219 0.02551586 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1855 21:48:58.251 0.00002489 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1856 21:48:58.251 0.02981651 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1857 21:48:58.251 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1858 21:48:58.281 0.00039506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1859 21:48:58.281 0.00002647 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1860 21:48:58.281 0.00043062 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1861 21:48:58.281 0.00035635 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1862 21:48:58.281 0.00024494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1863 21:48:58.281 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1864 21:48:58.281 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1865 21:48:58.281 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 80 1866 21:48:58.281 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1867 21:48:58.281 0.00028049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1868 21:48:58.281 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1869 21:48:58.281 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1870 21:48:58.281 0.00013353 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1871 21:48:58.281 0.00012326 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1872 21:48:58.281 0.00012247 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1873 21:48:58.281 0.00008731 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1874 21:48:58.281 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1875 21:48:58.281 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1876 21:48:58.281 0.00009126 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1877 21:48:58.281 0.00009956 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1878 21:48:58.281 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1879 21:48:58.281 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1880 21:48:58.281 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1881 21:48:58.281 0.00015091 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1882 21:48:58.281 0.00015763 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1883 21:48:58.281 0.00009758 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1884 21:48:58.281 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1885 21:48:58.281 0.00013630 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1886 21:48:58.281 0.00015921 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1887 21:48:58.281 0.00013393 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1888 21:48:58.281 0.00021096 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1889 21:48:58.281 0.00010825 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1890 21:48:58.281 0.00019437 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1891 21:48:58.281 0.00009600 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1892 21:48:58.281 0.00002765 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1893 21:48:58.281 0.00018449 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1894 21:48:58.281 0.00006637 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1895 21:48:58.281 0.00002923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1896 21:48:58.281 0.00015565 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1897 21:48:58.281 0.00022361 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1898 21:48:58.281 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1899 21:48:58.281 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1900 21:48:58.281 0.00014736 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1901 21:48:58.281 0.00022874 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1902 21:48:58.281 0.00013906 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1903 21:48:58.281 0.00025402 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1904 21:48:58.281 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1905 21:48:58.281 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1906 21:48:58.281 0.00019872 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1907 21:48:58.281 0.00022519 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1908 21:48:58.281 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1909 21:48:58.281 0.00018489 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1910 21:48:58.281 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1911 21:48:58.281 0.00007862 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1912 21:48:58.281 0.00015842 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1913 21:48:58.281 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1914 21:48:58.281 0.00010035 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1915 21:48:58.281 0.00001817 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1916 21:48:58.281 0.02721818 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1917 21:48:58.313 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1918 21:48:58.313 0.01383309 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1919 21:48:58.313 0.00001185 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1920 21:48:58.328 0.00047486 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1921 21:48:58.328 0.00000948 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1922 21:48:58.328 0.00041284 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1923 21:48:58.328 0.00027694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1924 21:48:58.328 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1925 21:48:58.328 0.00017857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1926 21:48:58.328 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1927 21:48:58.328 0.00006163 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1928 21:48:58.328 0.00047052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 90 1929 21:48:58.328 0.00038677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1930 21:48:58.328 0.00033541 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1931 21:48:58.328 0.00016237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1932 21:48:58.328 0.00019516 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1933 21:48:58.328 0.00017817 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 57 1934 21:48:58.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1935 21:48:58.328 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1936 21:48:58.328 0.00027101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 1937 21:48:58.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1938 21:48:58.328 0.00008178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1939 21:48:58.328 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1940 21:48:58.328 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4C 1941 21:48:58.328 0.00019951 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1942 21:48:58.328 0.00015447 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 43 1943 21:48:58.328 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1944 21:48:58.328 0.00006598 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1945 21:48:58.328 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1946 21:48:58.328 0.00020701 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4F 1947 21:48:58.328 0.00024178 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1948 21:48:58.328 0.00022123 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4D 1949 21:48:58.328 0.00009007 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1950 21:48:58.328 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1951 21:48:58.328 0.00021807 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 45 1952 21:48:58.328 0.00012642 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1953 21:48:58.328 0.00008296 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1954 21:48:58.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1955 21:48:58.328 0.00020820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1956 21:48:58.328 0.00017146 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1957 21:48:58.328 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1958 21:48:58.328 0.00003002 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1959 21:48:58.328 0.00011417 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1960 21:48:58.328 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1961 21:48:58.328 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1962 21:48:58.328 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1963 21:48:58.328 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1964 21:48:58.328 0.00017185 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1965 21:48:58.328 0.00021531 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1966 21:48:58.328 0.00002252 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1967 21:48:58.328 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1968 21:48:58.328 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1969 21:48:58.328 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1970 21:48:58.328 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1971 21:48:58.328 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1972 21:48:58.328 0.00007506 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1973 21:48:58.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1974 21:48:58.328 0.00005649 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1975 21:48:58.328 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1976 21:48:58.328 0.00013669 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1977 21:48:58.328 0.00016751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1978 21:48:58.328 0.00011259 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1979 21:48:58.328 0.00024573 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 1980 21:48:58.328 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1981 21:48:58.328 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1982 21:48:58.328 0.02592515 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1983 21:48:58.360 0.00000751 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1984 21:48:58.360 0.01482944 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1985 21:48:58.360 0.00006519 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 1986 21:48:58.376 0.00025126 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 1987 21:48:58.376 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1988 21:48:58.376 0.00032751 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1989 21:48:58.376 0.00026469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 1990 21:48:58.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1991 21:48:58.376 0.00049304 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1992 21:48:58.376 0.00039664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 1993 21:48:58.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1994 21:48:58.376 0.00014025 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: A0 1995 21:48:58.376 0.00017422 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1996 21:48:58.376 0.00015407 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 1997 21:48:58.376 0.00016395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 1998 21:48:58.376 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 1999 21:48:58.376 0.00025086 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2000 21:48:58.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2001 21:48:58.376 0.00023585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2002 21:48:58.376 0.00012958 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2003 21:48:58.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2004 21:48:58.376 0.00014973 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2005 21:48:58.376 0.00013985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2006 21:48:58.376 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2007 21:48:58.376 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2008 21:48:58.376 0.00012405 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2009 21:48:58.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2010 21:48:58.376 0.00011378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2011 21:48:58.376 0.00020267 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2012 21:48:58.376 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2013 21:48:58.376 0.00014301 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2014 21:48:58.376 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 20 2015 21:48:58.376 0.00008652 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2021 21:48:58.376 0.00003595 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2022 21:48:58.376 0.00010469 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2023 21:48:58.376 0.00011101 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2024 21:48:58.376 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2025 21:48:58.376 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2026 21:48:58.376 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2027 21:48:58.376 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2028 21:48:58.376 0.00001778 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2029 21:48:58.376 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2030 21:48:58.376 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2031 21:48:58.376 0.00012286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2032 21:48:58.376 0.00014657 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2033 21:48:58.376 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2034 21:48:58.376 0.00005136 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2035 21:48:58.376 0.00001659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2036 21:48:58.376 0.00019911 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2037 21:48:58.376 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2038 21:48:58.376 0.00012642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2039 21:48:58.376 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2040 21:48:58.376 0.00001462 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2041 21:48:58.376 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2042 21:48:58.376 0.00018923 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2043 21:48:58.376 0.00018133 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2044 21:48:58.376 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2045 21:48:58.376 0.00014341 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2046 21:48:58.376 0.00014775 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2047 21:48:58.376 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2048 21:48:58.376 0.02722767 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2049 21:48:58.407 0.00002963 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2050 21:48:58.407 0.02856574 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2051 21:48:58.407 0.00000316 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2052 21:48:58.438 0.00037965 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2053 21:48:58.438 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2054 21:48:58.438 0.00031802 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2055 21:48:58.438 0.00025837 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2056 21:48:58.438 0.00001541 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2058 21:48:58.438 0.00025758 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 2059 21:48:58.438 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2060 21:48:58.438 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2061 21:48:58.438 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: B0 2062 21:48:58.438 0.00015407 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2063 21:48:58.438 0.00037886 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2064 21:48:58.438 0.00026193 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2065 21:48:58.438 0.00018331 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2066 21:48:58.438 0.00010588 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2067 21:48:58.438 0.00009521 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2068 21:48:58.438 0.00032395 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2069 21:48:58.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2070 21:48:58.438 0.00019793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2071 21:48:58.438 0.00017778 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2072 21:48:58.438 0.00003951 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2073 21:48:58.438 0.00018568 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2074 21:48:58.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2075 21:48:58.438 0.00016000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2076 21:48:58.438 0.00015210 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2077 21:48:58.438 0.00019674 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2078 21:48:58.438 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2079 21:48:58.438 0.00011773 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2080 21:48:58.438 0.00029985 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2081 21:48:58.438 0.00019714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2082 21:48:58.438 0.00016790 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2083 21:48:58.438 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2084 21:48:58.438 0.00052780 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2085 21:48:58.438 0.00045274 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2086 21:48:58.438 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2087 21:48:58.438 0.00027891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2088 21:48:58.438 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 20 2089 21:48:58.438 0.00025995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 4B 2090 21:48:58.438 0.00008336 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2091 21:48:58.438 0.00012998 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2092 21:48:58.438 0.00013827 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 54 2093 21:48:58.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2094 21:48:58.438 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2095 21:48:58.438 0.00029235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 2D 2096 21:48:58.438 0.00016593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2097 21:48:58.438 0.00012128 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 37 2098 21:48:58.438 0.00012958 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2099 21:48:58.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2100 21:48:58.438 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2101 21:48:58.438 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 39 2102 21:48:58.438 0.00004701 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2103 21:48:58.438 0.00009877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2104 21:48:58.438 0.00011733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 2105 21:48:58.438 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2106 21:48:58.438 0.00003042 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2107 21:48:58.438 0.00003516 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2108 21:48:58.438 0.00020425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2109 21:48:58.438 0.00023664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 30 2110 21:48:58.438 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 44 2111 21:48:58.438 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2112 21:48:58.438 0.00012365 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2113 21:48:58.438 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2114 21:48:58.438 0.02456811 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2115 21:48:58.469 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2116 21:48:58.469 0.01479349 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2117 21:48:58.469 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2118 21:48:58.484 0.00039664 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2119 21:48:58.484 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2120 21:48:58.484 0.00082212 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2121 21:48:58.484 0.00069531 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2122 21:48:58.484 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2123 21:48:58.484 0.00031486 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2124 21:48:58.484 0.00022281 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 2125 21:48:58.484 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2126 21:48:58.484 0.00032395 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2127 21:48:58.484 0.00021215 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: C0 2128 21:48:58.484 0.00026074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2129 21:48:58.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2130 21:48:58.484 0.00021728 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2131 21:48:58.484 0.00000435 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2132 21:48:58.484 0.00024375 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2133 21:48:58.484 0.00031012 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2134 21:48:58.484 0.00005886 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2135 21:48:58.484 0.00026588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2136 21:48:58.484 0.00025877 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2137 21:48:58.484 0.00017225 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2138 21:48:58.484 0.00006005 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2139 21:48:58.484 0.00014894 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2140 21:48:58.484 0.00008494 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2141 21:48:58.484 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2142 21:48:58.484 0.00006914 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2143 21:48:58.484 0.00016988 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2144 21:48:58.484 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2145 21:48:58.484 0.00006360 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2146 21:48:58.484 0.00014183 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2147 21:48:58.484 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2148 21:48:58.484 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2149 21:48:58.484 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2150 21:48:58.484 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2151 21:48:58.484 0.00011141 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2152 21:48:58.484 0.00023427 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2153 21:48:58.484 0.00010785 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2154 21:48:58.484 0.00015328 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2155 21:48:58.484 0.00011773 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2156 21:48:58.484 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2157 21:48:58.484 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2158 21:48:58.484 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2159 21:48:58.484 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2160 21:48:58.484 0.00009995 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2161 21:48:58.484 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2162 21:48:58.484 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2163 21:48:58.484 0.00007506 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2164 21:48:58.484 0.00014696 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2165 21:48:58.484 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2166 21:48:58.484 0.00007980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2167 21:48:58.484 0.00011457 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2168 21:48:58.484 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2169 21:48:58.484 0.00008415 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2170 21:48:58.484 0.00008020 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2171 21:48:58.484 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2172 21:48:58.484 0.00003793 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2173 21:48:58.484 0.00014420 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2174 21:48:58.484 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2175 21:48:58.484 0.00004820 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2176 21:48:58.484 0.00013867 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2177 21:48:58.484 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2178 21:48:58.484 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2179 21:48:58.484 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2180 21:48:58.484 0.02733631 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2181 21:48:58.516 0.00000711 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2182 21:48:58.516 0.01343092 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2183 21:48:58.516 0.00000237 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2184 21:48:58.532 0.00021412 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2185 21:48:58.532 0.00006123 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2186 21:48:58.532 0.00044286 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2187 21:48:58.532 0.00029748 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2188 21:48:58.532 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2189 21:48:58.532 0.00041323 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2190 21:48:58.532 0.00031091 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 2191 21:48:58.532 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2192 21:48:58.532 0.00029985 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2193 21:48:58.532 0.00022361 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: D0 2194 21:48:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2195 21:48:58.532 0.00027891 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2196 21:48:58.532 0.00016672 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2197 21:48:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2198 21:48:58.532 0.00027378 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2199 21:48:58.532 0.00021175 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2200 21:48:58.532 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2201 21:48:58.532 0.00036306 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2202 21:48:58.532 0.00035398 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2203 21:48:58.532 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2204 21:48:58.532 0.00003872 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2205 21:48:58.532 0.00011812 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2206 21:48:58.532 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2207 21:48:58.532 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2208 21:48:58.532 0.00006795 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2209 21:48:58.532 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2210 21:48:58.532 0.00018252 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2211 21:48:58.532 0.00014538 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2212 21:48:58.532 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2213 21:48:58.532 0.00018212 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2214 21:48:58.532 0.00019398 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2215 21:48:58.532 0.00013077 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2216 21:48:58.532 0.00008573 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2217 21:48:58.532 0.00007585 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2218 21:48:58.532 0.00013037 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2219 21:48:58.532 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2220 21:48:58.532 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2221 21:48:58.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2222 21:48:58.532 0.00023664 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2223 21:48:58.532 0.00023467 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2224 21:48:58.532 0.00010706 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2225 21:48:58.532 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2226 21:48:58.532 0.00006202 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2227 21:48:58.532 0.00010074 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2228 21:48:58.532 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2229 21:48:58.532 0.00009205 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2230 21:48:58.532 0.00007546 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2231 21:48:58.532 0.00010667 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2232 21:48:58.532 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2233 21:48:58.532 0.00001343 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2234 21:48:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2235 21:48:58.532 0.00001738 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2236 21:48:58.532 0.00014262 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2237 21:48:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2238 21:48:58.532 0.00005175 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2239 21:48:58.532 0.00008375 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2240 21:48:58.532 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2241 21:48:58.532 0.00004425 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2242 21:48:58.532 0.00012049 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2243 21:48:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2244 21:48:58.532 0.00005768 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2245 21:48:58.532 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2246 21:48:58.532 0.02869413 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2247 21:48:58.563 0.00002212 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2248 21:48:58.563 0.01269413 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2249 21:48:58.563 0.00002212 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2250 21:48:58.578 0.00048079 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2251 21:48:58.578 0.00001699 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2252 21:48:58.578 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 2253 21:48:58.578 0.00000000 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 Length: 1, Data: 58 2257 21:48:58.578 0.00019753 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: E0 2258 21:48:58.578 0.00001857 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2259 21:48:58.578 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2260 21:48:58.578 0.00018410 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2261 21:48:58.578 0.00021057 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2262 21:48:58.578 0.00008770 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2263 21:48:58.578 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2264 21:48:58.578 0.00020741 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2265 21:48:58.578 0.00014222 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2266 21:48:58.578 0.00010785 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2267 21:48:58.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2268 21:48:58.578 0.00001936 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2269 21:48:58.578 0.00049936 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2270 21:48:58.578 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2271 21:48:58.578 0.00045946 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2272 21:48:58.578 0.00004583 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2273 21:48:58.578 0.00019990 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2274 21:48:58.578 0.00026943 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2275 21:48:58.578 0.00015052 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2276 21:48:58.578 0.00012840 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2277 21:48:58.578 0.00003358 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2278 21:48:58.578 0.00028444 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2279 21:48:58.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2280 21:48:58.578 0.00013669 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2281 21:48:58.578 0.00025916 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2282 21:48:58.578 0.00004188 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2284 21:48:58.578 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2285 21:48:58.578 0.00017027 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2286 21:48:58.578 0.00009798 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2287 21:48:58.578 0.00011575 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2288 21:48:58.578 0.00006479 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2289 21:48:58.578 0.00009086 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2290 21:48:58.578 0.00008178 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2291 21:48:58.578 0.00013235 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2292 21:48:58.578 0.00000395 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2293 21:48:58.578 0.00001501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2294 21:48:58.578 0.00010548 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2295 21:48:58.578 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2296 21:48:58.578 0.00002449 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2297 21:48:58.578 0.00010232 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2298 21:48:58.578 0.00000158 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2299 21:48:58.578 0.00007704 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2300 21:48:58.578 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2301 21:48:58.578 0.00017501 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2302 21:48:58.578 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2303 21:48:58.578 0.00003714 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2304 21:48:58.578 0.00027259 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2305 21:48:58.578 0.00027733 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2306 21:48:58.578 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2307 21:48:58.578 0.00016711 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2308 21:48:58.578 0.00014104 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2309 21:48:58.578 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2310 21:48:58.578 0.02554115 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2311 21:48:58.610 0.00000672 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2312 21:48:58.610 0.01529917 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2313 21:48:58.610 0.00003279 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2314 21:48:58.626 0.00028642 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 06 2315 21:48:58.626 0.00000474 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2316 21:48:58.626 0.00018923 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2317 21:48:58.626 0.00013314 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 58 2318 21:48:58.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2319 21:48:58.626 0.00016040 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2320 21:48:58.626 0.00013709 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 0F 2321 21:48:58.626 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2322 21:48:58.626 0.00039980 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2323 21:48:58.626 0.00033422 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: F0 2324 21:48:58.626 0.00017975 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: 10 2325 21:48:58.626 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2326 21:48:58.626 0.00019674 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2327 21:48:58.626 0.00014143 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2328 21:48:58.626 0.00000237 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2329 21:48:58.626 0.00013037 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2330 21:48:58.626 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2331 21:48:58.626 0.00011812 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2332 21:48:58.626 0.00017383 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2333 21:48:58.626 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2334 21:48:58.626 0.00021254 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2335 21:48:58.626 0.00014301 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2336 21:48:58.626 0.00013353 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2337 21:48:58.626 0.00001975 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2338 21:48:58.626 0.00007230 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2339 21:48:58.626 0.00005373 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2340 21:48:58.626 0.00020938 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2341 21:48:58.626 0.00017067 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2342 21:48:58.626 0.00009640 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2343 21:48:58.626 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2344 21:48:58.626 0.00004978 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2345 21:48:58.626 0.00014933 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2346 21:48:58.626 0.00000356 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2347 21:48:58.626 0.00005215 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2348 21:48:58.626 0.00000000 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2350 21:48:58.626 0.00011180 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2351 21:48:58.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2352 21:48:58.626 0.00010469 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2353 21:48:58.626 0.00014420 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2354 21:48:58.626 0.00021926 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2355 21:48:58.626 0.00016514 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2356 21:48:58.626 0.00007072 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2357 21:48:58.626 0.00010272 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2358 21:48:58.626 0.00015170 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2359 21:48:58.626 0.00007822 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2360 21:48:58.626 0.00022558 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2361 21:48:58.626 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2362 21:48:58.626 0.00013195 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2363 21:48:58.626 0.00004069 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2364 21:48:58.626 0.00012049 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2365 21:48:58.626 0.00010153 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2366 21:48:58.626 0.00001146 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2367 21:48:58.626 0.00022677 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2368 21:48:58.626 0.00013432 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2369 21:48:58.626 0.00010588 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2370 21:48:58.626 0.00000198 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2371 21:48:58.626 0.00010627 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2372 21:48:58.626 0.00011694 UV4BAND_E_CPS. IRP_MJ_WRITE COM1 SUCCESS Length: 1, Data: FF 2373 21:48:58.626 0.00000316 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2374 21:48:58.626 0.00007427 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2375 21:48:58.626 0.00000277 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2376 21:48:58.626 0.02698312 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2377 21:48:58.657 0.00000593 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: RXCHAR TXEMPTY CTS DSR RLSD BREAK ERR RING 2378 21:48:58.657 0.00042272 UV4BAND_E_CPS. IOCTL_SERIAL_WAIT_ON_MASK COM1 SUCCESS 2379 21:48:58.657 0.00000277 UV4BAND_E_CPS. IRP_MJ_READ COM1 SUCCESS Length: 1, Data: 06 2380 21:48:58.657 0.00017659 UV4BAND_E_CPS. IOCTL_SERIAL_SET_WAIT_MASK COM1 SUCCESS Mask: 2381 21:48:58.657 0.00018647 UV4BAND_E_CPS. IOCTL_SERIAL_CLR_DTR COM1 SUCCESS 2382 21:48:58.657 0.00006993 UV4BAND_E_CPS. IOCTL_SERIAL_PURGE COM1 SUCCESS Purge: TXABORT RXABORT TXCLEAR RXCLEAR 2383 21:48:58.657 0.01677156 UV4BAND_E_CPS. IRP_MJ_CLOSE COM1 SUCCESS Port Closed