CHIRP

It look like CHIRP only supports 2 power levels fot the RT86. After using the OEM software V1.2 it appears there are 3 levels. Low/Med/Hi and therefore the TX power has 2 bits allocated. So more like :-
MEM_FORMAT_RT86 = """
#seekto 0x0000;
struct {
lbcd rxfreq[4]; // RX Frequency 0-3
lbcd txfreq[4]; // TX Frequency 4-7
ul16 rx_tone; // PL/DPL Decode 8-9
ul16 tx_tone; // PL/DPL Encode A-B
u8 audio:2, // Audio 00=off 01=Scramble 10=Compand C
highpower:2, // Power Level 00=Low 01=Med 10=High
bcl:1, // Busy Lock OFF=0 ON=1
scramble_type:3; // Scramble 0=1 7=8
u8 reserved[3]; // Reserved D-F
} memory[16];

The different power setting have an effect on the radio display by showing 1-4 bars depending on the power setting and a lo setting shows "lo" on the radio.

The reserved 3 u8 at the end appear to be used in blocks for other features like Wide/Narrow. I have completed some hex comparisons to look into the further. I believe the current driver already maps some of these.
offset 4d defines the frequency range 02=400MHz-480MHz
offset 4E has 16 bits mapping "scan add" for each channel ie FFFF=all channels Del
offset 8d has 16 bits mapping the W/N for each channel ie FFFF=all channels wide
offset ad has 16 bits mapping Spec on/off for each channel
offset 100 16 x u8 containing the Frequency hop from Mode1-Mode4 00=off
offset 160 16 x 32 bits for the Spec codes

There are 2 attached data files one "base" and the other "mapping". I have also included screen shot of the OEM screen that matches the files.